JPS63115364A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent latch-up due to a parasitic transistor by providing a CMOSIC wherein a low resistance in formed across a resistor between the parasitic transistor base and a high voltage source terminal so that the equivalent base resistance can be decreased. CONSTITUTION:A recess is formed in a semiconductor substrate 1 between the MOS-type field effect transistors of the channels different from each other constituting a CMOSIC. And on this recess, a high-concentration impurity region 23 of the same conductivity type as the semiconductor substrate is formed, a conductive electrode 24 is made on the high-concentration impurity region, and the conductive electrode 24 is connected to a power supply 20 of the CMOSIC. This result in a low resistance newly made between the high-potential power supply and the low-concentration P-type impurity region, and the parasitic resistance due to the semiconductor substrate connecting between the base and the emitter of parasitic transistor becomes equivalently small. Also, since the base width of the parasitic transistor using the semiconductor substrate as the base region become wide thereby making the current amplification factor small, the latch-up phenomenon becomes difficult to occur.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a complementary MO5 integrated circuit (hereinafter referred to as CMOSIC2B-7).

BACKGROUND OF THE INVENTION In recent years, with the digitization of electronic equipment, MOS type semiconductor integrated circuits have been increasingly used. Among MOS type semiconductor integrated circuits, 0MOSICs, which consume less power, account for a high proportion.

FIG. 2 shows a cross-sectional view of the structure of a conventional 0MOSIC.

A low concentration P type impurity region 2 and a source region 4 and drain region 3 of a P channel transistor, which are high concentration P type impurity regions, are formed on a low concentration N type semiconductor substrate 1. A source region and a drain region 8 of an N-channel transistor, which are heavily doped N-type impurity regions, are formed in the region. A conductive electrode 12 is formed on a gate oxide film 9 that connects the source region 4 and drain region 3 of the P-channel transistor, and a conductive electrode 12 is formed on the gate oxide film 1o that connects the source region 7 and the drain region 8 of the N-channel transistor. A conductive electrode 17 is formed. Furthermore, the electrically conductive electrode 12.17 is connected to the input terminal 22. A conductive electrode 11 is formed on the drain region 3 of the P-channel transistor 3, a conductive electrode 18 is formed on the drain region 8 of the N-channel transistor, and the conductive electrode 11.18 is connected to the output terminal 19. It is connected to the.

A conductive electrode 13 is formed on the source region 4 of the P-channel transistor, and a conductive electrode 14 is formed on the heavily doped N-type impurity region 5 provided on the N-type semiconductor substrate 1. The sexual electrodes 13 and 14 are high potential power terminals 2o
It is connected to the. A conductive electrode 16 is formed on the source region 7 of the N-channel transistor, and a conductive electrode 15 is formed on the high concentration P-type impurity region 6 provided on the low concentration P-type impurity region 2. Electrodes 15 , 16 are connected to low potential power terminal 21 .

Problems to be Solved by the Invention However, the conventional device has a drawback in that a latch-up phenomenon due to parasitic elements is likely to occur. Below, we will explain this latch amplifier phenomenon using the third electrically equivalent circuit shown in Figure 2.
This will be explained using figures. The parasitic transistor Q1 is formed by the source region 4 of the P-channel transistor, the N-type semiconductor substrate 1, and the low concentration P-type impurity region 2, and the parasitic transistor Q2 is formed by the drain region 3 of the P-channel transistor, the N-type semiconductor substrate 1, and the low concentration P-type impurity region 2. type impurity region 2, the parasitic transistor Q3 is formed by the source region 7 of the N-channel transistor, the low concentration P-type impurity region 2, and the N-type semiconductor substrate 1, and the parasitic transistor Q4 is formed by the drain region 8 of the N-channel transistor,
It is formed by a low concentration P type impurity region 2 and an N type semiconductor substrate 1. R1, R3, and R5 are resistances due to the N-type semiconductor substrate 1, and R2, R4, and R6 are resistances due to the low concentration P-type impurity region 2. Parasitic transistor Q1. Q3 constitutes a thyristor.

In the electrical equivalent circuit of FIG. 3 described above, an overcurrent flows into the output terminal 19, and the parasitic transistor Q2 is turned on.
Then, the collector current of this parasitic transistor Q2 flows to the low potential power supply terminal 21 through the resistors R6 and R4. At this time, the voltage generated across the resistor R4 is the parasitic transistor Q
If the base-to-mitter forward voltage is larger than the base-to-mitter forward voltage of 5, the parasitic transistor Q3 is ONL, and the collector current of the parasitic transistor Q3 flows from the high potential power supply terminal 2o through the resistors R1 and R3. Furthermore, the voltage generated across the resistor R1 due to the collector current of the parasitic transistor Q3 is
1, the parasitic transistor Q1 turns on, and the parasitic transistors Q1, Q
The thyristor constituted by 3 is turned on, and an overcurrent flows until the high potential power supply terminal 20 or the low potential power supply terminal 21 is opened, and the element is finally destroyed by heat. Further, when an overcurrent flows out from the output terminal 19 and the parasitic transistor Q4 is turned on, a current flows from the high potential power supply terminal 20 through the resistor RI R5 to the collector of the parasitic transistor Q4.

At this time, if the voltage generated across the resistor R1 is larger than the forward voltage between the emitter and base of the parasitic transistor Q1, the parasitic transistor Q1 is turned on, and the parasitic transistor Q1
The collector current of passes through the resistor R2゜R4 and is connected to the low potential power supply 21.
flows to Furthermore, 6, ;-.

If the voltage generated across the resistor R4 due to the collector current of the parasitic transistor Q1 is greater than the forward voltage between the base and emitter of the parasitic transistor Q3, the parasitic transistor Q
3 turns ON, and the SIRISK made up of parasitic transistors Q1 and Q3 turns ON, and an overcurrent flows until the high potential power supply terminals 20, 4 or the low potential power supply terminal 21 are turned on in the same way as described above. The heat destroys the element.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention forms recesses in a semiconductor substrate between MOS field effect transistors with different channels constituting an OMOSIC, and forms a recess on the recess. A high concentration impurity region of the same conductivity type as the semiconductor substrate is formed, a conductive electrode is formed on the high concentration impurity region, and the conductive electrode is connected to the power source of the 0MOSIC.

Operation The present invention creates a new low resistance between the high potential power supply and the low concentration P-type impurity region due to the above-described structure, thereby reducing the base emitter of the parasitic transistor.

This effectively reduces the parasitic resistance caused by the semiconductor substrate that connects the semiconductor substrate, and the base width of the parasitic transistor that uses the semiconductor substrate as a base region becomes wider, which reduces the current amplification factor, making it difficult for latch-up to occur.

Example The present invention will be explained according to an embodiment using the drawings.

FIG. 1 is a sectional view of an aMos process a showing an embodiment of the present invention. Low concentration P type impurity region 2 on N type semiconductor substrate 1
Then, a source region 4 and a drain region 3 of a P channel transistor, which are high concentration P type impurity regions, are formed. Then, on the lightly doped P type impurity region 2, a source region 7, a drain region 8, and a heavily doped P type impurity region 6 of the N channel transistor, which are heavily doped N type impurity regions, are formed.

Further, a recess is formed on the surface of the N-type semiconductor substrate 1 between the P-channel transistor and the N-channel transistor,
A heavily doped N-type impurity region 23 is formed on the surface of the recess. A gate electrode 12 is formed on the gate oxide film 9 that connects the drain region 3 and source region 4 of the P-channel transistor, and a gate electrode 12 is formed on the gate oxide film 1o that connects the source region and the drain region 8 of the N-channel transistor. A gate electrode 17 is formed. And gate electrode 12
．． 17 is connected to the input terminal 22. A conductive electrode 11 is formed on the drain region 3 of the P-channel transistor, and a conductive electrode 18 is formed on the drain region 8 of the N-channel transistor. Conductive electrode 11
．． 18 is connected to an output terminal 19. A conductive electrode 24 is formed on a high concentration N-type impurity region 23 formed on the surface of a recess formed in an N-type semiconductor substrate, and a conductive electrode 13 is formed on a source region 4 of a P-channel transistor.
is formed. Conductive electrodes 13.24 are connected to high potential power supply terminal 2o. A conductive electrode 15 is formed on the heavily doped P-type impurity region 6, and a conductive electrode 16 is formed on the source region 7 of the N-channel transistor.

Conductive electrodes 15 , 16 are connected to low potential power terminal 21 .

If the structure is as described above, 9 bases will be obtained in Fig. 3.
7 A low resistance is connected in parallel with the resistance R1 between the base of the parasitic transistor Q1 and the high potential power supply terminal 20,
Equivalently, this is the same as reducing the resistance R1. Equivalently, since the resistance R1 becomes smaller, the current required to turn on the parasitic transistor Q1 becomes smaller. In addition, since the base width of the parasitic transistors Q1 and Q2 effectively widens and the current amplification factor decreases, if you try to obtain the collector current of the parasitic transistors Q1 or Q2 necessary to turn on the parasitic transistor Q3, a high It is necessary to allow a larger current to flow from the potential power supply terminal 20 to the output terminal 19 than in the conventional example. Because of the above, the latch amplifier phenomenon is less likely to occur.

The above explanation was made with an N-type substrate, but 0MOS with a P-type substrate
Obviously, it also applies to ICs.

Effects of the Invention As described above, according to the present invention, the latch-up phenomenon due to parasitic transistors is less likely to occur.
can be provided.

[Brief explanation of the drawing]

10 pages. Figure 1 is a cross-sectional view of the structure of 0MO5IC in one embodiment of the present invention, Figure 2 is a cross-sectional view of a conventional 0MOSIC, and Figure 3 is a cross-sectional view of a conventional 0MOSIC.
The figure is an electrical equivalent circuit diagram of a conventional 0MOSIC. 1...N-type semiconductor substrate, 2...Low concentration P-type impurity region, 3,4.6...High concentration P-type impurity region,
7.8.23...High concentration N-type impurity region, 11°1
3.115, 16, 18.24... conductive electrode,
12.17... Gate electrode, 19... Output terminal, 20... High potential power supply terminal, 21...
-Low potential power supply terminal, 22...Input terminal. Name of agent: Patent attorney Toshio Nakao and 1 other person
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Claims (1)

[Claims] A first MOS field effect transistor is formed on a semiconductor substrate of one conductivity type, an impurity region of a conductivity type opposite to that of the semiconductor substrate is formed on the semiconductor substrate, and the first MOS field effect transistor is formed in the impurity region. forming a second MOS field transistor with a channel opposite to that of the effect transistor;
A recess is formed on the semiconductor substrate between the MOS field effect transistor and the second MOS field effect transistor, and a highly concentrated impurity region of the same conductivity type as the semiconductor substrate is formed on the surface of the recess; A semiconductor integrated circuit device characterized in that a conductive electrode is formed on a high concentration impurity region of the same conductivity type as the semiconductor substrate, and the conductive electrode is connected to a power source.