JPS5910256A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain an MOS transistor integrated circuit device which has a small occupation area and is suitable for a low voltage power source driven circuit by a method wherein a bi-polar transistor is formed on the same chip as the MOS transistor, resulting in the construction of an analog circuit. CONSTITUTION:The constant current source connected to the common source to differential pair N type NOS transistors 2 and 3 is constituted of the bi-polar N-P-N transistor 13. The bi-polar N-P-N transistor 13 is composed of N type regions 18 and 19 and a P type region 23. A base region 23 is formed at the same time with the P type layer 20 of the N type MOS transistor 2, and a collector region 18 and an emitter region 19 with the N type layers 21 and 22 of the N type MOS transistor 2. The VBE of the bi-polar N-P-N transistor 13 can be regarded as a nearly constant value not be depending on the current value of the IC, and is much smaller than the VGS of the N type MOS transistor without being influenced by the emitter area, accordingly advantageous in case of operation by means of a low voltage power source.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated device of an analog circuit composed of insulated gate time-field effect transistors.

FIG. 1 shows a conventional example of a differential amplifier circuit constructed using an insulated gate open field transistor (hereinafter referred to as MO5 transistor) integrated circuit manufacturing process.

The above-mentioned differential amplifier circuit connects a differential pair of MOS transistors 2.3, and applies a first bias voltage 10 to each gate via a resistor 7.8. P-type MOS transistors 4 and 5 are connected between the input terminal 1 and the power source 9 as a load at each drain, and a second bias voltage 11 is applied to the gate of the common source, and the source is grounded. MO5)
This is a well-known circuit that connects a transistor and uses it as a constant current source.

Tortoise pressure between the gate and source of a MOS transistor (hereinafter referred to as Va
The relationship between the drain current (referred to as t), the drain current, and the size of the MOS transistor is expressed by the following equation (during operation in the saturation range).

2 ID = K-T(Vas-Vth)...(
1) Here, ID Ni drain current, N: constant, W: channel width, L: channel length, fth: L threshold 1 direct soldering pressure. As can be seen from equation (2), once the drain current ID is determined, the value of Vaz depends on L. The minimum value of the channel length LL) is determined in the manufacturing process. Therefore, the value of GJ' is determined by the channel width (c). Here, attention will be paid to the differential amplifier circuit shown in FIG. In order to drive the solder #voltage 9 with a low voltage (7MO5) transistors 2 and 5
．． A. It is necessary to make the 5.6Vat as small as possible. For this purpose, as mentioned above, the channel width (c) must be increased, and if the area of the MO5 transistor becomes very large, a drawback will occur. By the way, Io=1mA
, g'/L-10, Vat is approximately 3, which is very large.

An object of the present invention is to eliminate the drawbacks of the prior art described above, and to provide a MOS that occupies a small area and is suitable for low voltage power supply drive circuits.
) provides a transistor integrated circuit device.

The present invention is based on the base-emitter voltage (
We focused on the fact that rag) is not affected by the emitter area and exhibits an exponential characteristic with respect to the collector current. is formed on the same chip to form an analog circuit.

Hereinafter, embodiments of the present invention will be described in detail using the drawings. FIG. 2 shows the structure of an integrated circuit according to an embodiment of the present invention, FIG. 3 shows its circuit, and FIG. 4 shows a circuit of another embodiment. Here, the same parts as in FIG. 1 are given the same numbers. First, the differences between the circuit shown in FIG. 6 and the conventional circuit shown in FIG. 1 will be described. The constant current source connected to the common source of the differential pair MO transistors 2 and 5 is constituted by a bipolar transistor 15 shown in FIG. As is well known, Vsz of the bipolar np transistor 15
is expressed as below.

Vs Ez-! Ef-1nla
-(!l) where k: Boltzmann constant, T: absolute temperature, q: electric charge of Taneko, IC: collector current.

As can be seen from equation (5), since FBE is an exponential function of lc, it can be regarded as a substantially constant value regardless of the current value of lc when the bipolar npn transistor 3 is in normal operation. Moreover, it is not affected by the emitter area and its direct voltage is about 0.7V. This line is the square MOS shown in Figure 1.
Transistor 60VGsr (5V, u7/L=1
0, Ii>-1 mA). Therefore, it is advantageous when operating with a low pressure power source.

Next, the formation of the bipolar prL transistor 3 in the pMOSMOS transistor path manufacturing process will be explained with reference to FIG. Here, the semiconductor substrate 14 is a Le-shaped crystal single crystal,
+5.16, 17.18.19 are le-shaped areas, 202
1.22.2”+ is P shadow area, 24.25 is oxide film, 2
6 and 27 are polycrystalline silicon. 15, 16, 2.
4 and 26, the p@MOS transistor 4 in Fig. 3 is replaced with 2
0.21.22.degree. 25 and 27 constitute a loop-type MOS transistor 2, 17 constitutes a resistor 7, and 18.19.25 constitutes a bipolar npn transistor 15. The numeral 18 forms a collector region, the numeral 19 forms an emitter region, and the numeral 23 forms a base region. The base region 26 is the P of the MO5 transistor 2.
It is formed at the same time as the shaped layer 20 in the manufacturing process. Further, the collector region 18 and the emitter region 19 are formed simultaneously with the square layers 24 and 22 of the square AlO3 transistor 2. As described above, the bipolar (prL) transistor can be realized in the current MOS transistor integration V6 manufacturing process without adding any steps.

In the implementation column of FIG. 4, the bipolar RBP transistor is replaced with the differential pair n-type JfO5) transistor 2゜3 in FIG. 5, and as mentioned above, since VBE is small, Differential amplifier circuits are also suitable for low voltage power supply operation.

As described above, the present invention generally relates to an integrated circuit manufacturing process for digital circuits. Solve the problem when analog circuits such as differential amplifier circuits are mixed on the same chip in the MOS transistor manufacturing process (Vax is large and it is difficult to operate at low voltage) by configuring bipolar transistors without increasing the manufacturing process. It is possible to achieve the effect of being able to

[Brief explanation of drawings]

FIG. 1 is a circuit diagram constructed using a conventional manufacturing process, FIG. 2 is a cross-sectional view of the structure of a semiconductor integrated device according to an embodiment of the present invention, FIG. 6 is an equivalent circuit diagram of FIG. 2, and FIG. FIG. 6 is a circuit diagram of another implementation of the invention. 2.5.6... Le type-hfO5) transistor, 15
, 28, 29...Bipolar transistor, 1B,
19.21.22... Le-shaped semiconductor region, 20, 23
...P-type semiconductor region. 11 Zuga 3 Ward Sai 4 Kasumi

Claims (1)

[Claims] 1. A first insulated gate field effect transistor having a pair of second conductive type source/train regions isolated from each other in a fourteenth conductive type semiconductor substrate, and a second conductive type field effect transistor formed in the semiconductor substrate. a second insulated gate type zone effect transistor having a pair of first conductive 1 m source/drain regions formed isolated from each other in a conductor region of the semiconductor substrate; and a second conductor conductor region of the second conductivity type in the semiconductor substrate. A second conductivity type space region formed at the same time, and a first conductivity type collector region and an emitter region separated from each other in the base region and formed at the same time as the source/drain region of the second insulated gate field effect transistor. and the bipolar transistor is connected as a constant current source for the first insulated gate male field effect transistor or the second insulated gate field effect transistor serving as an amplification element. A semiconductor integrated device characterized by: