JPS59954A - Semiconductor integrated device - Google Patents

Abstract

PURPOSE:To increase the curent amplification factor of a bipolar transistor larger than that of a parasitic bipolar transistor by forming the impurity density of the second conductive type base region in such a manner that the part near the surface is in low density and the part isolated from the surface is in high density. CONSTITUTION:A bipolar transistor is composed of a base region 22, a collector region 8 and an emitter region 9. A parasitic bipolar transistor is formed of a semiconductor substrate 1 to become a collector region, the emitter region 9 and a base region 3. The density of the region 22 is formed to be lower than the density of the region 3 by utilizing the fact that the current amplification factor of the bipolar transistor is inversely proportional to the density of the region 22. Accordingly, the current amplification factor of the bipolar transistor becomes larger than that of a parasitic bipolar transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated device in which a bipolar transistor is formed in the manufacturing process of an insulated gate field effect transistor.

FIG. 1 shows a cross-sectional view of a semiconductor device including a bipolar transistor formed by a conventional insulated gate field effect transistor (hereinafter referred to as MOS transistor) manufacturing process. FIG. 2 is an enlarged cross-sectional view of the bipolar transistor.

In FIG. 1, a semiconductor substrate 1 is an n-type silicon single crystal, 6
, 7, 8, 9 are n shadow regions, 2, 3° 4.5 are p shadow regions,
11.13 is an oxide film, and 10.12 is polycrystalline silicon. 4, 5, 10 and 11 constitute a p-type MO transistor, and 2, 6, 7, 12 and 13 constitute an n-type MO transistor.
8) Configure transistors. 3,8.9 constitute a bipolar transistor. Here, 3 forms the maximum region of the bipolar transistor, 8 forms the collector region, and 9 forms the emitter region.

As described above, bipolar transistors can be constructed on the same semiconductor substrate through the MOS transistor manufacturing process. However, the bipolar transistor formed by the conventional manufacturing process described above has a drawback of having a small current amplification factor (hereinafter referred to as hrg).

This drawback will be explained in detail with reference to FIGS. 2 and 3. In FIGS. 2 and 3, the same parts as in FIG. 1 are designated by the same numbers. In FIG. 2, 16, 17, and 18 are the base terminal, collector terminal, and emitter terminal of the bipolar transistor 14, respectively.

Further, 19 indicates a terminal of the semiconductor substrate 1. Normally, a positive power source 20 is applied to the semiconductor substrate 1 to insulate it from the p-shade region.

The bipolar transistor 14 described above has a structure in which the semiconductor substrate 1 is the collector, the n-shade region 9 is the emitter, and the p-shade region 3 is the collector.
There is a parasitic bipolar transistor 15 based on , whose base and emitter regions are the same as those of the bipolar transistor 14 . FIG. 3 shows these circuits in operation.

, the common emitter terminal 18 of the bipolar transistor 14 and the parasitic bipolar transistor 15 is grounded, and the common base terminal 16 of the bipolar transistor 14 and the parasitic bipolar transistor 15 is connected to a bias voltage 21 in FIG. The collector/terminal 17 of the bipolar transistor 14 is then connected to other circuits. Further, the collector of the parasitic bipolar transistor 15 is connected to the positive power supply 20. Comparing the current amplification factor (hrgx) of the parasitic bipolar transistor 15 and the current amplification factor (hrgt) of the bipolar transistor 14° in the above circuit, it is found that hrzt>hrE2 from the structure shown in FIG. Therefore, the parasitic bipolar transistor 15 starts operating first, and a larger collector current flows than the positive power supply 20.

As described above, when the bipolar transistor 14 of the conventional semiconductor integrated device is operated, the parasitic bipolar transistor 15
The disadvantage is that a large current flows through the

Therefore, an object of the present invention is to provide a semiconductor integrated device in which the current amplification factor (hrgs) of the bipolar transistor 14 is larger than the current amplification factor (hrgt) of the parasitic bipolar transistor 15.

The present invention takes advantage of the fact that the current amplification factor of a bipolar transistor is inversely proportional to the concentration of the base region, and adds p-type impurities to the base region (n shadow region) of the bipolar transistor to lower the concentration of the base region. An embodiment of the present invention is shown in FIG. 4 and will be described in detail. Here, the same parts as in FIG. 2 are indicated by the same numbers. In FIG. 4, reference numeral 22 denotes a low-density p shadow region (hereinafter referred to as p-), which has a lower density than the p shadow region 3. Generally, the current amplification factor hrg of a bipolar transistor can be expressed by the following formula.

where ρB is the resistivity of the two base regions.

ρE: Resistivity of emitter region, XB: Base thickness.

LE: Diffusion length of emitter (As can be seen from the equation, hrg increases as the resistivity of the base region increases. In other words, hpg increases as the impurity concentration of the base region decreases.

Therefore, n-type impurities are added only to the surface of the p shadow region 3, which is the common base region of the bipolar transistor 14 and the parasitic bipolar transistor 15. As a result, only a portion shallower than the surface of the p shadow region 3 becomes a low density p shadow region 22. That is, the p shadow region 22 is the base region of the bipolar transistor 14. Therefore, when comparing the concentrations of the base region 22 of the bipolar transistor 14 and the base region 3 of the parasitic bipolar transistor 15, (concentration of the base region 22) <(base region 3), the current amplification factor of the bipolar transistor 14 (hpg2)
is the current amplification factor (hrEt) of the parasitic bipolar transistor 15
can be made larger than.

As described above, according to the present invention, the parasitic bipolar problem that occurs when bipolar transistors are formed on the same substrate in the MOS (MOS) transistor manufacturing process, which is generally an integrated circuit manufacturing process for digital circuits. The influence of the transistor can be reduced.

[Brief explanation of the drawing]

Claims (1)

[Claims] 1. A first insulated gate field effect transistor having a pair of second conductivity type source/drain regions formed in a first conductive semiconductor substrate and isolated from each other; 1
a second insulated gate field effect transistor having a pair of first conductivity type source/drain regions separated from each other in a second conductivity type semiconductor region formed in a conductivity type semiconductor substrate; a second conductivity type base region formed simultaneously with the second conductivity type semiconductor region in a first conductivity type semiconductor substrate; and a source/drain of the second insulated gate field effect transistor separated from each other in the base region. a bipolar transistor comprising a first conductivity type collector region and an emitter region formed simultaneously with the second conductivity type collector region;
1. A semiconductor integrated device characterized in that the impurity concentration of a conductive base region is low in a portion close to the surface and high in a portion remote from the surface. 2. The semiconductor integrated device according to claim 1, wherein the first conductivity type impurity is applied to the second conductive base region.