JPH02237058A - Semiconductor integrated circuit and manufacture thereof - Google Patents

Abstract

PURPOSE:To restrain an N channel MOS transistor from varying in characteristic by a method wherein a reverse conductivity type buried layer whose impurity concentration and vapor pressure are lower than those of a buried collector region is formed under the region of the N-channel and a P-channel MOS transistor formed on a substrate. CONSTITUTION:A high impurity concentration N-type buried collector region 2, and an N-type buried region 22 and a P-type buried region 3 whose impurity concentration and vapor pressure are lower than those of the buried collector region 2 are formed on a P-type single crystal silicon substrate 1. An N-well region 5 is formed on the N-type buried collector region 2, the N well region 5 and a P well region 7 are provided onto the N-type buried region 22, and a P-type isolating region 6 is built on the P-type buried region 3. By this setup, the P-well region 7 and the substrate 1 are electrically isolated from each other and an N-channel MOS transistor can be restrained from having in characteristic. A CMOS can be improved in resistance to latch-up.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor integrated circuit and a method for manufacturing the same, and in particular, to a semiconductor integrated circuit and a method for manufacturing the same.
B i − forming a (complementary MOS) transistor
The present invention relates to a CMOS integrated circuit and its manufacturing method.

Conventional technology In recent years, as semiconductor integrated circuits have been desired to have faster speeds and functions that support analog and digital, bipolar transistors and CM
Bi-C with OS transistors integrated on the same substrate
MOS integrated circuits are attracting attention. Conventional B i-CM
The OS integrated circuit has a structure as shown in FIG.

Hereinafter, with reference to the cross-sectional view shown in FIG.
-The structure of a CMOS integrated circuit and its manufacturing method will be explained.

This structure is realized through the following steps.

First, on a p-type single crystal silicon substrate (hereinafter referred to as a substrate) 1 on which an n-type buried collector region 2, an n-type buried region 21, and p-type buried regions 3, 31 are selectively formed, a resistivity of 1 to 1 is applied. An n-type silicon epitaxial layer 4 of 5Ω·cIl is formed, and an n-well region 5 connected to the n-type buried collector region 2 and the n-type buried region 21 is formed on the n-type buried collector region 2 and the n-type buried region 21, and an n-type silicon epitaxial layer 4 is formed on the p-type buried region 3. A p-type isolation region 6 is formed connected thereto, and a p-well region 7 is formed on the p-type buried region 31. Furthermore, a thick silicon oxide film 8 is grown using a selective oxidation method to isolate the elements.
Thereafter, a thin silicon oxide film that will become the gate oxide film 9 is formed, and a conductive film such as polycrystalline silicon is selectively formed thereon to form the gate electrode 10. Next, a collector all layer 11 of an npn transistor is formed by diffusion of n-type impurities, and a base region 12 is formed by selectively ion-implanting p-type impurities. Furthermore, n-type impurities are selectively ion-implanted to form low-concentration n-type source regions 13 and drain regions 1 of the n-channel MOS transistor.
31 is formed, and the gate electrode 1 is formed using a silicon oxide film or the like.
After forming a silicon oxide film for sidewalls on the sidewalls of 0, n-type impurities are selectively ion-implanted to form high-concentration n-type source regions 15 and drain regions 151 of an n-channel MOS transistor. Furthermore, p-type impurities are selectively ion-implanted to form high-concentration p-type source regions 16 and drain regions 1 of the p-channel MOS transistor.
61 is formed. Next, polycrystalline silicon containing n-type impurities is formed on the base region 6 to form an emitter electrode 17.
At the same time, an emitter region 18 is formed by diffusing n-type impurities from the emitter electrode 17.

As can be seen from FIG. 2, the p-well region 7 of the n-channel MOS transistor region and the p-type single crystal silicon substrate 1 are electrically connected via the p-type buried region 31.

Problems to be Solved by the Invention In such a conventional structure and its manufacturing method, since the p-well region 7 and the substrate 1 are electrically connected, when a negative voltage is applied to the substrate, n-channel MO
S transistor drain regions 131 and 151 and substrate 1
A high electric field is applied between the p-wells 7 and 7, and the hot electron effect becomes significant. For example, when using a ±5V power supply and the drain potential of an n-channel MOS transistor is 5V, the substrate potential is set to -5V, so the potential difference between the drain and the substrate becomes 10V, and hot electrons are injected into the gate oxide film. Increases trap probability. As a result, there have been disadvantages in that characteristics are impaired, such as fluctuations in the threshold voltage Vt of the n-channel MOS transistor and deterioration in mutual conductance gII. Another drawback is that a current flows into the substrate as a result of the switching operation of the MOS transistor, which becomes a noise current source and impairs the characteristics of the bipolar transistor. The present invention solves the above-mentioned conventional problems, and provides a semiconductor integrated circuit and a method for manufacturing the same, which suppresses characteristic fluctuations due to substrate bias of an n-channel MOS transistor and suppresses noise from the MOS transistor to a bipolar transistor. The purpose is to

Means for Solving the Problems To achieve this object, the semiconductor integrated circuit of the present invention comprises:
A heavily doped n-type buried collector region is formed below a region of a bipolar transistor formed on a p-type single-crystal silicon substrate, and an n-channel MOS transistor and a p-channel transistor are formed on the single-crystal silicon substrate. M
An n-type buried region made of an impurity having a lower concentration and vapor pressure than the impurity used for the buried collector region is formed below the region of the OS transistor. The manufacturing method for obtaining this structure consists of an n-type buried collector on a p-type single crystal silicon substrate and an n-type buried collector made of an impurity that is lower in concentration and has a lower vapor pressure than the impurity used for the same buried collector region. forming an n-type semiconductor layer on the surface of the single crystal silicon substrate; forming a first n-type well region in the semiconductor layer above the buried collector region; forming an n-type second well region and a p-type well region in the semiconductor layer on the semiconductor layer; forming a bipolar transistor in the n-type first well region;
The method includes a step of forming a p-channel MOS transistor in a second well region of the type, and forming an n-channel MOS transistor in the p-type well region.

Operation According to this structure and its manufacturing method, a p-channel MOS transistor is formed by an n-type buried region.
Since the well region and the substrate are electrically separated, the potential difference between the drain of the n-channel MOS transistor and the p-well region does not become as large as in the conventional example even when a negative voltage is applied to the substrate. <<Increase in the probability of hot electron injection trapping into the gate oxide film is suppressed, and variation in characteristics of the n-channel MOS transistor can be suppressed. Further, since the substrate current of the MOS transistor can be sucked out to the power supply terminal, it is not applied to the bipolar transistor through the substrate and does not become a noise current source.

Furthermore, since the n-type buried region under the n-channel MOS transistor region is formed of a low-concentration diffusion layer made of impurities with a lower vapor pressure than the n-type buried collector region of the bipolar transistor region, the p Encroachment into the well region can be reduced, the p-well region can be thickened, and the base width of the parasitic npn transistor formed between the n-type source region and the n-type buried region of the n-channel MOS transistor can be widened. It is possible to lower the current amplification factor and improve the latch-up resistance of the CMOS.

Embodiment An embodiment of a semiconductor integrated circuit and a method of manufacturing the same according to the present invention will be described with reference to the cross-sectional view shown in FIG.

This structure includes a highly concentrated n-type buried collector region 2 on a p-type single crystal silicon substrate 1, an n-type buried region 22 made of an impurity with a lower impurity concentration and lower vapor pressure, and A type buried region 3 is formed, and an n-well region 5 is formed on the n-type buried collector region 2.
However, an n-well region 5 and a p-well region are formed on the n-type buried region 22, a p-type isolation region 6 is formed on the p-type buried region 3, and in the n-well region 5, Collector all layer 11 connected to embedded collector region 2
, a base region 12 and an emitter region l8 are formed,
A p-type source region 16 and a drain region 161 are formed in the n-well region 5l, and a gate oxide 1!19 and a gate electrode 10 are stacked on the surface of the n-well region 51 between these regions, and the p-well region A low concentration n-type source region 13 and drain region 131 and a high concentration n-type source region 15 and drain region 151 are formed in the well region 7, and a gate is formed on the surface of the p well region 7 between these regions. An oxide film 9 and a gate electrode 10 are formed.

Note that 8 is a thick silicon oxide film for element isolation, and 14 is L.
This is a silicon oxide film for sidewalls to obtain a DD structure.

Next, a manufacturing method for obtaining this structure will be explained.

First, an n-type buried collector region 2 formed by selectively doping arsenic and an n-type buried collector region 2 formed by selectively doping antimony, which has a lower vapor pressure than arsenic.
2 and a p-type buried region 3 are selectively formed on a p-type single crystal silicon substrate 1 having a specific resistance of 0.3 to 10Ω.
- Form a c+a n-type silicon epitaxial layer 4. In this silicon epitaxial layer 4, an n-well region 5 is formed above and connected to the n-type buried collector region 2, an isolation region 6 is formed above the p-type buried region 3, and an A p-well region 7 is formed above region 22 in a region where an n-channel MOS transistor is to be formed, and an n-well region 51 is formed in a region where a p-channel MOS transistor is to be formed. Furthermore, a thick silicon oxide film 8 is grown by selective oxidation to form element isolation regions. Thereafter, a thin silicon oxide film that will become the gate oxide film 9 is formed, and a conductive film such as polycrystalline silicon is selectively formed thereon to form the gate electrode 10.

Next, a collector all layer 11 of an npn transistor is formed by diffusion of n-type impurities, and a base region 12 is formed by selectively ion-implanting p-type impurities. Furthermore, by selectively ion-implanting n-type impurities,
After forming a low concentration n-type source region 13 and drain region 131 of the OS transistor and forming a sidewall silicon oxide film l4 on the sidewall of the gate electrode 10,
N-channel MO by selectively ion-implanting D-type impurities
By forming the n-type source region 15 and drain region 151 with high concentration of the S transistor, the n-channel M
Forms the LDD structure of the OS transistor. Furthermore, p
p-channel MOS by selectively ion-implanting type impurities
High concentration p-type source region 16 and drain region 161 of the transistor are formed. Next, polycrystalline silicon containing arsenic impurities is selectively formed on the base region 12 to form the emitter electrode 17, and further heat treatment is performed to form the emitter region 18 by diffusion of impurities from the emitter electrode l7. do.

In the semiconductor integrated circuit formed as described above, the p-well region 7 of the n-channel MOS transistor region and the p-type single crystal silicon substrate 1 are electrically isolated by the n-type buried region 22. Therefore, a voltage higher than or equal to the lowest voltage applied to the p-type single-crystal silicon substrate 1 can be applied to the p-well region 7. For example, in the case of ±5V power supply operation, even when the source voltage is set to OV, the n-channel MOS The voltage of the p-well region 7, which becomes the substrate of the transistor, can be applied to Ov. As a result, only an electric field for a maximum voltage of 5V is generated at the drain end, so the hot electron effect of the n-channel MOS transistor due to substrate bias is suppressed, and fluctuations in v and deterioration of g are prevented. Further, the current to the substrate generated during switching of the MOS transistor is detoured to the power supply terminal (not shown) via the p-well region 7 and has no adverse effect on the Babolat transistor. Furthermore, since there is little back-diffusion into the p-well region 7 due to the n-type buried region 22, the width in the depth direction of the p-well region is not narrowed, improving the latch-up resistance of CMOS, and the n-type buried collector region 2 is Since the concentration is high, the collector layer of the bipolar transistor can be made to have a lower resistance.

Effects of the Invention According to the semiconductor integrated circuit of the present invention, a highly doped n-type buried collector region is provided under a region where a bipolar transistor is formed on one main surface of a p-type single crystal silicon substrate, and an n-channel MOS By providing a structure having an n-type buried region made of an impurity with a lower concentration and vapor pressure than the impurity used for the upper aa n-type buried collector region under the region where the transistor and the p-channel MoS transistor are formed, the substrate It is possible to suppress characteristic fluctuations of n-channel MOS transistors due to bias, suppress characteristic fluctuations of bipolar transistors due to substrate current of MOS transistors, improve latch-up resistance of CMOS, and lower resistance of the collector layer of bipolar transistors. can. As a result, a highly reliable semiconductor integrated circuit can be realized.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing an embodiment of a semiconductor integrated circuit according to the present invention, and FIG. 2 is a sectional view showing the structure of a conventional semiconductor integrated circuit. 1...p-type single crystal silicon substrate (substrate), 2.
...N-type buried collector region, 21.22...
......n-type buried region, 3, 31...p-type buried region, 4...n-type silicon epitaxial layer, 5...n-well region, 6.・・・・・・
P-type isolation region, 7. Old p-well region, 8. Thick silicon oxide film, 9. Gate oxide film, 10
...Gate electrode, 11...Collector all layer, 12...Base region, 13...
... Low concentration n-type source region, 131 ... Low concentration n-type drain region, 14 ... Silicon oxide film for sidewall, 15 ... High concentration N-type source region with high concentration, 151...N-type drain region with high concentration, 16...P-type source region with high concentration, 161......N-type source region with high concentration. P-type drain region, 17... emitter electrode, 18... emitter region.

Claims (2)

[Claims] (1) An n-channel MOS transistor formed on the single crystal silicon substrate in which a buried collector region of the opposite conductivity type is formed with high concentration under the region of a bipolar transistor formed on the single crystal silicon substrate of one conductivity type. A semiconductor integrated circuit characterized in that a buried region of an opposite conductivity type made of an impurity having a lower concentration and a lower vapor pressure than the impurity used for the buried collector region is formed under the region of the p-channel MOS transistor. (2) An embedded collector region of the opposite conductivity type that serves as a collector on a single-crystal silicon substrate of one conductivity type, and an embedded collector region of the opposite conductivity type made of an impurity that is lower in concentration and has a lower vapor pressure than the impurity used in the same buried collector region. a step of forming a semiconductor layer of an opposite conductivity type on the surface of the single crystal silicon substrate; a first well region of the opposite conductivity type in the semiconductor layer above the buried collector region;
A second semiconductor layer of an opposite conductivity type is formed on the semiconductor layer above the buried region.
a bipolar transistor in the first well region of opposite conductivity type and a channel MOS transistor of one conductivity type in the second well region of opposite conductivity type; . A method for manufacturing a semiconductor integrated circuit, comprising the step of forming a channel MOS transistor of an opposite conductivity type in the well region of one conductivity type.