JP3231284B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method of manufacturing a semiconductor device which functions as a Bi-CMOS in which a high-frequency bipolar transistor and a MOS transistor are mounted on a common substrate.

[0002]

2. Description of the Related Art At present, typical transistors generally used include a bipolar transistor composed of an emitter, a base and a collector, and a gate electrode, a gate oxide film and a source / drain region. MOS transistors. Bipolar transistors are characterized by being suitable for analog elements utilizing a linear amplification function, and MOS transistors are characterized by having a simple structure and being particularly suitable for logic elements. In recent years, bipolar transistors have been increasingly used as high-frequency transistors, and there is a demand for a transistor suitable for a higher-frequency region. On the other hand, there is a demand for higher integration of MOS transistors.

Further, in recent years, there has been a demand for miniaturization of a semiconductor device using a high-frequency bipolar transistor and a MOS transistor. In order to miniaturize such a semiconductor device, both are formed on a common substrate. It is effective to make one chip. Therefore, a so-called Bi-CMOS device in which a bipolar transistor and a MOS transistor are provided on a common substrate has been proposed.

Hereinafter, a conventionally proposed method of manufacturing a Bi-CMOS will be described with reference to the drawings. 16 to 24 are cross-sectional views showing the steps of manufacturing a conventionally proposed Bi-CMOS.

First, in the step shown in FIG. 16, the surface of the P-type silicon substrate 101 on the main surface side is oxidized to form a silicon oxide film. Then, etching is performed using a photoresist film (not shown) formed on the silicon oxide film by lithography as a mask to selectively remove the silicon oxide film, thereby forming a bipolar transistor formation region R.
A mask oxide film 106 having openings respectively in bp and the MOS transistor formation region Rmos is formed.

Next, arsenic ions 10 are formed on the main surface of P-type silicon substrate 101 using mask oxide film 106 as a mask.
7 at an acceleration energy of 30 keV and a dose of 1.
The implantation is performed under the conditions of 5 × 10 ¹⁵ / cm ² , and the bipolar transistor region Rbp and the MOS transistor formation region Rmos
Then, the deep injection layers 102 and 103 are respectively formed.

Next, a heat treatment is performed to obtain the deep injection layer 10.
After arsenic in 2103 is diffused and oxidized to form a patterning step, the mask oxide film 106 is entirely removed.

Next, in a step shown in FIG. 17, an epitaxial layer 105 is grown over the entire main surface of the P-type silicon substrate 101. At this time, the P-type silicon substrate 10
1 is formed along the main surface of the deep injection layer 102, 1
From 03, arsenic partially diffuses into the epitaxial layer 105, respectively, and N-type buried layers 108 and 109 are formed.

Next, after a silicon oxide film 110 and a silicon nitride film 111 for forming an active region are sequentially formed on the epitaxial layer 105, lithography and dry etching are performed to form a silicon nitride film 111 for forming the active region. Of the P-type transistors in the bipolar transistor formation region Rbp and the MOS transistor formation region Rmos
An opening is formed in the MOSFET formation region Rpmos, and phosphorus ions 112 are implanted from the opening to form two regions Rbp and Rpm.
A surface diffusion layer 113 is formed on os.

Next, in a step shown in FIG. 18, after removing the silicon oxide film 110, a silicon region in the opening is selectively oxidized to form a mask oxide film 115. By this heat treatment, the impurities in the surface diffusion layer 113 diffuse widely, so that the N well region 114 is formed, and the N type buried layers 108 and 109 also expand in the depth direction.

Next, in a step shown in FIG. 19, using the mask oxide film 115 as a mask, a MOS transistor formation region Rmo is formed.
Then, boron ions 116 are implanted into the NMOSFET formation region Rnmos and the like in s to form a P-type implantation layer.

Next, in the step shown in FIG. 20, the mask oxide film 115 is removed, and drive-in is performed by heat treatment to form a P-well region 117. By this heat treatment, the N-type buried layers 108 and 109 are further expanded in the depth direction.

Next, in the step shown in FIG.
After the COS forming silicon nitride film 118 is formed, isolation oxide films 119a to 119e are formed in predetermined isolation regions by using a normal LOCOS method.

Next, in a step shown in FIG. 22, after a silicon oxide film 120 is grown on the substrate, the silicon oxide film 120 is formed so as to include a portion immediately above the edge of the N-type buried layer 109 in the bipolar transistor formation region Rbp. Separation oxide films 119a, 11
9c and the vicinity of the center of the silicon oxide film 120 thereon are selectively removed to form trench opening windows 121, respectively.

Next, in the step shown in FIG. 23, using the silicon oxide film 120 as a mask, the silicon substrate exposed in the trench opening window 121 is etched to a depth of 5
A trench 122 of about 6 μm is formed.

Further, in the step shown in FIG.
After a channel stopper layer 123 is formed under the bottom surface of the trench 22, a sidewall oxide film 124 of the trench 122 is formed, and polysilicon is buried in the trench 122 to form a buried polysilicon layer 125. The buried polysilicon layer 125 is formed by depositing a polysilicon film on a substrate and then etching it back by a dry etching method.

Although the subsequent steps are omitted, diffusion layers and electrodes of the bipolar transistor, the PMOSFET and the NMOSFET are formed.

The Bi- formed by the above steps
In a CMOS device, the following effects can be obtained by using a trench isolation structure instead of the LOCOS isolation structure. By employing the trench isolation structure, the junction capacitance between the collector and the substrate in the bipolar transistor formation region Rbp is reduced, and the frequency of the bipolar transistor can be increased. Also, by adopting a trench isolation structure,
Unlike the LOCOS isolation structure, the width of the isolation oxide film 119 can be shorter than that of the PN junction isolation, so that the wiring capacitance is reduced and the frequency can be further increased.

At this time, instead of burying a silicon oxide film in a trench like a trench structure in a MOS transistor, polysilicon is buried. First, in the case of forming a bipolar transistor, a heat treatment at a high temperature of about 900 ° C. is required after forming a trench isolation, so that the coefficient of thermal expansion between the material in the trench and the silicon substrate is reduced. Secondly, in the case of polysilicon having a small grain size and directivity, it is necessary to avoid a trench much deeper than a trench isolation of a MOS transistor. This is because the embedding characteristics such as coverage are good, and the generation of voids can be avoided like a silicon oxide film. To this end, polysilicon is buried in the trench, and the buried polysilicon layer 125 and the P-type silicon substrate 101 are buried.
And a side wall oxide film 124 interposed therebetween.

Thereafter, although not shown, a region immediately below the exposed surface of the buried polysilicon layer 125 is oxidized to form a cap oxide film integrated with the isolation oxide films 119a and 119c. This prevents unnecessary transistors and capacitors from being generated by introducing impurities into the buried polysilicon layer 125 and activating them later.

[0021]

However, the method of manufacturing a Bi-CMOS device proposed above has the following problems.

First, in the state shown in FIG. 23, the N-type buried layers 108 and 109 are expanded by the heat treatment for forming the N-well region 114 and the P-well region 117. That is, when forming a bipolar transistor with a high frequency and a highly integrated CMOS transistor on a common substrate, heat treatment for activating the P-type and N-type wells of the CMOS transistor requires a high temperature and a long time. As a result, the N-type buried layers 108 and 109 in the bipolar transistor formation region are expanded. Therefore, in order to secure the isolation function, the trench 122 penetrating the N-type buried layer 109 in the bipolar transistor formation region Rbp must be deepened to about 5 to 6 μm. Therefore, there is a problem that the process time for forming the trench 122 is excessively increased, and it is practically difficult to perform the process.

That is, Bi as conventionally proposed
Due to the above-mentioned problems in the method of manufacturing a CMOS device, a high-frequency bipolar transistor and a CMO
Bi-MO with S-transistor formed on common substrate
The realization of the S device was hindered.

In a subsequent step, when the silicon oxide film 120 used as a mask for forming the trench is removed, the lower isolation oxide films 119b, 119d, and 11 are removed.
Since 9e is also partially removed, there is a problem that the element isolation function of the MOS transistor portion is deteriorated.

Second, as shown in FIG. 24, in a buried polysilicon layer 125 formed by etching back a polysilicon film, a V-groove 126 having a V-shaped concave at the center of the surface is generated. There was something to do. afterwards,
An oxide film and a wiring are formed on the buried polysilicon layer 125, but the presence of the V-groove 126 may cause disconnection or bridge in a later step.

Then, the present inventors have investigated the cause, and as a result, it is presumed to be caused by the following phenomenon.

As shown in FIG. 14, when a polysilicon film is grown in a trench, columnar crystal grains grow in a direction perpendicular to the wall surface of trench 122, which is a direction of a temperature gradient, and as a result, each columnar crystal is grown. The ends of the crystal grains are concentrated at the center of trench 122. That is, the boundaries of the crystals are concentrated at the center of the trench 122, and there are extremely many defects as compared with other regions. However, in general, the etching rate in a portion having many defects is much higher than that in a portion having few defects. As a result, it is presumed that a V-groove 126 is formed at the center of the buried polysilicon layer 125 to be formed.

Such a phenomenon occurs not only in a buried polysilicon layer in a trench of a Bi-CMOS device but also in a buried polysilicon layer in another semiconductor device. In addition, when etching back by embedding not only polysilicon but also other insulating materials in the trench, such a phenomenon may occur.

A first object of the present invention is to avoid the above-mentioned problem when forming a high frequency bipolar transistor and a highly integrated CMOS transistor on a common semiconductor substrate, and to provide a semiconductor device having both transistors mounted thereon. It is an object of the present invention to provide a method of manufacturing a semiconductor device which can form the device into one chip.

A second object of the present invention is to adjust the etching rate of a buried film having a polycrystalline structure such as polysilicon deposited in the trench so that the etching rate can be made uniform, so that the buried film formed in the trench can be made uniform. A method of manufacturing a semiconductor device for eliminating the occurrence of V-grooves on the surface of a film, flattening a member formed above a buried film, and obtaining a highly reliable semiconductor device without disconnection or bridge. Is to make it happen.

[0031]

Means for Solving the Problems In order to achieve the first object, the means taken by the present invention is to reduce the diffusion of impurities introduced into the buried layer of the bipolar transistor by suppressing the process of manufacturing the MOS transistor. Is to make adjustments.

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device including a bipolar transistor operating with a first conductivity type carrier as a majority carrier and a MOS transistor operating with a second conductivity type carrier as a majority carrier. A first impurity doped layer of a first conductivity type serving as a first buried layer is formed in a bipolar transistor formation region on a main surface side of a second conductivity type semiconductor substrate, and a second impurity doped layer is formed in a MOS transistor formation region. Forming a first conductivity type second impurity-introduced layer to be a buried layer, and then forming a first conductivity type epitaxial growth layer on the semiconductor substrate; and a boundary between the two transistor formation regions. Forming a trench deeper than a lower end of the first buried layer in the bipolar transistor formation region; A third step of filling the membrane embedded insulating in the trench, in a region including at least the epitaxial layer of the MOS transistor forming region, the threshold of the MOS transistor forming region
Area from just below the value control layer to below the channel stopper layer
As the first conductivity-type well layer is formed in the band, the first conductive
A fourth step of implanting high- type impurity ions at a high energy level;
A fifth step of forming a gate insulating film and a source / drain diffusion layer;
A sixth step of forming an emitter diffusion layer, a base diffusion layer, and a collector diffusion layer.

According to this method, since the formation of the first conductivity type well layer in the MOS transistor formation region is performed by implanting high-energy impurity ions, the impurity is implanted in a desired range deep into the semiconductor substrate. I can put it. In other words, the heat treatment for activating the necessary impurities can be completed in a very short time and at a low temperature, so that the first buried layer of the first conductivity type in the bipolar transistor formation region formed up to that time is enlarged. Can be suppressed. Therefore, it is not necessary to increase the depth of the trench, and it is possible to form the trench without spending a time that causes a cost that cannot be actually implemented. That is, a Bi-type transistor having a bipolar transistor having excellent high-frequency characteristics due to a trench structure.
MOS devices can be manufactured in a practical process. Further, a bipolar transistor having good frequency characteristics using an epitaxial layer having good crystallinity can be obtained.

[0034] In the method for manufacturing the above SL semi conductor arrangement, the before the second step, the a step at the boundary portions of the transistor forming region to form an isolation insulating film, the isolation insulating film subsequently on the substrate Forming a mask film having a high etching selectivity with respect to a semiconductor substrate; and forming a mask film on an end of the first buried layer in the bipolar transistor formation region.
Forming an opening in the mask film and the isolation insulating film immediately below the mask film so as to include the first portion, wherein the second step includes the step of forming an opening in the epitaxial growth layer and the semiconductor substrate. The trench can be formed by digging a region below the opening.

According to this method, a trench can be formed without deteriorating the isolation function of the isolation insulating film. Therefore, a Bi-MO suitable for high integration of MOS transistors can be formed.
An S device is formed.

In this case, it is preferable that the isolation insulating film is a silicon oxide film, and in the second step, a trench is formed using the silicon nitride film as a mask.

According to this method, even if a silicon nitride film having a lower etching selectivity with respect to a semiconductor substrate than a silicon oxide film is used as a mask film, the method of manufacturing a semiconductor device according to the present invention allows a trench to be formed as compared with a conventional manufacturing method. Since the depth is shallow and the etching time is short, no problem occurs. Then, when the mask film is removed as in the case where the oxide film is used as a mask, it is possible to prevent the isolation insulating film from becoming thin and impairing the isolation function.

[0038]

[0039]

[0040] In the method for manufacturing the above SL semiconductors devices, the first conductivity type is N-type, it is preferable that the second conductivity type is the P type.

According to this method, an NPN bipolar transistor having electrons having high mobility as a majority carrier is formed, and a Bi-MOS device having excellent high-frequency characteristics can be obtained.

In order to achieve the second object, the present invention provides a means for uniformizing the distribution of defects by rearranging the structure of an insulator consisting of a columnar structure embedded in a trench. To make the etching rate uniform.

That is, in the third step, the tray
Buried film with polycrystalline structure for burying in trench
After the formation of the buried film,
By performing etch back, the upper
The insulating buried film is filled.

According to this method, the heat treatment is performed with the buried film deposited on the substrate including the inside of the trench. Therefore, the third step is provided, and the structure of the insulator in the trench is rearranged by this heat treatment. As a result, the columnar structure is changed to an irregular granular structure, and the distribution of defects is substantially uniformized. Therefore, by etching back under de dry etching method, when leaving a buried film in a trench, the etch rate in the plane is made uniform, reliably prevent the V-grooves on the upper surface of the buried film is formed can do. Therefore, a highly reliable semiconductor device free from disconnection or a bridge in a subsequent process can be formed without adding a further embedding process or an oxide film embedding process.

[0045]

[0046]

[0047]

[0048]

[0049]

[0050]

[0051]

[0052]

[0053] In the method for manufacturing the above SL semi conductor arrangement, it is preferable that the buried layer is a polysilicon film.

According to this method, the junction capacitance between the collector and the substrate in the bipolar transistor formation region is reduced, and a semiconductor device having a bipolar transistor particularly suitable for high frequency operation is formed.

[0055] In the method for manufacturing the above SL semi conductor arrangement, it is preferable that the heat treatment temperature applied to the buried layer is less than 1000 ° C. growth temperature higher than the material constituting the filling layer.

According to this method, the polysilicon crystal in the trench can be rearranged and changed from a columnar structure to an irregular granular structure.

[0057]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) Hereinafter, an embodiment of a method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings.

FIGS. 1 to 11 are sectional views showing the steps of manufacturing a semiconductor device according to the embodiment of the present invention.

First, in the step shown in FIG. 1, the surface on the main surface side of the P-type silicon substrate 1 is oxidized to form a silicon oxide film. Then, etching is performed using a photoresist film (not shown) formed on the silicon oxide film by a lithography method as a mask to selectively remove the silicon oxide film and to form the bipolar transistor formation regions Rbp and Mbp.
An opening 5 is formed in each of the OS transistor formation regions Rmos.
A mask oxide film 2 having 1 and 61 is formed.

Next, using the mask oxide film 2 as a mask,
Ions are deposited on the main surface of the silicon substrate 1 at an acceleration energy of 30 keV and a dose of 1.5 × 10 ¹⁵ /
implanted under the condition of cm ² , and the bipolar transistor region R
Back injection layers 41 and 42 are formed in bp and the MOS transistor formation region Rmos, respectively.

Next, a heat treatment is performed to obtain the deep injection layer 4.
After the arsenic in 1 and 42 is diffused and oxidized to form a step for patterning, the mask oxide film 2 is entirely removed.

Next, in the step shown in FIG. 2, the N-type epitaxial layer 7 is formed over the entire main surface of the P-type silicon substrate 1.
Grow. At this time, arsenic partially diffuses into the epitaxial layer 7 from the deep implantation layers 41 and 42 formed along the main surface of the P-type silicon substrate 1, respectively.
N-type buried layers 81 and 82 having a large depth and width are formed. However, the N-type buried layer 81 in the bipolar transistor formation region Rbp and the MOS transistor formation region Rbp
Epitaxial growth is performed under the condition that the N-type buried layer 82 in mos does not contact. As a result, in the bipolar transistor formation region Rbp, an N-type buried layer 81 is formed over a wide range over the entire bipolar transistor formation region Rbp. In the MOS transistor formation region Rmos, only the PMOSFET formation region Rpmos has the N-type buried layer 82 Is formed.

Next, after a silicon oxide film 9 and a first silicon nitride film 10 are sequentially formed on the epitaxial layer 7, the isolation oxide films 11a to 11a are formed in predetermined isolation regions using a normal LOCOS method. 11e is formed. here,
The isolation oxide film 11a is formed above a region including one end of the N-type buried layer 81 and the outside thereof in the bipolar transistor formation region Rbp.
b is formed above the vicinity of the center of the N-type buried layer 81, and the isolation oxide film 11c is formed above the other end of the N-type buried layer 81 and a region including the outside. The isolation oxide film 11d is formed above the central end of the N-type buried layer 82 in the MOS transistor formation region Rmos, and the isolation oxide film 11e is formed in the MOS transistor formation region Rmos and the region outside thereof. Is formed at the boundary.

Next, in the step shown in FIG. 3, a second silicon nitride film 12 as a mask film is formed on the substrate, and then the isolation oxide films 11a and 11a are formed by lithography and dry etching. The vicinity of the center of the second silicon nitride film 11c and the second silicon nitride film 12 thereon is selectively removed to form trench opening windows 13, respectively. The two trench opening windows 13 define both ends of the bipolar transistor formation region Rbp, and are formed above both ends of the N-type buried layer 81 in the bipolar transistor formation region Rbp.

Next, in the step shown in FIG. 4, trench opening window 1 is formed using second silicon nitride film 12 as a mask.
The silicon substrate exposed in 3 is etched to form a trench 15 having a depth of about 3 μm. further,
Using the second silicon nitride film 12 as a mask, boron ions 14 are supplied at an acceleration energy of 30 keV, for example.
After implantation at a dose of 1.0 × 10 ¹² / cm ² to form a channel stopper layer 17, the substrate surface exposed in the trench 15 is oxidized to form a trench sidewall oxide film 16.
To form

Next, in the step shown in FIG. 5, after a polysilicon film serving as a buried film having a polycrystalline structure is deposited on the substrate, the second silicon nitride film 12 is used as an etching stopper film. Etchback is performed by dry etching to form a buried polysilicon layer 18 in the trench 15.

Next, in the step shown in FIG. 6, by using the second silicon nitride film 12 as a mask, the region immediately below the exposed surface of the buried polysilicon layer 18 is oxidized, so that the isolation oxide film 11a, Cap oxide films 19a and 19b integrated with 11c are formed.

Next, in the step shown in FIG. 7, the first silicon nitride film 10 and the second silicon nitride film 1 are formed.
2 is removed, a lithography method is used to form a photoresist film (not shown) in which only a predetermined region serving as a collector of the bipolar transistor formation region Rbp is opened, and the photoresist film is used as a mask to form phosphorus ions. 20 is implanted under the conditions of, for example, an acceleration energy of 60 keV and a dose of 3.0 × 10 ¹⁵ / cm ² to form a collector wall 21.

Since the trench isolation structure is provided by the series of steps shown in FIGS. 1 to 7, the junction capacitance between the collector and the substrate in the bipolar transistor formation region Rbp is reduced, and the frequency of the bipolar transistor can be increased. Become. Further, since the width of the isolation oxide film 11 can be made shorter than that of the PN junction isolation, the wiring capacitance is reduced, and the frequency can be further increased.

Next, in the step shown in FIG. 8, the PMOS of the MOS transistor formation region Rmos is formed by lithography.
After a photoresist film (not shown) having an opening in the FET formation region Rpmos is formed, boron ions are applied using the photoresist film as a mask, for example, at an acceleration energy of 15 k.
Implantation is performed under the conditions of eV and a dose of 6.3 × 10 ¹² / cm ² to form a threshold voltage control layer 23 of a PMOSFET.
Further, using the same photoresist film as a mask, phosphorus ions 22 are implanted, for example, at an acceleration energy of 160 keV and a dose of 6.6 × 10 4 by a high energy ion implantation method.
Continuous implantation is performed under the condition of ¹² / cm ² to form a punch-through stopper layer 24 below the threshold control layer 23.
Also, using the same photoresist film as a mask, phosphorus ions 22 are implanted under the conditions of, for example, an acceleration energy of 350 keV and a dose of 7.0 × 10 ¹² / cm ² , and a region immediately below the mask oxide film 19b and an oxide for isolation. A channel stopper layer 25 is formed in a region immediately below the film 11d.

Next, in the step shown in FIG. 9, using the same photoresist film as a mask, phosphorus ions 22 are irradiated with, for example, an acceleration energy of 700 keV and a dose of 1.0 × 10 4.
Implantation is performed under the condition of ¹³ ions / cm ² , and an N-type well layer 26 is formed in a wide region extending from immediately below the threshold control layer 23 to below the channel stopper layer 25.

Next, in the step shown in FIG. 10, the NMO of the MOS transistor formation region Rmos is formed by lithography.
A photoresist film (not shown) having an opening only on the SFET formation region Rnmos is formed, and using this photoresist film as a mask, phosphorus ions (not shown) are supplied with, for example, an acceleration energy of 30 keV and a dose of 4.6 × 10 4. ¹² pieces / c
Implantation is performed under the condition of m ² to form a threshold control layer 28 of an NMOSFET. Further, using the same photoresist film as a mask, boron ions 27 are implanted with high energy, for example, at an acceleration energy of 180 keV and a dose of 7.0 × 1.
Implantation is performed under the condition of 0 ¹² / cm ² to form a channel stopper layer 29 extending from a region immediately below the isolation oxide film 11d to a region immediately below the isolation oxide film 11e. afterwards,
Using the same photoresist film as a mask, boron ions 2
7 is implanted under the conditions of, for example, an acceleration energy of 400 keV and a dose of 4.4 × 10 ¹² / cm ² , and a P-type well layer is formed in a wide region from directly below the threshold control layer 28 to below the channel stopper layer 29. Form 30.

Although illustration and description of the subsequent manufacturing steps are omitted, as shown in FIG. 11, finally, the bipolar transistor is composed of a collector diffusion layer 40 formed by epitaxial growth and an oxide for isolation of the collector diffusion layer 40. A base diffusion layer 41 formed on a region between the film 11b and the cap oxide film 19b, an emitter diffusion layer 42 formed so as to be surrounded by the base diffusion layer 41, and a base electrode 43 contacting the base diffusion layer 41. And an emitter electrode 45 contacting the emitter diffusion layer 42, an interelectrode insulating film 44 interposed between the base electrode 43 and the emitter electrode 45, and a collector electrode 46 contacting the collector wall 21.

The PMOSFET has a P-type source diffusion layer 51, a P-type drain diffusion layer 52, and a gate oxide film 5.
5 and a gate electrode 56. NMOSFET
Are N-type source diffusion layer 53 and N-type drain diffusion layer 54
, A gate oxide film 57, and a gate electrode 58.

According to the manufacturing method of this embodiment, the N-type well layer 26 and the P-type well layer 30 are formed by high-energy ion implantation instead of diffusion by heat treatment. That is, it is not a method of forming a surface diffusion layer and then diffusing impurities by heat treatment to form a well layer as in a conventional method of manufacturing a semiconductor device. According to such a method, the impurities can be present in a desired range from the beginning of the ion implantation to the inside of the semiconductor substrate, so that it is not necessary to diffuse the impurities by heat treatment at a high temperature for a long time. Therefore, the heat treatment for activation can be performed in a very short time and at a low temperature, and the expansion of the N-type buried layer 81 in the depth direction in the bipolar transistor formation region Rbp can be suppressed. Therefore, the depth of the trench 15 penetrating through the N-type buried layer 81 in the bipolar transistor formation region Rbp is set to about 3
It can be as shallow as μm. Thereby, the following effects can be exerted.

First, the process time for forming the trench can be reduced. In other words, a bipolar transistor having good high-frequency characteristics and a highly integrated MOS transistor can be formed on a common P-type silicon substrate 1 under practically practicable conditions.

Second, since a nitride film can be used as a trench forming mask, deterioration of the LOCOS isolation function in the MOS transistor formation region Rmos can be prevented. Conventionally, as shown in FIG.
Silicon oxide film 1 on nitride film 118 for S formation
The trench was formed using 20 as a mask. This is to maintain a high selection ratio with the silicon substrate. However, when the silicon oxide film 120 is removed in a later step, the separation oxide film 11 which is the lower LOCOS film is removed.
9b, 119d and 119e are also partially removed, and MOS
There is a problem that the element isolation function of the transistor formation region Rmos is deteriorated. On the other hand, according to the method of the present embodiment, as described above, the trench 15 can be made shallow, so that the time for forming the trench is not so long. Therefore, any material that can provide a certain selectivity even if the selectivity with respect to the silicon substrate is smaller than that of the silicon oxide film can be used as a mask film.
That is, since the selectivity between the second silicon nitride film 12 and the lower isolation oxide films 11b, 11d, 11e can be maintained high, the isolation oxide film 11 which is a LOCOS film can be maintained.
There is an advantage that it is possible to reliably prevent the separation function from being impaired due to the thinning of b, 11d, and 11e.

By leaving the second silicon nitride film 12 in the state shown in the figure in the step shown in the figure, only the upper part of the buried polysilicon layer 18 can be easily selectively oxidized. Thus, the formation of the cap oxide films 19a and 19b can be facilitated. That is, the second silicon nitride film 12 can be used not only as a mask for trench formation but also as a mask for thermal oxidation.

Third, since the etching time for forming the trench is short and the loss of the second nitride film 12 is small, a separate mask is formed when the impurity for forming the channel stopper 17 is implanted. Thus, the channel stopper 17 can be formed in a self-aligned manner. In other words, even if the entire surface of the impurity is implanted without providing a separate mask, the impurity for forming the channel stopper is not introduced into the MOS transistor formation region Rmos.

In each MOS transistor shown in FIG. 11, a sidewall is formed on the side surface of gate electrodes 56 and 58, and a low concentration source diffusion layer and a low concentration drain diffusion layer are provided below the sidewall. A MOS transistor having an LDD structure may be provided. In that case, a MOS transistor which is further miniaturized by the effect of suppressing the short channel effect can be formed.

In the present embodiment, the bipolar transistor is an NPN bipolar transistor. However, the present invention is not limited to this embodiment, and a PNP bipolar transistor may be formed. However, an NPN-type bipolar transistor in which majority carriers are electrons has a higher operation speed, and thus has an advantage that it is more suitable for higher frequencies.

In the present embodiment, the N-type buried diffusion layers 81 and 82 and the regions thereon are formed by the epitaxial growth method. However, the present invention is not limited to such an embodiment, and the present invention is not limited thereto. The buried diffusion layers 81 and 82 may be formed. It is not always necessary to provide the N-type buried diffusion layer 82 in the MOS transistor region.

The types of processing for forming the respective regions of the bipolar transistor and the MOS transistor and the conditions such as the ion implantation amount and the implantation energy in this embodiment are not necessarily limited to the numerical values described in this embodiment. It goes without saying that it is not a thing.

(Second Embodiment) FIGS. 12 and 13 are sectional views showing only characteristic steps of a semiconductor device manufacturing process according to the present embodiment. Also in the present embodiment, steps similar to those shown in FIGS. 1 to 4 in the first embodiment are performed before the step shown in FIG.

That is, using the mask oxide film formed on the main surface side of the P-type silicon substrate 1, a deep injection layer is formed in each of the bipolar transistor region Rbp and the MOS transistor formation region Rmos. Further, an N-type epitaxial layer 7 is formed over the entire main surface of P-type silicon substrate 1.
Is grown, and arsenic is partially diffused into the epitaxial layer 7 from the deep injection layer to form N-type buried layers 81 and 82 having a large depth and width. Next, after a silicon oxide film 9 and a first silicon nitride film 10 are sequentially formed on the epitaxial layer 7, a normal LOC
Separation oxide films 11a to 11e are formed in predetermined isolation regions by using the OS method.
11e is formed. Next, a second mask film is formed on the substrate.
After the silicon nitride film 12 is formed, the vicinity of the center of the isolation oxide films 11a and 11c and the second silicon nitride film 12 thereon is selectively removed to form a trench opening window. Then, the silicon substrate exposed in the trench opening window 13 is etched to form a trench 15 for element isolation. Thereafter, a channel stopper layer 17 and a trench sidewall oxide film 16 are formed.

Next, in a step shown in FIG. 12, a polysilicon film Fps to be a buried film having a polycrystalline structure is formed on the substrate.
Is deposited. At this time, as shown in FIG. 14, in the trench 15, columnar crystal grains grow in a direction perpendicular to the wall surface of the trench 15, so that the ends of the columnar crystal grains concentrate at the center of the trench 15. , Many defects are concentrated.

Here, the feature of the method of manufacturing the semiconductor device according to the present embodiment is that a step of performing annealing at, for example, about 900 ° C. for about 30 minutes while the polysilicon film Fps is deposited is provided. . As a result of this annealing, as shown in FIG. 15, crystal rearrangement occurs, and the structure of the polysilicon changes from a structure in which columnar crystal grains are aggregated to a structure in which amorphous granular crystals are aggregated.

Then, in the step shown in FIG. 13, while using the second silicon nitride film 12 as an etching stopper film, it is etched back by dry etching to form a buried polysilicon layer 18 in the trench 15. .

In this embodiment, since the polysilicon structure in the trench 15 has a texture of irregular granular crystals, the etching rate in the plane is made uniform, and as a result, the buried polysilicon is formed. No V-groove is formed on the upper surface of the silicon layer 18, and a concave portion having a relatively gentle inclination is formed.

Although illustration of subsequent steps is omitted, the same steps as those shown in FIGS. 6 to 11 in the first embodiment are performed, and finally, the steps shown in FIG.
A semiconductor device having the same structure as the structure shown in FIG.

That is, the bipolar transistor has a collector diffusion layer 40 formed by epitaxial growth.
A base diffusion layer 41 formed on a region between the isolation oxide film 11b and the cap oxide film 19b in the collector diffusion layer 40, and an emitter diffusion layer 42 formed so as to be surrounded by the base diffusion layer 41. A base electrode 43 in contact with the base diffusion layer 41, an emitter electrode 45 in contact with the emitter diffusion layer 42, and an interelectrode insulating film 44 interposed between the base electrode 43 and the emitter electrode 45.
And a collector electrode 46 that contacts the collector wall 21.

The PMOSFET has a P-type source diffusion layer 51, a P-type drain diffusion layer 52, a gate oxide film 5
5 and a gate electrode 56. NMOSFET
Are N-type source diffusion layer 53 and N-type drain diffusion layer 54
, A gate oxide film 57, and a gate electrode 58.

According to the manufacturing method of the present embodiment, in the step shown in FIG. 12, a step of performing annealing by heat treatment with the polysilicon film Fps deposited is provided. In addition, the crystal structure of polysilicon changes from the texture of columnar crystal grains to the texture of amorphous crystal grains due to rearrangement, and the distribution of defects such as crystal grain boundaries is substantially uniformized. Therefore, in the step shown in FIG. 13, when the buried polysilicon layer 18 is formed in the trench 15 by etching back by the dry etching method, the in-plane etching rate is made uniform, and the buried polysilicon layer 18 is removed. V-grooves can be reliably prevented from being formed on the upper surface.
Therefore, a highly reliable Bi-CMOS without disconnection or bridging in a subsequent process can be performed without adding a further burying process or an oxide film burying process.
A device can be formed.

In particular, since the heat treatment is performed at 1000 ° C. or less (900 ° C. in the present embodiment) before the buried polysilicon layer 18 is etched back, the channel stopper formed by implanting impurities into the trench bottom is formed. 17
And the N-type buried layers 81 and 82 spread and interfere with each other, thereby suppressing deterioration of breakdown voltage and increase in capacitance component. That is, the structure of the buried polysilicon layer 18 can be improved as long as the effect of the shallow trench is not impaired.

That is, annealing after depositing a polysilicon film is performed at a temperature equal to or higher than the growth temperature
It is preferable to carry out at a temperature of not more than ° C. With this condition,
This is because the above problem can be avoided while rearranging the polysilicon crystal in the trench 15.

FIGS. 25 (a) and 25 (b) are photomicrograph copies showing the crystal structures of the buried polysilicon layer by the conventional manufacturing method and the manufacturing method of the present invention, respectively. As shown in FIG. 25A, in a buried polysilicon layer formed by a conventional manufacturing method, a large number of fine columnar crystal grains extending in a lateral direction of a trench appear to strike at a central portion. I have. On the other hand, in the buried polysilicon layer formed by the manufacturing method of the present invention shown in FIG. 25B, it is shown that columnar crystal grains grow into large amorphous crystal grains.

FIGS. 26 (a) and 26 (b) are microphotographs showing the cross-sectional shapes of the buried polysilicon layer by the conventional manufacturing method and the manufacturing method of the present invention, respectively. As shown in FIG. 26A, a V-groove is formed on the upper surface of a buried polysilicon layer formed by a conventional manufacturing method. On the other hand, in the buried polysilicon layer formed by the manufacturing method of the present invention shown in FIG. 26B, no V-groove is formed on the upper surface, and the upper surface of the entire substrate has a gentle shape.

In this embodiment also, in each MOS transistor, a sidewall is formed on the side surface of the gate electrodes 56 and 58, and a low concentration source diffusion layer and a low concentration drain diffusion layer are provided below the side wall. A MOS transistor having a so-called LDD structure may be provided. In that case, a MOS transistor which is further miniaturized by the effect of suppressing the short channel effect can be formed.

Further, in the present embodiment, a Bi-CMOS device in which a bipolar transistor and a MOS transistor are provided on a common semiconductor substrate is assumed, but the present invention is not limited to such an embodiment. The present invention can be applied to both general MOS transistors and bipolar transistors. Further, the present invention can be applied not only to a transistor but also to, for example, a trench-type capacitance element formed by filling a trench with polysilicon.

Further, when applied to a Bi-CMOS device, the bipolar transistor may be a PNP-type bipolar transistor instead of an NPN-type bipolar transistor. However, an NPN-type bipolar transistor in which majority carriers are electrons has a higher operation speed, and thus has an advantage that it is more suitable for higher frequencies.

Note that the types of processing for forming the respective regions of the bipolar transistor and the MOS transistor and the conditions such as the ion implantation amount and the implantation energy in this embodiment are not necessarily limited to the numerical values described in this embodiment. It goes without saying that it is not a thing.

[0102]

According to the first method of manufacturing a semiconductor device of the present invention, a method of manufacturing a semiconductor device for forming a bipolar transistor and a MOS transistor on the main surface side of a semiconductor substrate is described below. After a buried layer is formed by introducing impurities, a trench reaching the lower end of the buried layer is formed. Further, when a well layer is formed in a MOS transistor formation region, ion implantation of impurities with high energy is performed. Therefore, by suppressing the expansion of the buried layer in the depth direction due to the heat treatment, the depth of the trench can be reduced to such a degree that it can be formed within a time that does not hinder practical use. Practical application of Bi-MOS device in which MOS transistors with high integration are provided on a common substrate It is possible.

According to the second method of manufacturing a semiconductor device of the present invention, as a method of manufacturing a semiconductor device having a buried film having a polycrystalline structure composed of a plurality of crystal grains in a trench, a buried film for filling a trench is provided. Is grown, and then heat-treated and then etched back, so that the etching rate at the time of etching back the buried film is made uniform by a change in the crystal structure of the buried film in the trench, and the V-groove is formed. Therefore, a highly reliable semiconductor device without disconnection or bridge can be formed.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a step of forming a deep injection layer in the manufacturing steps of the semiconductor device according to the first embodiment.

FIG. 2 is a cross-sectional view showing a step of forming an isolation oxide film in the manufacturing steps of the semiconductor device according to the first embodiment.

FIG. 3 is a cross-sectional view showing a step of forming a mask oxide film and a trench opening window in the manufacturing steps of the semiconductor device according to the first embodiment.

FIG. 4 is a cross-sectional view showing a step of forming a trench, a channel stopper layer, and a trench sidewall oxide film in the manufacturing steps of the semiconductor device according to the first embodiment.

FIG. 5 is a cross-sectional view showing a step of forming a buried polysilicon layer in the trench in the manufacturing steps of the semiconductor device according to the first embodiment.

FIG. 6 is a cross-sectional view showing a step of forming a cap oxide film on the trench in the manufacturing steps of the semiconductor device according to the first embodiment.

FIG. 7 is a cross-sectional view illustrating a step of forming a collector wall layer in the manufacturing steps of the semiconductor device according to the first embodiment.

FIG. 8 is a cross-sectional view showing a step of forming a PMOSFET channel stopper in the manufacturing steps of the semiconductor device according to the first embodiment.

FIG. 9 is a cross-sectional view showing a step of forming an N-well layer of the PMOSFET in the manufacturing steps of the semiconductor device according to the first embodiment.

FIG. 10 is a cross-sectional view showing a step of forming a P-well layer of the NMOSFET in the manufacturing steps of the semiconductor device according to the first embodiment.

FIG. 11 is a cross-sectional view showing a state in which formation of main parts of each transistor has been completed in the manufacturing process of the semiconductor device according to the first embodiment.

FIG. 12 is a cross-sectional view showing a step of depositing a polysilicon film for forming a buried polysilicon layer in the manufacturing steps of the semiconductor device according to the second embodiment.

FIG. 13 is a cross-sectional view showing a step of forming a buried polysilicon layer in a trench by etch-back in the manufacturing steps of the semiconductor device according to the second embodiment.

FIG. 14 is a cross-sectional view schematically showing a crystal structure of polysilicon in a trench when a polysilicon film for forming a buried polysilicon layer is formed in a manufacturing process of the semiconductor device according to the second embodiment. .

FIG. 15 is a cross-sectional view schematically showing a crystal structure of polysilicon in a trench after annealing a polysilicon film for forming a buried polysilicon layer in a manufacturing process of the semiconductor device according to the second embodiment. It is.

FIG. 16 is a cross-sectional view showing a step of forming a deep injection layer in a manufacturing process of a semiconductor device according to a conventional example.

FIG. 17 shows N in the manufacturing process of a semiconductor device according to a conventional example.
It is sectional drawing which shows the process of forming a type | mold buried layer and a surface diffusion layer.

FIG. 18 is a cross-sectional view showing a step of forming a mask oxide film in the steps of manufacturing a semiconductor device according to a conventional example.

FIG. 19 is a sectional view showing P in the manufacturing process of a semiconductor device according to a conventional example.
It is sectional drawing which shows the process of forming the P-type injection layer for well regions.

FIG. 20 is a sectional view showing P in the manufacturing process of the semiconductor device according to the conventional example.
FIG. 4 is a cross-sectional view illustrating a step of forming a well region.

FIG. 21 is a cross-sectional view showing a step of forming an oxide film for isolation in a manufacturing process of a semiconductor device according to a conventional example.

FIG. 22 is a cross-sectional view showing a step of forming a mask oxide film and a trench opening window in a manufacturing process of a semiconductor device according to a conventional example.

FIG. 23 is a cross-sectional view showing a step of forming a trench in the manufacturing steps of a semiconductor device according to a conventional example.

FIG. 24 is a cross-sectional view showing a step of forming a buried polysilicon layer in a trench in a manufacturing process of a semiconductor device according to a conventional example.

FIG. 25 is a copy of a micrograph showing a crystal structure of a buried polysilicon layer according to a conventional manufacturing method and a manufacturing method of the present invention in order.

FIG. 26 is a copy of a micrograph showing a cross-sectional shape of a buried polysilicon layer according to a conventional manufacturing method and a manufacturing method of the present invention in order.

[Explanation of symbols]

 Rbp Bipolar transistor formation region Rmos MOS transistor formation region 1 P-type silicon substrate 2 Mask oxide film 3 Arsenic ion 7 Epitaxial layer 9 Silicon oxide film 10 First silicon nitride film 11 Isolation oxide film 12 Second silicon nitride film Reference Signs List 13 trench opening window 14 boron ion 15 trench 16 trench side wall oxide film 17 channel stopper layer 18 buried polysilicon layer 19 cap oxide film 20 phosphorus ion 21 collector wall 22 phosphorus ion 23 threshold control layer 24 punch-through stopper layer 25 channel stopper layer 26 N-type well layer 27 Boron ions 28 Threshold control layer 29 Channel stopper layer 30 P-type well layer 41 Deep injection layer 42 Deep injection layer 51 Opening 61 Opening 81 N-type buried layer 8 N-type buried layer

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-44261 (JP, A) JP-A-6-53442 (JP, A) JP-A-5-21591 (JP, A) JP-A-60-1985 154638 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/06 H01L 21/8249 H01L 21/8222 H01L 21/76 H01L 21/265

Claims (7)

(57) [Claims] 1. A method of manufacturing a semiconductor device comprising: a bipolar transistor that operates with a first conductivity type carrier as a majority carrier; and a MOS transistor that operates with a second conductivity type carrier as a majority carrier. A first conductivity type first impurity doped layer serving as a first buried layer is formed in a bipolar transistor forming region on a main surface side of a semiconductor substrate, and a first conductive layer serving as a second buried layer is formed in a MOS transistor forming region. Forming a second impurity-doped layer of a first conductivity type, and forming a first conductivity type epitaxial growth layer on the semiconductor substrate.
A second step of forming a trench deeper than a lower end of the first buried layer in the bipolar transistor formation region at a boundary between the two transistor formation regions, and filling the trench with an insulating buried film. A third step of forming a channel in at least a region of the MOS transistor formation region including the epitaxial growth layer from immediately below the threshold control layer in the MOS transistor formation region.
A fourth step of implanting high-concentration impurity ions of the first conductivity type so that the first conductivity type well layer is formed in a region below the stopper layer; and forming a gate electrode and a gate in the MOS transistor formation region. A fifth step of forming an insulating film and a source / drain diffusion layer; and a sixth step of forming an emitter diffusion layer, a base diffusion layer, and a collector diffusion layer in the bipolar transistor formation region. Manufacturing method of a semiconductor device. 2. The method for manufacturing a semiconductor device according to claim 1, wherein before the second step, a step of forming an isolation insulating film at a boundary between the two transistor formation regions; forming a high mask film etching selection ratio to the insulating film for isolation and the semiconductor substrate, said to contain the upper portion of said first buried <br/> Me inclusive layer end of the bipolar transistor formation region Forming an opening in the mask film and the isolation insulating film immediately below the mask film. In the second step, the epitaxial growth layer and the upper
A method of manufacturing a semiconductor device, wherein the trench is formed by digging a region below the opening in the semiconductor substrate. 3. The method of manufacturing a semiconductor device according to claim 2, wherein said isolation insulating film is a silicon oxide film, and said trench is formed by using said silicon nitride film as a mask in said second step. Manufacturing method of a semiconductor device. 4. The method of manufacturing a semiconductor device according to any one of claims 1 to 3, the first conductivity type is N-type, the second conductivity type is characterized in that it is a P-type A method for manufacturing a semiconductor device. 5. The method according to claim 1, wherein
The method for manufacturing a semiconductor device according to In the third step, the semiconductor device is buried in the trench.
After forming a buried film with a polycrystalline structure, heat treatment
Do not etch back the buried film after
Fills the trench with the insulating buried film.
A method of manufacturing a semiconductor device. 6. A method according to claim 5 Symbol mounting method of manufacturing a semiconductor device, wherein said buried layer is a polysilicon film. 7. The semiconductor device manufacturing method according to claim 5 , wherein a heat treatment temperature applied to the buried film is not lower than a growth temperature of a material forming the buried film and not higher than 1000 ° C. Manufacturing method.