JPH0411778A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent damage due to a thermal runaway by connecting the drain electrode of a P-channel FET to a gate electrode and composing its source and the base of an NPN transistor of the same P-type layers. CONSTITUTION:A P-FET is formed of a P-type semiconductor base 8, a P- channel 14 and an insulator 15, a drain is connected to a gate via a drain-gate electrode 16, and always opened. An NPN transistor is composed of N-type semiconductor collector 7, emitter 9, P-type semiconductor 8. Here, the drain electrode of a P-FET is connected to a gate electrode, and the source of a P-channel FET and the base 8 of an NPN transistor are formed of the same P-type layers. Then, a current from the base 3 of the NPN transistor to an emitter 2 becomes equal to the drain-source current of the P-FET. Thus, temperature coefficient from the drain-gate terminal to the emitter 2 is reduced to eliminate a damage due to a thermal runaway.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device that eliminates the adverse effects of heat.

[Conventional technology]

Figure 3 shows a conventional N P N 1-transistor (hereinafter referred to as N
FIG. 4 is a cross-sectional view of a Brainer type N P N l-transistor as an example.

In FIG. 3, 1 is a lid, 2 is an emitter, and 3 is a base. Further, in FIG. 4, 7 is the collector of the N-type semiconductor, 8 is the base of the P-type semiconductor, 91 is the emitter of the N-type semiconductor, 1o is an insulator for insulating the semiconductor from the upper electrode of the semiconductor, and 11 is the A base electrode 12 is used to connect the base 8 of the P-type semiconductor to an external circuit, and an emitter electrode 12 is used to connect the emitter 9 of the N-type semiconductor to an external circuit.

Next, the operation will be explained.

By biasing the collector 1 to a higher voltage than the emitter 2 and allowing current to flow from the base 3 to the emitter 2, the current flowing from the collector 1 to the emitter 2 is rolled and amplified.

[Problem to be solved by the invention 1] In the conventional N P N -T r, the current from the base 3 to the emitter 2 has a positive temperature coefficient, so when the temperature becomes high,
The current from base 3 to emitter 2 increases and thus
This results in positive feedback that the temperature of the semiconductor increases. For this reason, there was a problem of destruction due to thermal runaway.

B's invention was made in order to solve the above-mentioned problems, and by obtaining a semiconductor device with a smaller temperature coefficient than the conventional N P N 1 transistor alone, it is possible to create a semiconductor device that is less prone to destruction due to thermal runaway. The purpose is to provide equipment.

[Means to solve the problem]

The semiconductor device according to the present invention has NPN in the same chip.
) transistor and Pf-Yarnel field effect 1- constitute a transistor, connect the drain electrode and gate electrode of the P-channel field-effect transistor, and connect the source of the P-channel field-effect transistor and the base of the transistor are composed of the same P layer.

[Effect]

In this invention, NPN! - Since the temperature coefficient of the P-channel field-effect transistor connected to the base of the transistor is negative, the drage-source current of the P-channel field-effect transistor decreases with increasing temperature.

At this time, the base current to the N P N l - transistor becomes equal to the Si between the drain and the source of the P channel field effect transistor, so when the temperature rises, the N
Compared to a single PNI transistor, the rate of increase in base current is smaller, making it less likely to cause damage due to thermal runaway.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 shows a circuit diagram of the invention, and the second F! ! J1 is shown as an embodiment of the present invention, and is composed of a pulley type NPN resistor (hereinafter referred to as NPN-Tr) and a P channel field effect resistor (hereinafter referred to as P-FET). FIG. 2 is a cross-sectional view of the semiconductor device of FIG.

In Figure 1, 1 is the collector of N P N -Tr, 2 is the emitter of N P N -Tr, and 3 is the collector of N P N -Tr.
The base of N-Tr is the source of P-FET, 4 is the gate of P-FET, 5 is the drain of P-FET, 6 is the gate 4 of P-FET and the drain 5 of P-FET.
This is the terminal connected to. Also, in Figure 2, 7 is N
collector of the P-type semiconductor, 8 is the base of the P-type semiconductor, 9 is the emitter of the N-type semiconductor, 1o is the insulator, 12 is the emitter electrode, 13 is the FL4 pin of the P-type semiconductor, 11LttP-
P channel for depletion of FET, 1
5 is an insulator constituting the insulated gate field effect transistor, and 16 is a drain-gate electrode for connecting the drain and gate of the insulated gate field effect transistor and for connecting to an external circuit.

Next, the operation will be explained.

P-type semiconductor drain, 73. P-type semiconductor path 8. P
Channel 14. P-FE composed of insulator 15
T is connected to drain electrode -1 by drain node 1 to electrode 16, and the channel of the P-FET is always open. In addition, N-type semiconductor collector 7. Base of P-type semiconductor8. An NPNTr is configured by the N-type semiconductor emitter 9.

At this time, the base 8 of the P-type semiconductor of the NPN-Tr is P-F.
Since it is the source of ET, it has the circuit configuration shown in FIG.

In the circuit of FIG. 1, the current from the base 3 to the emitter 2 of the NPN-Tr is equal to the drain-source current of the P-FET. In this case, the temperature coefficient of the do-L ino-source current of the P-FET is negative, so N P N -T
When r has the same configuration, the temperature coefficient from drain data 1 to terminal 6 to emitter 2 of the circuit in Figure 1 is smaller than the temperature coefficient of the current from the base to the emitter of a single NPN-Tr. . , This makes it less likely to cause damage due to thermal runaway than N P N-Tr alone.

〔Effect of the invention〕

As explained above, the present invention provides an NP in the same chip.
A P-channel field effect I-run star is formed by dipping with NI-Lanodisk, and a P-channel field effect is formed.
Connect the do and in electrodes of the transistor and the gate electrode, and connect the NPNI-
Since the bases of the transistors are made of the same P layer, a semiconductor device that is resistant to destruction due to thermal runaway can be obtained.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram according to the present invention, FIG. 2 is a sectional view of a semiconductor device showing an embodiment of the present invention, and FIG. 3 is a conventional N
The circuit symbol diagram of P N -Tr, FIG. 4 is a sectional view of a conventional semiconductor device. In the figure, 1 is the collector, 2 is the emitter, 3 is the base, 4 is the gate, 5 is the drain, 6 is the drain-gate terminal, 7 is the collector of the N-type semiconductor, 8 is the base of the P-type semiconductor, 9 is the N-type Semiconductor emitter, 10.15 is an insulator,
12 is an emitter electrode, 13 is a drain of a P-type semiconductor, 1
4 is a P channel, and 16 is a drain-gate electrode. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent: Masuo Oiwa (2 others) b F Towing Itodentsu

Claims (1)

[Claims] An NPN transistor and a depletion P-channel field-effect transistor are configured in the same chip, the drain electrode and gate electrode of the P-channel field-effect transistor are connected, and the source of the P-channel field-effect transistor and the base of the NPN transistor are the same. 1. A semiconductor device comprising a P layer.