JP2005093763A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2005093763A
JP2005093763A JP2003325841A JP2003325841A JP2005093763A JP 2005093763 A JP2005093763 A JP 2005093763A JP 2003325841 A JP2003325841 A JP 2003325841A JP 2003325841 A JP2003325841 A JP 2003325841A JP 2005093763 A JP2005093763 A JP 2005093763A
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semiconductor device
switch element
state
power
gate
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Koji Takada
浩司 高田
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which prevents lowering of the input voltage for a drive circuit due to the operation of a protective circuit and which is high in reliability, in a power semiconductor device accommodating the protective circuit. <P>SOLUTION: The driving circuit is connected to the IN terminal of the semiconductor device 1, a "high" signal is applied on the IN terminal of the semiconductor device 1, and the signal is transmitted to a power switching element 2, while passing through an n-type diffusion resistor 11 connected to an aluminum wiring 8 via a contact 9. An MOS structure is formed of polysilicon 10 and the n-type diffusion resistor 11, as a variable resistor 5 between the IN terminal and the power switch element 2 for the semiconductor device 1. At normal operation times, a gate intercepting MOS 4, connected between the gate of power switch element 2 and a grounding potential, is set to OFF state, whereby the MOS structure goes to ON state. At detection of abnormalities, the gate intercepting MOS 4 is set to ON state, and the MOS structure goes to OFF state. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、ランプ、LED、インダクタなどの負荷を駆動するパワースイッチ素子に関する。   The present invention relates to a power switch element that drives a load such as a lamp, an LED, and an inductor.

従来、ランプやコイル等の負荷を駆動する手法として、負荷の低電位側に半導体装置を設け、その半導体装置のオン、オフにより、負荷を駆動する方法が一般的によく用いられている。この半導体装置は各種保護機能を一般的に備えている。   Conventionally, as a method for driving a load such as a lamp or a coil, a method of driving a load by providing a semiconductor device on the low potential side of the load and turning on or off the semiconductor device is generally used. This semiconductor device generally has various protection functions.

従来の半導体装置の回路図を図3に示す。   A circuit diagram of a conventional semiconductor device is shown in FIG.

電源7に接続されたランプ、コイル等の負荷6の低電位側に、スイッチとなる半導体装置1が接続されている。   A semiconductor device 1 serving as a switch is connected to a low potential side of a load 6 such as a lamp or a coil connected to a power source 7.

この半導体装置1は、異常検出回路3を備えており、負荷6に過電流が流れるとその電流に応じたパワースイッチ素子2のドレイン端子(D端子)電位の変動を検出して、ゲート遮断MOS4のゲートにオン信号を送る。その結果、ゲート遮断MOS4がオンして、そのドレイン端子およびドレイン端子に接続されたパワースイッチ素子2のゲートの電位が0V近くになるため、パワースイッチ素子2がオフし、過電流による破壊から守られる(例えば、特許文献1参照)。   The semiconductor device 1 includes an abnormality detection circuit 3. When an overcurrent flows through the load 6, the semiconductor device 1 detects a change in the potential of the drain terminal (D terminal) of the power switch element 2 according to the current and detects a gate cutoff MOS 4. Send an ON signal to the gate. As a result, the gate cut-off MOS 4 is turned on, and the potential of the gate of the power switch element 2 connected to the drain terminal and the drain terminal is close to 0 V. Therefore, the power switch element 2 is turned off and is protected from destruction due to overcurrent. (See, for example, Patent Document 1).

また、負荷6に過電流保護が働かない程度で、長時間電流が流れ続けたり、過電流保護はかかるが、その状態が長く続き、半導体装置の温度が上がり過ぎた場合にも、異常検出回路3が働き、ゲート遮断MOS4のゲートにオン信号を送り、そのゲート遮断MOSのドレイン端子は0V近くになりパワースイッチ素子2をオフし破壊から守る。   In addition, even if the current continues to flow for a long time or overcurrent protection is applied to the extent that the overcurrent protection does not act on the load 6, the abnormality detection circuit is also activated when the state continues for a long time and the temperature of the semiconductor device rises excessively. 3 works to send an ON signal to the gate of the gate cut-off MOS 4 and the drain terminal of the gate cut-off MOS becomes close to 0V to turn off the power switch element 2 to protect it from destruction.

次に上記従来の半導体装置の断面構造図を図4に示す。   Next, FIG. 4 shows a cross-sectional structure diagram of the conventional semiconductor device.

半導体装置1のIN端子には半導体装置1を制御するためにマイコン等の駆動回路が接続され、各種保護が働いた場合、ゲート遮断MOS4のゲートにオン信号を送り、そのゲート遮断MOS4のドレイン端子は0V近くになるため、半導体装置1のIN端子からパワースイッチ素子2のゲートG間に接続された抵抗12に、マイコン等の制御素子から電流が流れ込む。   A drive circuit such as a microcomputer is connected to the IN terminal of the semiconductor device 1 to control the semiconductor device 1 and when various protections are activated, an ON signal is sent to the gate of the gate cutoff MOS 4 and the drain terminal of the gate cutoff MOS 4 Is close to 0 V, so that a current flows from a control element such as a microcomputer into the resistor 12 connected between the IN terminal of the semiconductor device 1 and the gate G of the power switch element 2.

上記抵抗12は一般にポリシリコン抵抗が用いられるが、パワースイッチ素子2のスイッチングスピードを早くするため、低抵抗に設定される。この場合、電流異常や温度異常等に対して各種保護が働いた場合、半導体装置1の入力電流が大きいため、マイコン等の制御素子は入力電圧を維持出来なくなる。   The resistor 12 is generally a polysilicon resistor, but is set to a low resistance in order to increase the switching speed of the power switch element 2. In this case, when various protections are applied against current abnormality, temperature abnormality, etc., the input current of the semiconductor device 1 is large, so that a control element such as a microcomputer cannot maintain the input voltage.

近年は特に電源装置の省エネルギー化のため、マイコン等の駆動回路における電流能力は下がって来ている。このような場合、異常電流等により回路の保護機能が働き、パワースイッチ素子はオフされるが、駆動回路の入力電圧が低下してくるため、半導体装置1のIN電圧が下がり、異常検出回路3が作動しなくなってしまう。異常検出回路ブロック3は横型MOS、抵抗、ダイオード、ツェナーダイオード等がP型拡散層の中、あるいは上に作られ回路を構成している。パワースイッチ素子2は低い電圧でもオンするため、異常電流等が流れているにもかかわらず、異常検出回路3が機能せず、パワースイッチ素子2は破壊に至る。
特開2002−100972号公報(第4図)
In recent years, the current capability in a drive circuit such as a microcomputer has been lowered particularly in order to save energy of a power supply device. In such a case, the protection function of the circuit is activated by an abnormal current or the like, and the power switch element is turned off. Will not work. In the abnormality detection circuit block 3, a lateral MOS, a resistor, a diode, a Zener diode, etc. are formed in or on the P-type diffusion layer to constitute a circuit. Since the power switch element 2 is turned on even at a low voltage, the abnormality detection circuit 3 does not function even though an abnormal current flows, and the power switch element 2 is destroyed.
Japanese Patent Laid-Open No. 2002-1000097 (FIG. 4)

上記従来の技術を用いた場合、入力端子から流れ込む電流を小さくして、マイコン等の制御素子の電圧で確実に異常検出回路3の動作を継続させるためには、半導体装置1の入力端子からパワースイッチ素子のゲート間に接続された抵抗値を高くする方法があるが、この場合パワースイッチ素子2のスイッチングスピードの遅れが大きくなり、負荷のオン・オフのスイッチング動作を遅れなく正確に制御する事が出来ない。半導体装置1のIN端子からパワースイッチ素子2のゲート間に接続された抵抗値を小さくすると従来技術で述べた様に異常状態が長引いたりすると、駆動回路の入力電圧が下がり異常検出回路3が働かなくなり、パワースイッチ素子2はオンし、破壊に至る。   When the above conventional technique is used, in order to reduce the current flowing from the input terminal and reliably continue the operation of the abnormality detection circuit 3 with the voltage of the control element such as a microcomputer, the power from the input terminal of the semiconductor device 1 is used. There is a method of increasing the resistance value connected between the gates of the switch elements. In this case, the delay of the switching speed of the power switch element 2 becomes large, and the switching operation of the load on / off can be accurately controlled without delay. I can't. If the resistance value connected between the IN terminal of the semiconductor device 1 and the gate of the power switch element 2 is reduced, if the abnormal state is prolonged as described in the prior art, the input voltage of the drive circuit is lowered and the abnormality detection circuit 3 is activated. The power switch element 2 is turned on, leading to destruction.

上記課題を解決するために、本発明の半導体装置は、パワー素子とその制御回路を備えた半導体装置であって、前記制御回路は、前記パワー素子に流れる電流または温度の異常を検出する異常検出回路と、前記異常検出回路からの出力信号に応じて前記パワー素子への入力を遮断するスイッチ素子と、前記パワー素子の入力端子に接続され、前記異常検出回路からの出力信号に応じて抵抗値が変化する可変抵抗体とを備えたことを特徴とする。   In order to solve the above-described problems, a semiconductor device of the present invention is a semiconductor device including a power element and a control circuit for the power element, and the control circuit detects an abnormality in current or temperature flowing through the power element. A circuit, a switch element that cuts off an input to the power element in accordance with an output signal from the abnormality detection circuit, and a resistance value that is connected to an input terminal of the power element and in accordance with an output signal from the abnormality detection circuit And a variable resistor that changes.

また、上記半導体装置は、前記異常検出回路からの出力信号により前記スイッチ素子がオン状態であるときは、前記可変抵抗体は高抵抗値となり、前記異常検出回路からの出力信号により前記スイッチ素子がオフ状態であるときは、前記可変抵抗体は低抵抗値となるものである。   In the semiconductor device, when the switch element is turned on by an output signal from the abnormality detection circuit, the variable resistor has a high resistance value, and the switch element is turned on by an output signal from the abnormality detection circuit. When in the off state, the variable resistor has a low resistance value.

さらに、前記可変抵抗体はMOS構造と高抵抗体との並列抵抗からなり、前記スイッチ素子がオフ状態であるときは、前記MOS構造がオン状態となって低抵抗値となり、前記スイッチ素子がオン状態であるときは、前記MOS構造がオフ状態となって高抵抗となるものである。   Further, the variable resistor comprises a parallel resistance of a MOS structure and a high resistor, and when the switch element is in an off state, the MOS structure is in an on state and has a low resistance value, and the switch element is on. When it is in a state, the MOS structure is turned off and has a high resistance.

前記高抵抗体として前記MOS構造が形成された半導体基板の拡散抵抗を用いることが好ましい。   It is preferable to use a diffusion resistance of a semiconductor substrate on which the MOS structure is formed as the high resistance body.

また、前記パワー素子がN型MOSFETで構成されることが好ましいが、IGBTで構成されていても、バイポーラトランジスタで構成されていてもよい。   The power element is preferably composed of an N-type MOSFET, but may be composed of an IGBT or a bipolar transistor.

また、本発明の半導体装置において、前記パワー素子は負荷を介して電源に接続されており、その入力端子には前記パワー素子を駆動するための駆動回路が接続されていることが好ましい。   In the semiconductor device of the present invention, it is preferable that the power element is connected to a power source through a load, and a drive circuit for driving the power element is connected to an input terminal of the power element.

本発明によれば、IN端子に接続されるマイコン等の駆動回路の電流能力が低くとも使用可能であり、パワースイッチ素子2のスイッチングスピードを落とす事なく、ランプ、LED、インダクタなどの負荷を駆動するパワースイッチ素子2に関し、過電流、短絡電流が流れた場合や、その電流でパワースイッチ素子2が発熱した場合、パワースイッチ素子2の入力を低電位にし、パワースイッチ素子2をオフして破壊から守り、信頼性を向上させる。   According to the present invention, a drive circuit such as a microcomputer connected to the IN terminal can be used even if the current capability is low, and loads such as lamps, LEDs, and inductors are driven without reducing the switching speed of the power switch element 2. When an overcurrent or a short-circuit current flows or the power switch element 2 generates heat due to the current, the input of the power switch element 2 is set to a low potential and the power switch element 2 is turned off to be destroyed. Protect from and improve reliability.

以下、本発明の実施の形態について、図を用いて説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

図1は本発明の実施の形態における半導体装置の回路図であり、図3と比較すると、IN端子からパワースイッチ素子2のゲートの間に接続される抵抗が可変抵抗体5である点が異なり、それ以外は同じ構成である。   FIG. 1 is a circuit diagram of a semiconductor device according to an embodiment of the present invention, and differs from FIG. 3 in that the resistor connected between the IN terminal and the gate of the power switch element 2 is a variable resistor 5. The rest of the configuration is the same.

上記可変抵抗体の構造模式図を図2に示す。(a)は平面図であり、(b)は図2(a)に示したA−A’方向の断面図である。   A schematic diagram of the structure of the variable resistor is shown in FIG. (A) is a top view, (b) is sectional drawing of the A-A 'direction shown to Fig.2 (a).

図2(a)に示すように、半導体装置1(図示せず)のIN端子には半導体装置1を制御するためにマイコン等の駆動回路(図示せず)が接続され、通常動作時はハイ信号(例えば5V)が半導体装置1のIN端子に加えられ、コンタクト9を介してアルミ配線8に接続されたN型拡散抵抗11を通りパワースイッチ素子2のゲートに信号が伝わる。   As shown in FIG. 2A, a drive circuit (not shown) such as a microcomputer is connected to the IN terminal of the semiconductor device 1 (not shown) to control the semiconductor device 1 and is high during normal operation. A signal (for example, 5 V) is applied to the IN terminal of the semiconductor device 1, and the signal is transmitted to the gate of the power switch element 2 through the N-type diffusion resistor 11 connected to the aluminum wiring 8 through the contact 9.

また、図2(b)に示すように、ポリシリコン10とN型拡散抵抗11とでMOS構造が形成されており、ゲート酸化膜(図示せず)上に形成されたポリシリコン10に電圧が加わると、その真下にキャリアの流れる通路(以下、チャンネルという。)が出来て、IN端子からの信号は矢印の様に流れる。   Further, as shown in FIG. 2B, a MOS structure is formed by the polysilicon 10 and the N-type diffused resistor 11, and a voltage is applied to the polysilicon 10 formed on the gate oxide film (not shown). When added, a passage (hereinafter referred to as a channel) through which the carrier flows is formed immediately below, and a signal from the IN terminal flows as shown by an arrow.

半導体装置1の動作を以下に詳細に説明する。まず、正常動作時において、異常検出回路3からゲート遮断MOS4のゲートに0Vの電圧信号が送られるため、ゲート遮断MOS4はオフ状態であり、そのドレイン電位は高電位に保たれる。このドレインはパワースイッチ素子2のゲートと接続されているため、パワースイッチ素子2はオン状態となる。この場合において、異常検出回路3からポリシリコン10に対してアルミ配線8、さらにコンタクト9を介して、前記MOS構造のしきい値電圧以上の信号が加わる。このポリシリコン10は、N型拡散抵抗11とオーバーラップしている。   The operation of the semiconductor device 1 will be described in detail below. First, during normal operation, since a voltage signal of 0 V is sent from the abnormality detection circuit 3 to the gate of the gate cutoff MOS 4, the gate cutoff MOS 4 is in an off state and its drain potential is kept at a high potential. Since this drain is connected to the gate of the power switch element 2, the power switch element 2 is turned on. In this case, a signal equal to or higher than the threshold voltage of the MOS structure is applied from the abnormality detection circuit 3 to the polysilicon 10 through the aluminum wiring 8 and the contact 9. The polysilicon 10 overlaps with the N-type diffused resistor 11.

この場合において、MOS構造がオンして、ポリシリコン10直下でチャンネルが形成されるため、半導体装置1のIN端子とパワースイッチ素子2との間は低抵抗に保たれる。   In this case, since the MOS structure is turned on and a channel is formed immediately below the polysilicon 10, the resistance between the IN terminal of the semiconductor device 1 and the power switch element 2 is kept low.

一方、負荷に過電流が流れる等して保護回路が動作する場合、異常検出回路3からゲート遮断MOS4のゲートにオン信号が入力して、パワー遮断MOS4が導通し、そのドレイン電位はソース電位、すなわち、接地電位とほぼ同電位になるため、ゲート遮断MOS4のドレイン端子は0V近くになる。また、ゲート遮断MOS4のゲートにオン信号を送ると同時に、異常検出回路3からアルミ配線8とコンタクト9を介してポリシリコン10に0Vの電圧信号が送られる。この結果、ポリシリコン10の真下に形成されていたチャンネルは閉じられ、IN端子からの信号はN型拡散抵抗11を通って、コンタクト9を介してアルミ配線8で接続されたパワースイッチ素子2のゲートに信号が送られる。この場合、N型拡散抵抗11の抵抗値はシート抵抗とU字部分の距離の乗算であり、上記MOS構造のチャンネル抵抗と比較して十分に高い抵抗値となる。このため、抵抗を流れる電流は十分に小さくなり、駆動回路の入力電圧の低下がほとんど起こらないため、異常検出回路3が働き続け、パワースイッチ素子2はオフ状態が保たれるため、破壊しない。   On the other hand, when the protection circuit operates due to an overcurrent flowing through the load or the like, an ON signal is input from the abnormality detection circuit 3 to the gate of the gate cutoff MOS4, the power cutoff MOS4 becomes conductive, and the drain potential is the source potential, That is, since the potential is substantially the same as the ground potential, the drain terminal of the gate cutoff MOS 4 is close to 0V. At the same time as the ON signal is sent to the gate of the gate cutoff MOS 4, a voltage signal of 0V is sent from the abnormality detection circuit 3 to the polysilicon 10 through the aluminum wiring 8 and the contact 9. As a result, the channel formed immediately below the polysilicon 10 is closed, and the signal from the IN terminal passes through the N-type diffused resistor 11 and passes through the contact 9 to the power switch element 2 connected by the aluminum wiring 8. A signal is sent to the gate. In this case, the resistance value of the N-type diffusion resistor 11 is a product of the sheet resistance and the distance between the U-shaped portions, and becomes a sufficiently high resistance value as compared with the channel resistance of the MOS structure. For this reason, the current flowing through the resistor becomes sufficiently small and the input voltage of the drive circuit hardly decreases, so that the abnormality detection circuit 3 continues to operate and the power switch element 2 is kept in the OFF state and is not destroyed.

以上のように本実施の形態によれば、MOS構造の可変抵抗体をパワースイッチ素子のゲートと、駆動回路が接続された入力端子との間に配置することにより、通常の動作時にはMOS構造が導通して低抵抗が保たれ、また異常動作時にはMOS構造が遮断して高抵抗が保たれる。よって、スイッチングスピードを低下させることなく、負荷のオン・オフのスイッチング動作を遅れなく正確に制御する事が出来ると同時に、異常時の回路保護も確実に行えるものである。   As described above, according to the present embodiment, the MOS structure variable resistor is arranged between the gate of the power switch element and the input terminal to which the drive circuit is connected, so that the MOS structure can be obtained during normal operation. When conducting, the low resistance is maintained, and during abnormal operation, the MOS structure is cut off and the high resistance is maintained. Therefore, it is possible to accurately control the on / off switching operation of the load without delay without reducing the switching speed, and at the same time, it is possible to reliably protect the circuit in the event of an abnormality.

なお、本実施の形態では、可変抵抗体をなすMOS構造のゲート電極材料としてポリシリコンを用いたが、他の金属材料、例えばアルミ配線等であってもよい。また、可変抵抗体としてNMOS構造を示したが、N型基板上にPMOSが形成される構造であってもよい。   In the present embodiment, polysilicon is used as the gate electrode material of the MOS structure forming the variable resistor, but other metal materials such as aluminum wiring may be used. Moreover, although the NMOS structure is shown as the variable resistor, a structure in which a PMOS is formed on an N-type substrate may be used.

また、本実施の形態では、パワースイッチ素子2としてN型MOSFETで構成される例を示したが、IGBTで構成されていても、バイポーラトランジスタで構成されていてもよい。   In the present embodiment, an example in which the power switch element 2 is configured by an N-type MOSFET has been described. However, the power switch element 2 may be configured by an IGBT or a bipolar transistor.

本発明に係る半導体装置は、回路保護機能を備えたパワー半導体装置、特に低電圧で駆動する制御素子を用いる半導体装置として有用である。   The semiconductor device according to the present invention is useful as a power semiconductor device having a circuit protection function, particularly a semiconductor device using a control element driven at a low voltage.

本発明の実施の形態における半導体装置の回路図Circuit diagram of a semiconductor device in an embodiment of the present invention 本発明の実施の形態における可変抵抗体の構造模式図であり、(a)は平面図、(b)は図2(a)に示したA−A’方向の断面図It is a structure schematic diagram of the variable resistor in embodiment of this invention, (a) is a top view, (b) is sectional drawing of the A-A 'direction shown to Fig.2 (a). 従来の技術における半導体装置の回路図Circuit diagram of conventional semiconductor device 従来の技術における半導体装置の断面構造図Cross-sectional structure diagram of conventional semiconductor device

符号の説明Explanation of symbols

1 半導体装置
2 パワースイッチ素子
3 異常検出回路
4 ゲート遮断MOS
5 可変抵抗体
6 負荷
7 電源
8 アルミ配線
9 コンタクト
10 ポリシリコン
11 N型拡散抵抗
12 抵抗
DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Power switch element 3 Abnormality detection circuit 4 Gate interruption | blocking MOS
5 Variable Resistor 6 Load 7 Power Supply 8 Aluminum Wiring 9 Contact 10 Polysilicon 11 N-type Diffusion Resistance 12 Resistance

Claims (8)

パワー素子とその制御回路を備えた半導体装置であって、
前記制御回路は、
前記パワー素子に流れる電流または温度の異常を検出する異常検出回路と、
前記異常検出回路からの出力信号に応じて前記パワー素子への入力を遮断するスイッチ素子と、前記パワー素子の入力端子に接続され、前記異常検出回路からの出力信号に応じて抵抗値が変化する可変抵抗体とを備えたことを特徴とする半導体装置。
A semiconductor device comprising a power element and its control circuit,
The control circuit includes:
An abnormality detection circuit for detecting an abnormality in current or temperature flowing in the power element;
A switch element that cuts off the input to the power element in response to an output signal from the abnormality detection circuit and an input terminal of the power element, and a resistance value changes in accordance with an output signal from the abnormality detection circuit. A semiconductor device comprising a variable resistor.
前記異常検出回路からの出力信号により前記スイッチ素子がオン状態であるときは、前記可変抵抗体は高抵抗値となり、
前記異常検出回路からの出力信号により前記スイッチ素子がオフ状態であるときは、前記可変抵抗体は低抵抗値となることを特徴とする請求項1記載の半導体装置。
When the switch element is turned on by an output signal from the abnormality detection circuit, the variable resistor has a high resistance value,
2. The semiconductor device according to claim 1, wherein the variable resistor has a low resistance value when the switch element is in an OFF state by an output signal from the abnormality detection circuit.
前記可変抵抗体はMOS構造と高抵抗体との並列抵抗からなり、前記スイッチ素子がオフ状態であるときは、前記MOS構造がオン状態となって低抵抗値となり、
前記スイッチ素子がオン状態であるときは、前記MOS構造がオフ状態となって高抵抗となることを特徴とする請求項2記載の半導体装置。
The variable resistor comprises a parallel resistance of a MOS structure and a high resistor, and when the switch element is in an off state, the MOS structure is in an on state and has a low resistance value.
3. The semiconductor device according to claim 2, wherein when the switch element is in an on state, the MOS structure is in an off state and has a high resistance.
前記高抵抗体として前記MOS構造が形成された半導体基板の拡散抵抗を用いることを特徴とする請求項3記載の半導体装置。 4. The semiconductor device according to claim 3, wherein a diffusion resistance of a semiconductor substrate on which the MOS structure is formed is used as the high resistance body. 前記パワー素子がN型MOSFETで構成されることを特徴とする請求項1ないし4のいずれかに記載の半導体装置。 The semiconductor device according to claim 1, wherein the power element is formed of an N-type MOSFET. 前記パワー素子がIGBTで構成されることを特徴とする請求項1ないし4のいずれかに記載の半導体装置。 The semiconductor device according to claim 1, wherein the power element is formed of an IGBT. 前記パワー素子がバイポーラトランジスタで構成されることを特徴とする請求項1ないし4のいずれかに記載の半導体装置。 5. The semiconductor device according to claim 1, wherein the power element is a bipolar transistor. 前記パワー素子は負荷を介して電源に接続されており、その入力端子には前記パワー素子を駆動するための駆動回路が接続されていることを特徴とする請求項1ないし7のいずれかに記載の半導体装置。 8. The power element is connected to a power source via a load, and a drive circuit for driving the power element is connected to an input terminal of the power element. Semiconductor device.
JP2003325841A 2003-09-18 2003-09-18 Semiconductor device Pending JP2005093763A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7733133B2 (en) * 2008-01-10 2010-06-08 Nec Electronics Corporation Power switch circuit having variable resistor coupled between input terminal and output transistor and changing its resistance based on state of output transistor
KR20170064490A (en) 2015-12-01 2017-06-09 다이요 유덴 가부시키가이샤 Dielectric material for multilayer ceramic capacitor, and multilayer ceramic capacitor

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60132355A (en) * 1983-12-20 1985-07-15 Sanyo Electric Co Ltd Semiconductor device
JPH06244414A (en) * 1993-02-22 1994-09-02 Hitachi Ltd Protective circuit and semiconductor device containing the same
JPH09116101A (en) * 1995-10-24 1997-05-02 Hitachi Ltd Built-in control circuit insulation gate type semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60132355A (en) * 1983-12-20 1985-07-15 Sanyo Electric Co Ltd Semiconductor device
JPH06244414A (en) * 1993-02-22 1994-09-02 Hitachi Ltd Protective circuit and semiconductor device containing the same
JPH09116101A (en) * 1995-10-24 1997-05-02 Hitachi Ltd Built-in control circuit insulation gate type semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7733133B2 (en) * 2008-01-10 2010-06-08 Nec Electronics Corporation Power switch circuit having variable resistor coupled between input terminal and output transistor and changing its resistance based on state of output transistor
KR20170064490A (en) 2015-12-01 2017-06-09 다이요 유덴 가부시키가이샤 Dielectric material for multilayer ceramic capacitor, and multilayer ceramic capacitor

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