JPS60132356A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60132356A JPS60132356A JP24121983A JP24121983A JPS60132356A JP S60132356 A JPS60132356 A JP S60132356A JP 24121983 A JP24121983 A JP 24121983A JP 24121983 A JP24121983 A JP 24121983A JP S60132356 A JPS60132356 A JP S60132356A
- Authority
- JP
- Japan
- Prior art keywords
- region
- transistor
- pair
- regions
- resistance regions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 5
- 239000010410 layer Substances 0.000 description 19
- 238000010586 diagram Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000002344 surface layer Substances 0.000 description 3
- 108091006146 Channels Proteins 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0744—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common without components of the field effect type
- H01L27/075—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. lateral bipolar transistor, and vertical bipolar transistor and resistor
- H01L27/0755—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
- H01L27/0772—Vertical bipolar transistor in combination with resistors only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は、電圧スイ・リチング回路等に用いられる半導
体装置に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a semiconductor device used in a voltage switching/liching circuit or the like.
（川 従来技術
従来の電圧スイ・リチング回路を具備したパワーアンプ
に用いられる過電圧保護回路は、第５図に示すようなも
のである。３個のトランジスタ（’ｒ ｒ １）（Ｔｒ
２）（Ｔｒ３） 、１！： ５個の抵抗（Ｒ１）−（Ｒ
ｓ） トチ電圧スイ・リチング回路（支））を構成し、
このスイ・９チング回路■）により、スピーカ等に信号
を出力する出力トランジスタ（Ｔｒｓ）のドライバート
ランジスタ（Ｔｒりを動作せしめて、過電圧に対して装
置を保護するものである。すなわち、電源電圧（Ｖ ｃ
ｃ）が所定値より上昇すると、抵抗（ｋ６）および抵抗
（Ｒ４）に流れる電流が所定値を越え、そのため抵抗（
Ｒ４）の両端にかかる電圧が閾値電圧より上昇し、トラ
ンジスタ（Ｔｒｚ）がＯＮする。すると抵抗（Ｒ５）に
電流が流れ、その両端の電位差が太き（なりトランジス
タ（′ｒ「りのベースにバイアスがかかり、トランジス
タ（Ｔｚ）がＯＮする。トランジスタ（Ｔｚ）がＯＮす
ることにより、抵抗（Ｒ２）に電流が流れ、その両端に
電位差が生じ、トランジスタ（ＴｒＱがＯＮする。トラ
ンジスタ（Ｔｒ３）がＯＮすると、ドライバトランジス
タ（Ｔｒ４）のベースが接地し、トランジスタ（Ｔｚ）
を強制的にＯＦ Ｆさせ、出力トランジスタ（Ｔｒ５）
のベース電流の供給を停止せしめ、出力トランジスタ（
Ｔｒｓ）をＯＦＦさせるようになっている。(Prior Art) An overvoltage protection circuit used in a power amplifier equipped with a conventional voltage switching circuit is as shown in Fig. 5.Three transistors ('r r 1) (Tr
2) (Tr3), 1! : 5 resistors (R1) - (R
s) Configure the Tochi voltage switch/liching circuit (support),
This switching circuit (■) operates the driver transistor (Tr) of the output transistor (Trs) that outputs a signal to a speaker, etc., and protects the device against overvoltage.In other words, the power supply voltage ( V c
When c) rises above a predetermined value, the current flowing through resistor (k6) and resistor (R4) exceeds the predetermined value, so that resistor (
The voltage applied across R4) rises above the threshold voltage, and the transistor (Trz) turns on. Then, a current flows through the resistor (R5), and the potential difference between its ends becomes large.A bias is applied to the base of the transistor ('r), and the transistor (Tz) turns on.By turning on the transistor (Tz), Current flows through the resistor (R2), creating a potential difference across it, turning on the transistor (TrQ). When the transistor (Tr3) turns on, the base of the driver transistor (Tr4) is grounded, and the transistor (Tz)
is forcibly turned off, and the output transistor (Tr5)
stops supplying the base current of the output transistor (
Trs) is turned off.
しかしながら、この従来装置では、３個のトランジスタ
（ＴｒＱ・・・（Ｔｒ３）および５個の抵抗（Ｒ１）・
・・（Ｒ５）の計８個の素子を必要とし、装置が複雑に
なる。However, in this conventional device, three transistors (TrQ...(Tr3) and five resistors (R1)...
A total of eight elements (R5) are required, making the device complicated.
ヒ＼）発明の目的
本発明は、上述した難点を解消すべくなされたもので、
電圧スイッチング回路を少ない素子数で確実に動作せし
めることのできる装置を提供することを目的とする。H\) Purpose of the Invention The present invention has been made to solve the above-mentioned difficulties.
It is an object of the present invention to provide a device that can reliably operate a voltage switching circuit with a small number of elements.
に））発明の構成
本発明は、−導電型の第１領域、この領域に形成された
少なくとも一対の他導電型の抵抗領域、この一対の抵抗
領域間に絶縁層を介して跨る。電極層を具備し、前記第
１領域と電極層との間に印加される電圧値に応じて、前
記一対の抵抗領域間に両抵抗領域間を導通させるチャン
ネルが形成されることを特徴とする半導体装置である。B)) Structure of the Invention The present invention includes a first region of a negative conductivity type, at least a pair of resistance regions of a different conductivity type formed in this region, and an insulating layer extending between the pair of resistance regions. The device comprises an electrode layer, and a channel is formed between the pair of resistance regions to provide electrical continuity between the two resistance regions, depending on a voltage value applied between the first region and the electrode layer. It is a semiconductor device.
（ホ）実施例
以上、本発明の一実施例を、第１図ないし第４図を参照
して説明する。第１図は本発明の要部を示すＹ面図、第
２図は同断面図である。(E) Embodiment An embodiment of the present invention will now be described with reference to FIGS. 1 to 4. FIG. 1 is a Y-plane view showing essential parts of the present invention, and FIG. 2 is a sectional view thereof.
第１図および第２図において、（１）はＰ８！！シリコ
ン基板、（２）は基板（１）表面に形成されたＮ型のエ
ピタキシャル層である。（３）は濃度の低いＰ−型の第
１領域で、イオン注入法や拡散法などによりエピタキシ
ャル層（２１に形成される。（４）はへ型の抵抗領域で
、第１領域（３）に少なくとも一対形成されている。In Figures 1 and 2, (1) is P8! ! The silicon substrate (2) is an N-type epitaxial layer formed on the surface of the substrate (1). (3) is a low concentration P- type first region, which is formed in the epitaxial layer (21) by ion implantation or diffusion method. (4) is a hemi-shaped resistance region; At least one pair is formed.
この抵抗領域（４）は本実施例では一対形成しているが
、必要に応じて、それ以上形成しても良い。（５）は二
酸化シリコン（Ｓｉ０２）からなる絶縁層で、前記表面
を熱酸化するなどして形成される。（６）は第１の電極
層で、抵抗領域ｆ４）（４１間に絶縁層（５）を介を分
離する。（７）は第１領域（３）に配置された第２の電
極層で、この電極層（７）により、第１領域（３）の電
極取り出しと配線が行われる。また、第１領域（３）に
は、第１の電極層（６）の下に位１−する第１領域（３
）の表面層部分の全てがＰ−型からＮ型へと反転するの
を防止する１こめのＰ型のチャンネルスト・リパ（８）
が形成されている。尚、図中（９１（１０）は、他の素
子、例えば後述する第３図に示す、トランジスタ（Ｔｒ
ｌ）や抵抗（Ｒ２１）などと配線する電極層である。In this embodiment, a pair of resistor regions (4) are formed, but more resistor regions (4) may be formed as required. (5) is an insulating layer made of silicon dioxide (Si02), which is formed by thermally oxidizing the surface. (6) is the first electrode layer, which is separated by the insulating layer (5) between the resistance regions f4) (41). (7) is the second electrode layer arranged in the first region (3). This electrode layer (7) performs electrode extraction and wiring in the first region (3).Also, in the first region (3), there is a layer located below the first electrode layer (6). First area (3
) One P-type channel stripper (8) that prevents the entire surface layer of the P-type from converting from P-type to N-type.
is formed. Note that (91 (10) in the figure indicates other elements, such as a transistor (Tr) shown in FIG. 3, which will be described later.
This is an electrode layer that is connected to the resistor (R21) and the resistor (R21).
而して、前記第１領域（３）と第１の電極層（６）との
間に印加される電圧値に応じて、一対の抵抗領域（４１
（４１間に、両抵抗領域（４１（４）間を導通せしめる
チャンネルが形成される。すなわち、第１、第２電極層
＋６）（７１間に印加される電圧がある閾値を越えると
、抵抗領域（４１（４１間に介在するＰ〜型の第１領域
（３）の表面層部分がＮ型に反転し、Ｎ型の抵抗領域（
４１（４）が導通して、抵抗として電流が流れるように
なる。The pair of resistance regions (41) corresponds to the voltage applied between the first region (3) and the first electrode layer (6).
(Between 41, a channel is formed that conducts between both resistance regions (41 (4). In other words, the first and second electrode layers +6) (When the voltage applied between 71 exceeds a certain threshold, the resistance The surface layer portion of the P-type first region (3) interposed between the regions (41 (41) is inverted to the N-type, and an N-type resistance region (
41(4) becomes conductive and current flows as a resistor.
第６図は前述した素子を利用したトランジスタスイッチ
ング回路図である。この図において、抵抗（Ｒ１１）と
（Ｒ１２） とのスイッチングを前述した抵抗領域（４
］ （４１に介在する第１領域（３）のＰ−型からＮ型
への反転によって行うものである。尚、抵抗（Ｒ１＋
）および（Ｒ１２）は抵抗領域（４）（４］に対応して
いる。すなわち、第１、第２の電極層（６１（７１に電
源電圧が印加され、その電源電圧値が所定電圧値（Ｖ″
ｒ）以上の電圧値になったとき、抵抗領域間に介在する
第１領域の表面層部分が反転することにより、抵抗（Ｒ
１１）と（Ｒ１２）とが導通し、トランジスタ（’ｒｚ
１）のベースにバイアスがかかつてトランジスタ（Ｔｒ
ｌｌ）がＯＮするものである。そして前記所定電圧値（
ＶＱはＰ−型の第１領域の表面濃度をコントロールする
ことによって自在に設定することができる。FIG. 6 is a transistor switching circuit diagram using the above-described elements. In this figure, switching between resistors (R11) and (R12) is shown in the resistance region (4) described above.
] (This is done by inverting the first region (3) interposed in 41 from P- type to N-type. Note that the resistance (R1+
) and (R12) correspond to the resistance region (4) (4]. In other words, a power supply voltage is applied to the first and second electrode layers (61 (71), and the power supply voltage value becomes a predetermined voltage value ( V''
r), the surface layer portion of the first region interposed between the resistance regions is reversed, and the resistance (R
11) and (R12) conduct, and the transistor ('rz
1) When a bias is applied to the base of the transistor (Tr
ll) is turned on. And the predetermined voltage value (
VQ can be freely set by controlling the surface concentration of the P-type first region.
第一４図は本発明をパワーアンプの過成圧保護回路に適
用した場合の回路図で、第６図で示した抵抗（Ｒ１１）
（Ｒ１２）およびトランジスタ（Ｔｒｌｌ）が第４図
の抵抗（’１１ＸＲ１２） オヨヒト５ ンシス９ （
’ｒｒ１１）に対応し、第１図の第１、第２の電極層（
６）（７）間に印加される電源電圧として、第４図のＶ
ｃｃ−ＧＮＤ間の電源電圧が印加される。つまり、Ｖｃ
ｃ−ＧＮＤ間電圧電圧ｆｉの第１領域（３）の反転重圧
を越えたとき、抵抗（Ｒ１１）と（Ｒ１２）とが導通し
、トランジスタ（１゛口１）のベースバイアスがかかり
トランジスタ（Ｔｒｌｌ）がＯＮ（、、ドライバートラ
ンジスタ（Ｔｒ１２）を０ＦＦＬ、出力トランジスタ（
ＴｒｌＢ）がＯＦＦする。Figure 14 is a circuit diagram when the present invention is applied to an overvoltage protection circuit of a power amplifier, and the resistor (R11) shown in Figure 6 is
(R12) and the transistor (Trll) are the resistance ('11XR12) shown in Figure 4.
'rr11), the first and second electrode layers (
As the power supply voltage applied between 6) and (7), V in FIG.
A power supply voltage between cc and GND is applied. In other words, Vc
When the c-GND voltage fi exceeds the inversion pressure in the first region (3), the resistors (R11) and (R12) become conductive, and the base bias of the transistor (1) is applied, causing the transistor (Trll ) is ON (,, driver transistor (Tr12) is 0FFL, output transistor (
TrlB) is turned off.
尚、ドライバートランジスタ（Ｔｒ １２ ）および出
カトランジスタ（Ｔｒ １５）などを分離領域で分離さ
れた他領域に形成することにより集積化が可能である。Note that integration is possible by forming the driver transistor (Tr 12 ), output transistor (Tr 15), etc. in other regions separated by an isolation region.
以上のように、本発明を用いたパワーアンプの過電圧保
護回路では、トランジスタ（Ｔ ｒ １１ ）と抵抗（
に１＋）（Ｒ１２）および抵抗（Ｒ２１）とで電比スイ
・リチング回路（２１）が構成でき、素子数を従来例に
比して大幅に削減することができる。As described above, in the power amplifier overvoltage protection circuit using the present invention, the transistor (T r 11 ) and the resistor (
1+) (R12) and the resistor (R21) can constitute an electric ratio switching circuit (21), and the number of elements can be significantly reduced compared to the conventional example.
ト）発明の詳細
な説明したように、本発明によれば、極めて少ない素子
数で威圧スイッチング回路を構成することができるので
、構造が１１１１単になり、清産性に優れるなどその工
業的価値は大きい。g) As described in detail, according to the present invention, it is possible to construct a high-pressure switching circuit with an extremely small number of elements, so the structure is simple and the industrial value is high, such as excellent productivity. big.
第１図は本発明の要部を示す１に面図、第２図は同断面
図、第３図は本発明を用いた電圧スイ・リチング回路を
示す回路図１、第４図は本発明をパワーアンプ過電圧保
護回路に用いた回路図である。第５図は従来の過電圧保
護回路を示す回路図である。
（２）・・・エピタキシャル層、（３）・・第１領域、
（４）・・抵２の電極層。
５４図
ど１
邪５図Fig. 1 is a plan view showing the main part of the present invention, Fig. 2 is a sectional view thereof, Fig. 3 is a circuit diagram 1 showing a voltage switching/litting circuit using the present invention, and Fig. 4 is a circuit diagram showing the voltage switching circuit using the present invention. FIG. 2 is a circuit diagram in which the above is used in a power amplifier overvoltage protection circuit. FIG. 5 is a circuit diagram showing a conventional overvoltage protection circuit. (2)...Epitaxial layer, (3)...First region,
(4)...Resistor 2 electrode layer. 54 Figure 1 Evil 5 Figure
Claims (1)
なくとも一対の他導電型の抵抗領域、この一対の抵抗領
域間に絶縁層を介して跨る電極層を具備し、前記第１領
域と電極層との間に印加される電圧値に応じて、前記一
対の抵抗領域間に両抵抗領域間を導通させるチャンネル
が形成されることを特徴とする半導体装置。(1) - A first region of a conductivity type, at least a pair of resistance regions of a different conductivity type formed in this region, and an electrode layer spanning between the pair of resistance regions with an insulating layer interposed therebetween; A semiconductor device characterized in that a channel is formed between the pair of resistance regions in accordance with a voltage value applied between the resistance regions and the electrode layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24121983A JPS60132356A (en) | 1983-12-20 | 1983-12-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24121983A JPS60132356A (en) | 1983-12-20 | 1983-12-20 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60132356A true JPS60132356A (en) | 1985-07-15 |
Family
ID=17070966
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24121983A Pending JPS60132356A (en) | 1983-12-20 | 1983-12-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60132356A (en) |
-
1983
- 1983-12-20 JP JP24121983A patent/JPS60132356A/en active Pending
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