JP2000031385A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow high-precision current output of a current adder digital/ analogue converter, by providing each gate and source of an MOS transistor 1 with a conductor wiring layer for connecting each drain of a plurality of MOS transistors provided in parallel to a ground potential. SOLUTION: When each gate of MOS transistors 104-108 is applied with an arbitrary constant bias, a current density 109 occurs at the upper part of the MOS transistor 104 and the lower part of the MOS transistor 108, provided vertically, while a current density 110 occurs at the upper and lower parts of the MOS transistors 105, 106, and 107 which generate the output current of a D/A converter. The MOS transistors 104 and 108 are so provided as to protect the MOS transistors 105, 106, and 107 and the current density 110 near the source of the MOS transistors 105, 106, and 107 are all even when a saturation current flows between a source and a drain, so a desired D/A transformer output current is provided as a source potential is constant.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in a digital / analog converter, and more particularly to a method for realizing a stable and accurate current output characteristic.

[0002]

2. Description of the Related Art FIG. 4 shows a layout pattern configuration diagram of a current addition type digital / analog converter which generates an output current by arranging a plurality of conventional general MOS transistors. Conventionally, basic MOS transistors, which will be described later with reference to the layout pattern configuration diagram of the basic MOS transistors in FIG.
06, the source potential of each MOS transistor is connected from the conductive wiring layer B402 to the source via the conductive wiring layer A [1] 409 via a hole and a source contact. MOS transistor 4
04, 405 and 406 are connected to the conductor wiring layer A
[2] Connected to drain 403 through drain contact. Each gate of the MOS transistors 404, 405, and 406 is connected to the conductor wiring layer A [3] 401 through a gate contact, and an arbitrary constant bias is applied. M
OS transistor 404 upper part and MOS transistor 40
6, a current density [1] 407 is generated below the MOS transistor 405, and a current density [2] 408 is generated above and below the MOS transistor 405 depending on the arrangement of the transistors. For example, as shown in FIG. 4, it is assumed that three stages are vertically stacked. Assuming that a current “1” flows to one source on one side of one MOS transistor, “1” is applied to the upper source of the first MOS transistor 404 and “1” is applied to the lower source.
Since the upper source of the second MOS transistor 405 is “1”, the lower source is “1”, the upper source of the third MOS transistor 406 is “1”, and the lower source is “1”. MOS transistor 404
In contrast to “1” near the upper source and near the lower source of the third MOS transistor 406, near the source above the second MOS transistor 405, the current “1” near the lower source of the first MOS transistor 404 and the second The current “1” near the source above the MOS transistor 405 is added to make the current “2”. Similarly, near the source below the second MOS transistor 405, the current “1” near the source above the third MOS transistor 406 and the current “1” near the source below the second MOS transistor 405 are added. The current is "2"
Since the current flows, a difference in current density depending on the location of the MOS transistor appears. A voltage drop occurs at a portion where the current density is high (a portion where the current “2” flows), and no voltage drop occurs at a portion where the current density is low (a portion where the current “1” flows) as compared with the portion where the current density is high. As described above, when the presence or absence of a voltage drop due to the location of the transistor occurs, the source potential of each transistor differs,
That is, since the transistors having different source potentials have different effective gate voltages, the source-drain currents flowing in the unit transistors are different.

[0003]

When a plurality of transistors are arranged in parallel, a desired digital-analog converter current output cannot be obtained because the output current capabilities of the unit transistors differ depending on the location of the transistors. are doing. The present invention is to arrange the current density near the source of all the transistors when arranging a plurality of transistors in parallel as described above, keep the source potential uniform, and make the saturation currents of the unit transistors all the same, It is an object of the present invention to realize a current output of a current addition type digital / analog converter with high accuracy.

[0004]

According to the semiconductor device of the present invention, two parallel conductive gate electrodes longer than the thin oxide film are provided on the thin oxide film, and the two conductive The gate electrode is electrically connected on a thick oxide film, the outside of the gate electrode is used as a source, and two drains corresponding to the two sources are commonly provided inside the gate electrode. -MO as drain (D)-source (S)
A plurality of S-structure transistors (hereinafter referred to as MOS transistors) 1 are arranged in parallel so that gate electrodes are parallel to each other, and each gate, each source, each drain and a gate contact for the purpose of connection with the conductor layer wiring. , A source contact, a drain contact, a conductor wiring layer 1 for applying a source potential so as to cover each source,
A conductor wiring layer for applying a constant bias to the gate electrode of the S transistor, a conductor wiring layer for extracting output current from the drains of the plurality of MOS transistors, and a MOS transistor having the same structure as the plurality of MOS transistors; In a semiconductor device in which a plurality of MOS transistors 1 are arranged in parallel, both gates and sources of the MOS transistor 2 are connected to the plurality of MOS transistors 1 arranged in parallel.
The present invention is characterized in that a conductor wiring layer 4 for applying the same potential as each gate and each source of the S transistor 1 and connecting each drain of the MOS transistor 2 to the ground potential is provided.

[0005]

[Function] In this way, digital
In the analog converter, the saturation current of the unit transistor, which is the basis of the output current of the digital-analog converter, is extremely important. A plurality of parallel-arranged transistors 1 for generating current to obtain the output current of the digital-to-analog converter
A transistor 2 having the same structure as that of the transistor 1 is arranged at both ends of the transistor 1, and the same current as that of the transistor 1 is applied to the transistor 2 without using the transistor 2 as an output current of a digital / analog converter. Since the current density near the source of each of the plurality of transistors becomes equal for all the transistors, a desired current can be extracted from the transistor 1 and a digital-to-analog converter output with high accuracy can be obtained.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the operation of the present invention will be described in detail based on embodiments.

FIG. 1 is a layout pattern diagram in an embodiment of the present invention. MOS transistors 104, 105, 1
Reference numerals 06, 107 and 108 arrange the basic type MOS transistors described in FIG. 2 in parallel, and the source potential of each MOS transistor is set to the conductor wiring layer B10.
2 through a hole through the conductor wiring layer A [1] 112 and connected by a source contact. The drains of the MOS transistors 105, 106, and 107 are connected to the conductor wiring layer A [2] 103 through drain contacts. The drains of the MOS transistors 104 and 108 are connected to the conductor wiring layer A [4] 111 through a drain contact to the ground potential. MOS transistor 10
The gates 4, 105, 106, 107 and 108 are connected to the conductor wiring layer A [3] 101 through gate contacts, and an arbitrary constant bias is applied. A current density [1] 109 is generated above and below the MOS transistor 104 arranged above and below the MOS transistor 108, and the current density [1] 109 is formed above and below the MOS transistors 105, 106, and 107 that generate the output current of the digital-to-analog converter. 1] 110 occurs. Although the current density [1] 109 and the current density [2] 110 are different from each other,
The transistors 104 and 108 are MOS transistors 10
5, 106, and 107, and the current density [2] 110 near the sources of the MOS transistors 105, 106, and 107 due to the flow of the saturation current between the source and the drain. Since all are uniform and the source potential becomes uniform, it is possible to obtain a desired digital-to-analog converter output current.

FIG. 2 is a layout pattern diagram of a basic type MOS transistor used in the conventional example and the embodiment of the present invention. A source 201 is provided on both outer sides, a plurality of source contacts 204 for connection between the source and the conductor wiring layer A [1] 208, and a common drain 203 for the source is provided at the center, and the drain and the conductor are provided. Wiring layer A [2] 2
Drain contacts 2 for the purpose of connection to
05, comprising two conductive gates 202 whose long sides are longer than the source and the drain and are parallel and electrically connected at both ends, for the purpose of connecting the gates to the conductor wiring layer A [3] 210 A plurality of gate contacts 206, a plurality of holes 207 for connection between the conductor wiring layer A [1] 208 and the conductor wiring layer B, and a conductor wiring layer for applying a source potential to the source. A [1] 208 and a conductor wiring layer A [2] 209 for extracting current from the drain
And a conductor wiring layer A for applying a constant bias to the gate.
[3] A basic type MOS transistor provided with 210.

FIG. 3 is based on the embodiment of the invention of FIG.
FIG. 3 is a detailed diagram of a layout pattern configuration. The portion described with reference to FIG. A plurality of output current blocks 301 are arranged in parallel in the horizontal direction, and a source potential is applied from the left side in FIG. Since the current density flows in the same manner as in the present invention shown in FIG. 1, the current density [1] 303 has a high current density (the portion where the current “2” flows) and the current density [2] 3
02 has a low current density (portion where the current “1” flows).

[0010]

As described above, according to the semiconductor device of the present invention, a MOS transistor having the same structure is arranged at both ends of a plurality of MOS transistors for obtaining a current output of a digital-to-analog converter, and a current is supplied to the MOS transistor. Are equalized, the saturation current between the source and drain of the MOS transistor becomes equal, and a desired digital-to-analog converter current output can be obtained with high accuracy.

[Brief description of the drawings]

FIG. 1 is a layout pattern configuration diagram of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a layout pattern configuration diagram of a basic type MOS transistor in a conventional example and an example of the present invention.

FIG. 3 is a detailed diagram of a layout pattern configuration of the semiconductor device according to the embodiment of the present invention.

FIG. 4 is a layout pattern configuration diagram of a conventional semiconductor device.

[Explanation of symbols]

 101 conductor wiring layer A [3] 102 conductor wiring layer B 103 conductor wiring layer A [2] 104 MOS transistor 105 MOS transistor 106 MOS transistor 107 ..MOS transistor 108 ... MOS transistor 109 ... current density [1] 110 ... current density [2] 111 ... conductor wiring layer A [4] 112 ... conductor wiring layer A [1] 201: Source of MOS transistor 202: Gate of MOS transistor 203: Drain of MOS transistor 204: Source contact of MOS transistor 205: Drain contact of MOS transistor 206: Gate of MOS transistor Contact 207: Hole 208: Conductor wiring layer A [1 209 ... conductor wiring layer A [2] 210 ... conductor wiring layer A [3] 301 ... output current block 302 ... current density [1] 303 ... current density [2] 401 ..Conductor wiring layer A [3] 402 ... conductor wiring layer B 403 ... conductor wiring layer A [2] 404 ... MOS transistor 405 ... MOS transistor 406 ... MOS transistor 407 ... Current density [1] 408 ... Current density [2] 409 ... Conductor wiring layer A [1]

Claims (1)

[Claims] 1. A thin oxide film having two parallel conductive gate electrodes longer than the thin oxide film, and connecting the two conductive gate electrodes on an electrically thick oxide film. , Both sides of the gate electrode as sources, and 2 inside the gate electrode.
One common drain corresponding to the two sources,
M to be source (S) -drain (D) -source (S)
A plurality of transistors 1 (hereinafter referred to as MOS transistors) having an OS structure are arranged in parallel so that gate electrodes are parallel to each other, and each gate, each source, each drain and a gate contact for the purpose of connection with a conductor layer wiring are provided. , A source contact, a drain contact, a conductor wiring layer 1 for applying a source potential so as to cover each source,
A conductor wiring layer for applying a constant bias to the gate electrode of the S transistor, a conductor wiring layer for extracting output current from the drains of the plurality of MOS transistors, and a MOS transistor having the same structure as the plurality of MOS transistors; In a semiconductor device in which a plurality of MOS transistors 1 are arranged in parallel, both gates and sources of the MOS transistor 2 are connected to the plurality of MOS transistors 1 arranged in parallel.
A semiconductor device comprising: a conductor wiring layer that applies the same potential as each gate and each source of an S transistor and connects each drain of the MOS transistor to a ground potential.