JP4526338B2 - D / A conversion circuit, organic EL drive circuit, and organic EL display device - Google Patents

Description

  The present invention relates to a D / A conversion circuit, an organic EL drive circuit, and an organic EL display device. Specifically, the display data is D / A converted corresponding to the column pin of the organic EL panel, and the drive current in the column direction or the drive current The present invention relates to an improvement in an organic EL driving circuit and an organic EL display device capable of suppressing unevenness in luminance of a display screen and variation in luminance due to variation in conversion characteristics of a D / A conversion circuit in a current driving circuit that generates an original current. .

In an organic EL display panel of an organic EL display device mounted on a mobile phone, PHS, DVD player, PDA (mobile terminal device), etc., the number of column lines is 396 (132 × 3) terminal pins (column pins), row Lines having 162 terminal pins have been proposed, and column line and row line terminal pins tend to increase further.
As a drive circuit for such an organic EL display panel, Japanese Patent Application Laid-Open No. 2003-234655 (Patent Document 1) and Japanese Patent Application Laid-Open No. 2003-308043 (Patent Document 2) of this applicant provided with a D / A conversion circuit corresponding to a column pin. ) In the latter case, the D / A conversion circuit provided for the column pin receives the display data and the reference current, and the display data is D / A converted for the column pin of the organic EL panel according to the reference current to drive the current in the column direction or A current that is a source of the drive current is generated. In this case, in particular, in a passive matrix organic EL panel, a peak current is generated in order to initially charge and drive an organic EL element having the characteristic of a capacitive load.
JP 2003-234655 A JP 2003-308043 A

FIG. 6 is an example of a D / A conversion circuit (Japanese Patent Laid-Open No. 2003-308043) mainly composed of a MOSFET transistor (MOS transistor) provided corresponding to a column pin of a drive circuit of an organic EL display panel.
Reference numeral 11 denotes a D / A conversion circuit (D / A) of the current drive circuit. D / A 11 is a so-called current switching D / A, and is configured by a current mirror circuit. The D / A 11 receives the reference current Ip from the constant current source 12 to the input side transistor TNa via the input terminal 11a, receives display data D0 to Dn-1 from the register 16, and doubles the reference current Ip to display data. Output circuit. This D / A 11 is composed of an N-channel input side transistor TNa and a current mirror circuit of N-channel output side transistors TNb to TNn-1, and in parallel with the input side transistor TNa in order to generate a peak current. An N-channel MOS transistor TNp is provided as an input side transistor.

The gate and drain of the transistor TNp are connected to the input terminal 11a. The sources of the transistors TNa and TNp are grounded via the resistors Ra and RPa and the switch circuits SWa and SWPa, respectively. The switch circuits SWa and SWPa are ON / OFF controlled by pulse signals P and CONT from the control circuit 15. When the switch circuit SWa is turned on and the switch circuit SWPa is turned off, the reference current Ip is received and the D / A 11 outputs the peak current. The switch circuits SWa and SWPa are both turned ON, and the D / A 11 outputs a steady current corresponding to the reference current.
The resistors Rb to Rn-1 provided downstream of the output side transistors TNb to TNn-1 are resistors that balance the operating current of the current mirror circuit, and N provided downstream of the resistors Ra to Rn-1. The channel transistors Trb to Trn-1 are switching transistors that are turned on / off by display data D0 to Dn-1.

Here, the drains of the output side transistors TNb to TNn-1 are connected to the output terminal 11b of the D / A 11, and each transistor has, for example, × 1, for the gate width (channel width) of the transistor TNa. It has a gate width (channel width) corresponding to the weight of each digit of a multiple of × 2, × 4,... × n. The gate width (channel width) corresponding to the weight of each digit is usually formed by connecting a plurality of unit transistors formed as transistor cells in parallel.
An output stage current source 13 includes a drive level shift circuit 13a and an output stage current mirror circuit 13b.
The drive level shift circuit 13a is a circuit for transmitting the output current of the D / A 11 to the output stage current mirror circuit 13b, and includes an N-channel MOS transistor TNv. The gate of the transistor TNv is connected to the bias line Vb, the source side is connected to the output terminal 11b, and the drain is connected to the input terminal 13c of the output stage current mirror circuit 13b.
The output stage current mirror circuit 13b has P channel MOS transistors TPu and TPw and P channel MOS transistors TPx and TPy constituting an output stage current mirror circuit. The transistor TPy outputs a drive current from its drain to the organic EL element 4 via the output pin 9.

Such a current driving circuit performs D / A conversion in accordance with the reference current Ip, and generates a driving current in the column direction or a current that is a source of this driving current corresponding to the column pin. In addition, the D / A is configured by a current mirror circuit using a large number of transistor cells. For this reason, variations in D / A conversion characteristics result in variations in output current between column pins, which appear as variations in luminance of the display screen and variations in luminance.
Since this luminance unevenness and luminance variation cannot be absorbed even if the current value of the reference current is adjusted, it is necessary to provide an adjustment circuit for adjusting the conversion current value in the D / A conversion circuit. However, since this adjustment circuit must be provided for column pins, the circuit scale increases as the number of elements in the adjustment circuit increases, making it difficult to make the current drive circuit as a single chip as an IC.
An object of the present invention is to solve such a problem of the prior art, in which a current mirror circuit is configured by using a large number of transistor cells, and a large number of D / As having the current mirror circuit as elements are provided. An object of the present invention is to provide a D / A conversion circuit capable of reducing variations in output current between D / A due to variations in D / A conversion characteristics.
Another object of the present invention is to provide a display screen with non-uniformity in brightness and variations in brightness in an organic EL driving circuit and an organic EL display device using a D / A including a current mirror circuit using a large number of transistor cells as described above. It is an object to provide an organic EL driving circuit or an organic EL display device capable of suppressing the above.

In order to achieve the above object, the D / A conversion circuit, organic EL drive circuit or organic EL display device of the present invention is characterized in that in the D / A conversion circuit having a current mirror circuit as an element, the current mirror circuit is A MOS transistor or gate region that includes a plurality of transistor cells, and each transistor cell (unit transistor) is formed in a square shape close to a square that has a bent stripe shape when viewed from the plane. as viewed from the plane direction of the current flowing to, those having an MOS transistor striped channel is formed in the form of a square near the formed and squares are folded.

By the way, in the current mirror circuit using MOS transistors, the variation ΔI of the output side current value with respect to the predetermined input drive current value I can be expressed by the following equation. ΔI = I−2ΔVth / (VGS−Vth) (1)
However, VGS is a gate-source voltage, Vth is a threshold voltage, and ΔVth is a difference voltage with respect to a threshold voltage which is a design standard of the transistor.
(VGS−Vth) in the above equation (1) can be expressed by the following equation.
VGS−Vth = √ {(2 / μnCox) · (L / W) · ID} …… (2)
Where μn is the electron mobility, Cox is the capacitance per unit area of the gate oxide film, ID is the drain current, L is the channel length, and W is the channel width.
By the way, the number of drive pins tends to increase due to a demand for higher resolution. As a result, the power consumption increases, so that further reduction is required. Therefore, the operating power supply voltage of the D / A conversion circuit needs to be suppressed to about 3 V or less, for example. Therefore, VGS cannot be increased.

Therefore, when ID is considered to be a constant value, if (VGS−Vth) is increased, the variation ΔI is reduced. In order to increase (VGS−Vth), it is necessary to increase L / W. In other words, the reciprocal W / L may be reduced.
Therefore, the present invention relates to a MOS transistor having a stripe-like MOS transistor whose gate region is bent when viewed from the plane or a transistor having a MOS transistor having a stripe-shaped channel whose direction of current flowing through the gate region is folded when viewed from the plane. A large number of cells are formed, and a D / A of a current mirror circuit type is configured using these transistor cells. As a result, a current mirror circuit can be configured by transistors having a long channel length L. Moreover, W / L can be made small by this.
Further, by bending the channel, the shape of the transistor cell (unit transistor) is not a rectangular shape, but can be a square shape close to a square shape. This shortens the distance between the transistor cells and improves the integration efficiency. In addition, the distance between the transistors constituting the current mirror circuit can thereby be laid out short. As a result, it is possible to improve the pair property from the viewpoint of the characteristics of each transistor constituting the current mirror circuit, and to improve the current accuracy of D / A conversion.
For this reason, the present invention can reduce variations in output current between D / A due to variations in D / A conversion characteristics in a circuit provided with a large number of D / As using a current mirror circuit. Furthermore, in the organic EL drive circuit and the organic EL display device in which the D / A of the present invention is provided corresponding to the terminal pin of the organic EL panel, variation in the conversion current of the current mirror circuit is suppressed, and the conversion characteristics of the D / A conversion circuit are reduced. It is possible to suppress the luminance unevenness of the display screen due to the variation and the luminance variation.

FIG. 1 is an explanatory diagram of a layout of a transistor cell constituting a D / A of a current driving circuit and a current mirror circuit of an output stage current source according to an embodiment to which the organic EL driving circuit of the present invention is applied. ) Is an explanatory plan view of a semiconductor structure of a transistor cell in a current mirror type D / A, FIG. 2B is an AA cross-sectional explanatory view, and FIG. 3A is a current mirror type D / A. FIG. 3B is a cross-sectional explanatory view taken along the line BB of FIG. 4, and FIG. 4 is a plan view of still another semiconductor structure of the transistor cell in the current mirror type D / A. FIG. 5A is an explanatory diagram of a current mirror type D / A using the transistor cell, and FIG. 5B is an equivalent circuit of the transistor cell.
In FIG. 1, reference numeral 10 denotes a layout of a transistor cell (transistor unit circuit) 1 constituting a current mirror. This layout 10 corresponds to a region where a D / A provided for a column pin and an output stage current source are formed in a column driver IC of an organic EL drive circuit.
In order to form a current mirror of the D / A 11 and the output stage current source 13 shown in FIG. 6, the transistor cell 1 having the arrangement shown in the layout 10 as shown in FIG. 1 is used. Therefore, the D / A 11 in FIG. 6 is a D / A 5 having a circuit configuration that does not use the resistors Ra to Rn-1 as shown in FIG. 5A, and the transistor cell 1 is shown in FIG. Two transistors, each including a series circuit 20 of an N-channel MOS transistor TN for current output and an N-channel MOS transistor Tr serving as a switch circuit, are configured as a unit. Further, for D / A5, the transistor TN of the transistor cell 1 is a serpentine transistor 21 having a striped channel that is folded back when viewed from the plane as shown in FIGS.

The D / A 5 shown in FIG. 5A uses the transistor cell 1 as two input side transistors and a number of output side transistors of a current mirror circuit. In the transistor Tr of the output side transistor cell 1, the gate G2 receives one bit of the display data, and is turned on / off according to “1” and “0”. The drains D of the two input side transistor cells 1 are both connected to the input terminal 5a of the D / A 5, and the drains D of the many output side transistor cells 1 are connected to the output terminal 5b of the D / A 5. . An analog conversion current for the display data is generated at the output terminal 5b. The gates G1 of the transistors TN are connected in common and further connected to the input terminal 5a. The source S of each transistor cell 1 (the source S of the transistor Tr) is connected to the ground GND.
As shown in the layout 10 of FIG. 1, here, the transistor cell 1 has a direction (vertical direction = column direction) orthogonal to the pad arrangement direction (corresponding to the row direction) connected to the column pins of the organic EL drive circuit. Are arranged vertically and horizontally in a rectangular transistor array block 3a in the longitudinal direction.

The total number of transistor cells 1 in the transistor array block 3a is 252 and 42 × 6. The transistor array block 3a is repeatedly formed at every three pad pitches in the pad array direction (lateral direction = row direction) with a predetermined gap therebetween. Each row of two transistor cells 1 in the row direction corresponds to each pad.
In each transistor array block 3a in the unit of 3 × pad pitch width, the transistor cell 1 constituting the current mirror is selected, and the R, G, B D / A current mirror circuits are formed.
In this embodiment, the D / A5 circuit shown in FIG. 5A is used instead of the D / A11 circuit as corresponding to D / A11 in FIG. In the layout 10 of FIG. 1, D / A 5 is formed by D / A 5 Bi corresponding to R, G, and B, and each transistor cell 1 in each region of D / A 5 Ri and D / A 5 Gi. The D / A5 formed by the D / A5Bi and the D / A5Ri and D / A5Gi transistor cells 1, respectively, eliminates the resistors Ra and RPa of the D / A11 of FIG. 6 as shown in FIG. Thus, the upstream side input side transistors TNa and TNp and the switch circuits SWa and SWPa are directly connected. Further, the resistors Ra to Rn-1 are eliminated, and the upstream output transistors TNa to TNn-1 are directly connected to the transistors Tra to Trn-1 which are downstream switch circuits.

As a result, the transistor configuration of each circuit on the input side and output side constituting the current mirror circuit is such that the current output N-channel MOS transistor TN and the switch circuit are connected to the source and drain as shown in FIG. A series circuit of N-channel MOS transistors Tr can be used as a unit circuit.
Each current source 4Bi, 4Ri, 4Gi is provided as a region of the current mirror circuit constituting the output stage current source 13 on the pad 2 side of the transistor array block 3a. The B (blue) transistor cell region is allocated as a current source 4Bi of 2 × 6 regions as shown in the figure. A current mirror circuit is constituted by the upper wiring layer by ten transistor cells in this region. The output of this current mirror circuit is connected to the pad 2Bi via the upper wiring line 9b. In the current source 4Bi, ten transistor cells are used, and the remaining two are reserved or dummy transistor cells.

Assuming that the pad 2Bi side is the front, the transistor cell region constituting the current source of the R (red) current mirror is allocated as a 2 × 6 region as shown in the figure. This is the current source 4Ri. Similarly, a current mirror circuit is formed by 10 transistor cells each, and the output of the current mirror circuit is connected to the pad 2Ri via the upper wiring line 9r.
Further, the transistor cell region constituting the current source of the G (green) current mirror is allocated as 2 × 6 regions as shown in the figure. This is the current source 4Gi. Similarly, a current mirror circuit is constituted by 10 transistor cells each, and the output of the current mirror circuit is connected to the pad 2Gi through the upper wiring line 9g.
Behind these are three 12 × 6 regions that form a current mirror D / A in a current mirror configuration, and these regions similarly correspond to B, R, and G in this order. / A5Bi, D / A5Ri, and D / A5Gi. Each D / A is composed of 70 transistor cells, and two transistor cells are reserved or dummy transistors.

The number of the above-mentioned transistor cells (unit transistors) 252 is such that a transistor or transistor cell that is substantially twice or n times the area of the unit transistor is partially included in the current mirror circuit. When one is formed, it is a numerical value converted as two or n. On the other hand, when two or n transistors / transistor cells, each of which is an integral number of unit transistors, are formed, the current mirror circuit is configured as a value converted to one as a whole. It is.
The output terminal of the D / A 5 Bi is connected to the input terminal of the current source 4 Bi through an upper wiring line 8 b. The output terminals of D / A5Ri and D / A5Gi are connected to the corresponding input terminals of the current source via the current source 4Ri and the current source 4Gi and the wiring lines 8r and 8g, respectively.
Such a transistor array block 3a is laid out for each of the three pads B, R, and G.
Note that the blocks of the B, R, and G current sources 4Bi, 4Ri, and 4Gi in FIG. 1 are arranged in the horizontal direction corresponding to the pads 2Bi, 2Ri, and 2Gi, and D / A5Bi, 5Ri , 5Gi may be arranged in the order of B, R, G in the vertical direction.

Meanwhile, the output stage current source 13 in FIG. 6 is a P-channel MOS transistor, and D / A 11 is an N-channel MOS transistor. In the connection by the wiring lines, D / A5Bi, D / A5Ri, and D / A5Gi are N-channel MOS transistor transistor cell 1, and current source 4Bi, current source 4Ri, and current source 4Gi are P-channel MOS transistor transistors. This is the case of cell 1. Therefore, for the current source 4Bi, the current source 4Ri, and the current source 4Gi, although the equivalent circuit of FIG. 5B is not shown, the N channel is changed to a P channel MOS transistor.
Here, since the number of transistor cells in each current source block is much smaller than the number of transistor cells in the D / A block, the transistor cell 1 has the same transistor cell apart from the P-channel and N-channel configurations. However, when the current source 4Bi, the current source 4Ri, and the current source 4Gi are D / A5Bi and D / A5Ri and D / A5Gi are, for example, the transistor cell 1 of the same N-channel MOS transistor, D / A5Bi, D / A5Ri, D / A5Gi output terminals, current source 4Bi, current source 4Ri, and current source 4Gi input terminals via a current mirror circuit of a P-channel MOS transistor formed in another region Will be connected to each other. In this case, the current source 4Bi, the current source 4Ri, and the current source 4Gi formed of N-channel MOS transistors are current sink type unlike the output stage current source 13 of FIG.
Further, the transistor constituting the current source 4Bi, the current source 4Ri, and the current source 4Gi does not need a switch operation transistor. In the case of the transistor cell 1 of the equivalent circuit of FIG. 5B, the current output MOS transistor TN in the series circuit 20 is used. Therefore, the N-channel MOS transistor Tr serving as a switch circuit is used as the transistor cell 1 which is set to the ON state and substantially includes one current output transistor.

2 and 3 are explanatory diagrams of the semiconductor structure of the transistor cell 1 formed in each region of D / A5Bi, 5Ri, and 5Gi forming the circuit of D / A5 shown in FIG. 5A in such a case. is there.
The transistor cell 1 of D / A5Bi, 5Ri, and 5Gi is formed of a series circuit 20 of a transistor TN and a transistor Tr serving as a switch circuit, as shown in FIG. 5B. D / A5Bi, 5Ri, and 5Gi are circuits in which the resistance is deleted from D / A11 in FIG. Therefore, the series circuit 20 is a unit circuit on both the input side and the output side of the current mirror circuit.
Specifically, on the input transistor side of the current mirror circuit, the drain D of the transistor TN of the series circuit 20 is connected to the input terminal 11a receiving the reference current, and the source S of the transistor Tr is connected to the ground GND. As shown in the transistor cell 1 on the leftmost side of FIG. 5A, when the gate of the transistor Tr is set to a predetermined bias voltage Vb, this is not a switch circuit but a resistor. In an actual circuit, the transistor Tr of the transistor cell 1 on the leftmost side of FIG. 5A or the switch circuit SWa of FIG. 6 is replaced with a resistor.
As described above, in the output side transistor of the current mirror circuit, the drain D of the transistor TN is connected to the output terminal 5a, and the source S of the transistor Tr is connected to the ground GND. A plurality of transistor cells 1 of the series circuit 20 are connected in parallel according to the weighting of each digit of the output side transistor.

FIG. 2A is a plan view of the D / A 5 Bi, 5 Ri, 5 Gi transistor cell 1 in which the upstream transistor TN is a serpentine transistor. The transistor cell 1 constituting the current source 4Bi, the current source 4Ri, and the current source 4Gi does not necessarily have to be a serpentine type transistor.
Reference numeral 21 denotes a region where the transistor TN is formed, and reference numeral 22 denotes a region where the transistor Tr is formed. 22 s is a source region of the transistor Tr, and 23 is a source contact region. 22g is the gate region of the transistor Tr, and 24 is its gate contact region. Reference numeral 22d denotes a drain region of the transistor Tr and a source region of the transistor TN.
21g is a gate region of the transistor TN, and 25 is its gate contact region. Reference numeral 26 denotes a channel formation region for forming a channel below the gate electrode of the gate region 21g. When a predetermined voltage is applied to the gate, the gate region is a stripe bent when viewed from the plane. A shaped channel (inversion layer) is formed immediately below the channel formation region 26. Around this region, a LOCOS (SiO ₂ ) region 26L is provided to separate the stripe channels. 21d is a drain region of the transistor TN, and 27 is its drain contact region.
Here, as shown in the AA cross-sectional view of FIG. 2B, the channel formation region 26 is alternately arranged with the LOCOS region 26 </ b> L, and the channel formed in the gate region is limited in the range of the channel formation region 26. Is done. As a result, it is possible to form a twisted channel in the gate region as viewed from above. As a result, the channel formed in the gate region has a shape in which the direction of current flow is folded. This also makes it possible to reduce the W / L of the transistor TN.

FIG. 3A shows the shape of another channel formation region, in which a plurality of channel formation regions 26 are provided in parallel with one U-shaped bent channel formation region 261 as a unit, and linear struts are formed on both sides. A live 262 is provided, and the channel forming region 26 in FIG. 2A is divided into a plurality of portions.
Outside the gate region 21g, channel contact regions 263 for extracting channel current are provided at the ends of the bent portions 261 and 262, respectively. The ends are connected to each other by a wiring line 265 via a contact region 264 in the upper contact region wiring layer to form one bent channel.
FIG. 3B is an explanatory view of the BB cross section. The channel contact region 263 is formed as an N ⁺ island region immediately below the ends of the bent portions 261 and 262, respectively.
The AA cross section is the same as FIG.

  FIG. 4 shows another channel formation region, in which a plurality of stripe channel formation regions 266 are simply arranged in parallel, and channel contact regions 267 and 268 provided in the vertical direction of the drawing in the channel formation region 266 are provided. Are connected by wiring lines 269, respectively. As a result, the channel formed in the gate region has a shape in which the direction in which the current flows is folded as viewed from the plane. In addition, the cross-sectional explanatory drawing about this is omitted.

As described above, the series circuit 20 in FIG. 5B may be a series circuit in which the transistor TN side is downstream and the transistor Tr side is upstream. Furthermore, only the transistor TN side constituting the current mirror circuit may be provided as the transistor cell 1 in each of the D / A 5 Bi, 5 Ri, and 5 Gi, and the switching transistor Tr may be provided in another region. Therefore, the transistor cell 1 may be only one MOS transistor for current output of the serpentine type MOS transistor cell.
Further, the MOS transistor TN for current output of the transistor cell 1 of the embodiment is configured such that the gate region is substantially rectangular and the direction of the current flowing through the channel formed in the gate region is folded. ing. However, a similar channel can be formed even if the gate region itself of the MOS transistor TN is bent in a plan view.

In the embodiment, the serpentine type MOS transistor cell is used for the D / A current mirror circuit, but the unit transistor of the current mirror circuit of the output stage current source may also be constituted by the serpentine type MOS transistor cell. Of course.
Further, in the layout of FIG. 1 of the embodiment, each area constituting the current mirror circuit of the D / A and the output stage current source is constituted by the transistor cell 1 having two transistors as a unit. However, the transistor cell 1 may be configured in units of two or more transistors. Further, the number of transistor cells of the output stage current source is smaller than that of D / A, and the unit transistor of the current mirror circuit of the output stage current source does not require a switch circuit, so that there is no N channel MOS transistor Tr. A transistor cell having only one MOS transistor TN for output may be used.
Furthermore, although the transistor cell 1 of the embodiment is composed of an N channel MOS transistor, it may be composed of a P channel MOS transistor.

FIG. 1 is an explanatory diagram of a layout of a transistor cell constituting a D / A of a current driving circuit and a current mirror circuit of an output stage current source of an embodiment to which an organic EL driving circuit of the present invention is applied. 2A is an explanatory plan view of a semiconductor structure of a transistor cell in a current mirror type D / A, and FIG. 2B is an AA cross-sectional view thereof. FIG. 3A is an explanatory plan view of another semiconductor structure of a transistor cell in a current mirror type D / A, and FIG. FIG. 4 is an explanatory plan view of still another semiconductor structure of a transistor cell in a current mirror type D / A. FIG. 5A is an explanatory diagram of a current mirror type D / A using the transistor cell, and FIG. 5B is an equivalent circuit of the transistor cell. FIG. 6 is an explanatory diagram of an example of a D / A provided corresponding to the column pin of the drive circuit of the organic EL display panel.

Explanation of symbols

1 ... transistor cell (unit transistor), 2 ... pad,
3, 3a ... Unit transistor array block,
4Bi, 4Ri, 4Gi ... current drive circuit,
5Bi, 5Ri, 5Gi ... D / A,
6bi ... output terminal, 7bi ... input terminal,
8b, 8r, 8g, 9b, 9r, 9g ... wiring lines,
10 ...
21 ... A region where the transistor TN is formed,
21g: gate region of transistor TN,
21d ... Drain region of the transistor TN,
22 ... A region where the transistor Tr is formed,
22g: the gate region of the transistor Tr,
22s ... the source region of the transistor Tr,
22d ... Drain region of the transistor Tr,
23 ... Source contact region,
24, 25 ... gate contact region,
26: Channel forming groove,
26L ... LOCOS area,
27: Drain contact region.

Claims (9)

In a D / A conversion circuit having a current mirror circuit as an element,
The current mirror circuit includes a plurality of transistor cells, and each of the transistor cells is a MOS formed in a quadrangular shape close to a square in which a gate region is bent in a stripe shape when viewed from a plane. A D / A conversion circuit having a MOS transistor formed in a square shape close to a square and having a stripe-shaped channel that is folded when the direction of a current flowing through the transistor or the gate region is viewed from a plane.   2. The D / A converter circuit according to claim 1, wherein the transistor cell comprises a series circuit including the MOS transistor and a switch-operation transistor connected in series to the MOS transistor.   3. The D / A conversion circuit according to claim 2, wherein the MOS transistor is a serpentine type MOS transistor, and the transistor for the switching operation is also a MOS transistor, and the MOS transistors are formed in a rectangular region as viewed from the plane. .   Each of the transistor cells is assigned as an input side transistor and a plurality of output side transistors of the current mirror circuit, and each of the switch operation transistors of the plurality of output side transistor cells has one bit of display data at a gate. 4. The D / A conversion circuit according to claim 3, wherein the D / A conversion circuit generates an analog current obtained by D / A converting the display data as a total output of the plurality of output side transistor cells.   5. The D / A conversion circuit according to claim 4, wherein the analog current is generated as a current sent to a terminal pin of an organic EL panel or a current serving as a basis thereof.   6. The D / A conversion circuit according to claim 5, wherein the transistor cell is a cell selected from a plurality of transistor cells arranged vertically and horizontally in a rectangular transistor arrangement block as viewed from above.   An organic EL drive circuit comprising the D / A conversion circuit according to claim 1. 7. The D / A converter circuit according to claim 6, wherein the rectangular transistor array block is substantially 3n times (n is a positive integer) a pad pitch in an array direction of pads connected to terminal pins of the organic EL panel. A plurality of transistor cells arranged in a direction perpendicular to the pad arrangement direction. The transistor cells are selected and integrated into an IC so that the R / G / B D / A conversion circuits are sequentially formed in a direction perpendicular to the pad arrangement direction in the transistor arrangement block. An organic EL driving circuit having the D / A conversion circuit according to Item 6.   9. An organic EL display device comprising: the organic EL driving circuit according to claim 7; and an organic EL panel receiving a driving current from the organic EL driving circuit at a terminal pin.

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