JP6985875B2 - Digital-to-analog conversion circuit - Google Patents

Description

The present invention relates to a semiconductor integrated circuit, a digital-analog conversion circuit, and a method for driving the semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit including a MOS field effect transistor, a digital-analog conversion circuit, and a method for driving the semiconductor integrated circuit.

In recent years, with the progress of high integration due to the miniaturization of semiconductor integrated circuits by deep submicron technology, the increase in leakage current due to the miniaturization of MOS field effect transistors constituting the semiconductor integrated circuits is becoming a problem. The leakage current can be reduced, for example, by increasing the thickness of the gate insulating film of the MOS field effect transistor and the length of the gate length. However, the operating speed of the MOS field effect transistor decreases as the thickness of the gate insulating film and the length of the gate length increase. Therefore, in semiconductor integrated circuits for applications that require high processing speed, the problem is how to reduce the leakage current while achieving high processing speed.

As an example of a technology aimed at reducing leakage current while achieving high-speed processing speed in a semiconductor integrated circuit, a main circuit composed of MOS field-effect transistors and an enable signal being turned off during standby are used. A MOS field-effect transistor for cutting the leak current that cuts off the leak current path of the main circuit is provided, and the MOS field-effect transistor for cutting the leak current is a transistor circuit having a longer channel length than the MOS field-effect transistor that constitutes the main circuit. Is known (see, for example, Patent Document 1).

Further, as an example of other technologies, a logic circuit composed of a MOS field-effect transistor and a MOS field-effect transistor for cutting a leak current that cuts off the leak current path of the logic circuit by turning off the enable signal during standby are used. As the MOS field-effect transistor for cutting off the leak current, a semiconductor integrated circuit having a smaller leakage current than the MOS field-effect transistor constituting the logic circuit is known (see, for example, Patent Document 2).

According to these technologies, the enable signal is turned on only when the logic circuit is operated to conduct the MOS field effect transistor for leak current cutoff, and the enable signal is turned off when the logic circuit is put on standby for leak current cutoff. By making the MOS field effect transistor non-conducting, it is possible to reduce wasteful power consumption due to leakage current during standby of the logic circuit.

Japanese Unexamined Patent Publication No. 2002-164775 Japanese Unexamined Patent Publication No. 2008-08548

As described above, the leakage current of the MOS field effect transistor inevitably increases as it is miniaturized in order to operate at high speed. In other words, it can be said that the leakage current of the MOS field effect transistor has a trade-off relationship with the increase in the operating speed. Therefore, if the gate insulating film of the MOS field effect transistor is thinned and the gate length is shortened in order to realize a logic circuit that operates at high speed, the leakage current increases accordingly, and as a result, the ON / OFF current ratio of the logic circuit increases. It is lowered and malfunctions are likely to occur. In the above-mentioned conventional technique, since the reduction of the leakage current is regarded as the standby time of the logic circuit, the ON / OFF current ratio is lowered by the leakage current during the operation of the logic circuit, and a malfunction occurs. The problem of ease will arise.

The present invention has been made in view of such a situation, and an object of the present invention is to provide a semiconductor integrated circuit that operates at high speed and has a low risk of malfunction.

More specifically, one object of the present invention is to increase the ON / OFF current ratio of the current switch circuit by reducing the leakage current when the current switch circuit is OFF in the semiconductor integrated circuit, and to increase the ON / OFF current ratio of the current switch circuit. This is to avoid deterioration of the operating characteristics due to the leakage current at the time of OFF.

Another object of the present invention is to provide a digital-to-analog conversion circuit that operates at high speed and has a low risk of malfunction.

Another object of the present invention is to provide a method for driving a semiconductor integrated circuit that operates at high speed and has a low risk of malfunction.

The present invention for solving the above problems is configured to include the following invention-specific matters or technical features.

That is, the present invention according to a certain viewpoint is a semiconductor integrated circuit including a current switch circuit. In the current switch circuit, a predetermined voltage is applied to the gate to turn it on, a first transistor whose drain is connected to the current output terminal, and a switch control signal are input to the gate, and the current switch circuit flows from the source of the first transistor to the ground. It includes a second transistor that turns on / off the current, and a third transistor that turns on / off the connection between the gate and the source of the first transistor by inputting the switch control signal to the gate. The first transistor may be an input / output N-channel MOS field effect transistor. Further, the second transistor may be an N-channel MOS field effect transistor for a core. Further, the third transistor may be the core P-channel MOS field effect transistor.

The current switch circuit is in a state where it can be operated by the switch control signal while the predetermined voltage is applied to the gate of the first transistor and the first transistor is turned on. In the operating current switch circuit, the second transistor is turned on while the switch control signal is at a high level, whereby the output current flows through the first transistor and the second transistor. Further, in the current switch circuit during operation, the output current is cut off by turning off the second transistor while the switch control signal is at a low level. Further, while the switch control signal is at a low level, the third transistor is turned on and the gate and source of the first transistor are connected and short-circuited, whereby the first transistor is also turned off.

Since the first transistor is an input / output MOS field effect transistor, the leakage current is smaller than that of the second transistor. Further, since the leak current required for the second transistor flows from the gate of the first transistor through the third transistor, the leak current of the second transistor is the output current flowing from the drain of the first transistor to the ground. It has no effect.

Therefore, while the switch control signal is at a low level, the magnitude of the leakage current of the current switch circuit depends on the leakage current of the first transistor and becomes equal to or less than the leakage current of the first transistor. Therefore, by thickening the gate insulating film of the first transistor, the ON / OFF current ratio of the current switch circuit can be increased, so that there is a risk of malfunction due to a decrease in the ON / OFF current ratio due to the leak current. Can be reduced.

Further, since the gate insulating film of the third transistor can be made thinner than that of the first transistor, high-speed switch operation is possible. Therefore, it is possible to extremely shorten the time from the timing when the switch control signal becomes low level until the first transistor is turned off and the leakage current of the current switch circuit becomes equal to or less than the leakage current of the first transistor.

Further, as described above, since the first transistor is an input / output MOS field effect transistor, the leakage current is smaller than that of the second transistor. Therefore, while the switch control signal is low level, the magnitude of the leak current of the current switch circuit depends on the magnitude of the leak current of the first transistor. Further, since the gate insulating film of the second transistor can be thinned to such an extent that sufficiently high-speed operation is possible, high-speed switch operation is possible. The operating speed of the current switch circuit depends on the operating speed of the second transistor. Therefore, the current switch circuit can operate at high speed according to the switch control signal.

This makes it possible to provide a semiconductor integrated circuit that operates at high speed and has a low risk of malfunction.

The semiconductor integrated circuit may include a constant current control circuit that constantly controls the output current of the current switch circuit.

As a result, the output current of the current switch circuit can be controlled to a predetermined magnitude while the switch control signal is at a high level, that is, while the second transistor is ON.

The constant current control circuit may include a current mirror output side transistor constituting a current mirror circuit that controls the output current of the current switch circuit based on a reference current.

As a result, the output current of the current switch circuit can be controlled to a constant current based on the reference current while the switch control signal is at a high level.

In the current switch circuit, the predetermined voltage is applied to the gate to turn it on, a fourth transistor whose drain is connected to the current output terminal, and a logic inversion signal of the switch control signal are input to the gate, and the fourth The fifth transistor that turns on / off the current flowing from the source of the transistor to the ground, and the sixth transistor that the logic inversion signal of the switch control signal is input to the gate and turns on / off the connection between the gate and the source of the fourth transistor. A transistor may be included, and the source of the second transistor and the source of the fifth transistor may be connected. The fourth transistor may be an input / output N-channel MOS field effect transistor. Further, the fifth transistor may be the N-channel MOS field effect transistor for the core. Further, the sixth transistor may be the core P-channel MOS field effect transistor.

This makes it possible to provide a semiconductor integrated circuit provided with a current switch circuit composed of a differential amplifier circuit, which operates at high speed and has a low risk of malfunction.

The semiconductor integrated circuit corresponds to each bit of a digital signal of n (n is an integer of 1 or more) bits, and is based on the n current switch circuits connected in parallel and the digital control signal. A switch control unit that outputs the switch control signal corresponding to each of the current switch circuits may be provided, and the constant current control circuit may include an output current of each of the n current switch circuits. The output current of each of the n current switch circuits may be controlled so that the current corresponds to the corresponding bit of the n-bit digital signal.

This makes it possible to realize a current output type digital-to-analog conversion chip that operates at high speed and has a low risk of malfunction.

Further, according to another aspect, the present invention depends on the total output current of the semiconductor integrated circuit, the control circuit that generates the digital control signal based on the n-bit digital signal, and the n current switch circuits. It is a digital-to-analog conversion circuit including an analog signal output circuit that outputs an analog signal.

This makes it possible to realize a digital-to-analog conversion circuit that operates at high speed and has a low risk of malfunction.

The control circuit includes a delay circuit that delays the rise or fall timing of the digital control signal with respect to the rise or fall timing of the n-bit digital signal, and the rise or fall timing of the digital control signal is the second rise or fall timing. It can correspond to the timing when the transistor switches from ON to OFF.

In the current switch circuit described above, the delay of the rising timing of the output current is slightly increased. This increase in the delay of the rise timing of the output current itself is extremely small to the extent that it hardly causes a problem in operating the current switch circuit at high speed. However, the ON / OFF duty ratio of the output current of the current switch circuit has an error due to the increase in the delay of the rising timing of the output current.

According to the delay circuit, the falling timing of the output current of the current switch circuit can be delayed by delaying the rising or falling timing of the digital control signal with respect to the rising or falling timing of the digital signal. As a result, the increase in the delay of the rising timing of the output current of the current switch circuit can be offset, so that the error of the ON / OFF duty ratio caused by the delay of the rising timing of the output current of the current switch circuit is reduced. be able to.

As a result, in the current output type digital-to-analog conversion circuit, it is possible to reduce the error of the ON / OFF duty ratio caused by the delay of the rising timing of the output current of the current switch circuit.

Further, according to another aspect, the present invention applies a predetermined voltage to the gate of the first transistor whose drain is connected to the current output terminal to turn on the first transistor, and from the source of the first transistor to the ground. The switch control signal is input to the gate of the second transistor that turns on / off the flowing current, and the switch control signal is input to the gate of the third transistor that turns on / off the connection between the gate and the source of the first transistor. It is a driving method of a semiconductor integrated circuit including. The first transistor may be an input / output N-channel MOS field effect transistor. Further, the second transistor may be the N-channel MOS field effect transistor for the core. Further, the third transistor may be the core P-channel MOS field effect transistor.

According to the present invention, it is possible to provide a method for driving a semiconductor integrated circuit that operates at high speed and has a low risk of malfunction.

According to the present invention, it is possible to provide a semiconductor integrated circuit that operates at high speed and has a low risk of malfunction.

More specifically, according to the present invention, in a semiconductor integrated circuit, by reducing the leakage current when the current switch circuit is turned off, the ON / OFF current ratio of the current switch circuit is increased and the current switch circuit is turned off. It is possible to avoid deterioration of the operating characteristics due to the leakage current at the time.

Further, according to the present invention, it is possible to provide a digital-to-analog conversion circuit that operates at high speed and has a low risk of malfunction.

Further, according to the present invention, it is possible to provide a method for driving a semiconductor integrated circuit that operates at high speed and has less risk of malfunction.

Other technical features, objectives, and effects or advantages of the present invention will be demonstrated by the following embodiments described with reference to the accompanying drawings.

It is a circuit diagram which illustrated the structure of the digital-to-analog conversion circuit which concerns on this invention. It is a circuit diagram of the 1st Embodiment of a current switch circuit, and is the circuit diagram which showed the state which the current switch circuit is ON. It is a circuit diagram of the 1st Embodiment of a current switch circuit, and is the circuit diagram which showed the state which the current switch circuit is OFF. It is a circuit diagram of the 2nd Embodiment of a current switch circuit. It is a circuit diagram of the 3rd Embodiment of a current switch circuit. It is a circuit diagram of the 4th Embodiment of a current switch circuit. It is a circuit diagram which illustrated an example of the circuit structure of a control circuit. It is a graph which showed the output signal waveform of a current switch circuit. It is a graph which illustrated the voltage waveform of the digital control signal output by a control circuit. It is a graph which showed the output signal waveform of a current switch circuit.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the embodiments described below are merely examples, and there is no intention of excluding the application of various modifications and techniques not specified below. The present invention can be implemented with various modifications (for example, combining each embodiment) without departing from the spirit of the present invention. Further, in the description of the following drawings, the same or similar parts are represented by the same or similar reference numerals. The drawings are schematic and do not necessarily match the actual dimensions and ratios. Even between drawings, there may be parts where the relationship and ratio of dimensions differ from each other.

The configuration of the digital-to-analog conversion circuit according to the present invention will be described with reference to FIG.

FIG. 1 is a circuit diagram illustrating a configuration of a digital-to-analog conversion circuit according to the present invention. As shown in the figure, the digital-to-analog conversion circuit 1 according to the present invention includes, for example, a semiconductor integrated circuit 10, a current mirror bias circuit 20, a control circuit 30, and an analog signal output circuit 40.

The semiconductor integrated circuit 10, for example, n (n is an integer of 1 or more) corresponding to each bit of a bit of the digital signal, 1 n pieces of current switch circuit ₁₁ connected in parallel, ₁₁ 2, ... and 11 _n , based on the digital control signal, and n current switch circuits ₁₁ 1, ₁₁ 2, switch control unit 12 for outputting a switch control signal _SC 1 to SC _n corresponding to each of the ... 11 _n, and the current output terminal 13 ,including. The semiconductor integrated circuit 10 is, for example, a semiconductor integrated circuit manufactured by a 40 nm process and having a power supply voltage Vdd of 1.1 V, but is not particularly limited thereto, and is manufactured by, for example, a process of 90 nm or less. It may be a semiconductor integrated circuit. Further, the semiconductor integrated circuit 10 may be any circuit as long as it is typically a semiconductor integrated circuit including a current switch circuit.

The current switch circuit 11 ₁ includes, for example, a first transistor QA ₁ , a second transistor QB ₁ and a third transistor QC ₁ . Similarly, the current switch circuit 11 ₂ includes a first transistor QA ₂ , a second transistor QB ₂ and a third transistor QC ₂ , and the current switch circuit 11 _n includes a first transistor QA _n , a second transistor QB _n, and a first transistor. Includes 3 transistors QC _n. Moreover, current switch circuit ₁₁ 1, ₁₁ 2, ... 11 _n, the current switching circuit ₁₁ 1, ₁₁ 2 may include a constant current control circuit for constant current control of the output current _I 1 ~I _n of ... 11 _n.

The current switch circuit 11 ₁ may include a current mirror output side transistor QD ₁ as an example of a constant current control circuit. Current mirror output transistors QD ₁ constitute a current mirror circuit for controlling on the basis of the output current I ₁ of the current switch circuits 11 ₁ to a current (reference current) of the constant current source 21. Moreover, current switch circuit 11 ₂ may include a current mirror output transistors QD _2. Current mirror output transistors QD ₂ constitute a current mirror circuit for controlling on the basis of the output current I ₂ of the current switch circuits 11 ₂ to the current (reference current) of the constant current source 21. Similarly, the current switch circuit 11 _n may include a current mirror output side transistor QD _n . Current mirror output transistors QD _n constitute a current mirror circuit for controlling on the basis of the output current I _n of the current switch circuits 11 _n to the current (reference current) of the constant current source 21. The configuration of the constant current control circuit _{is not particularly limited to the current mirror output side transistors QD 1} , QD ₂ , ... QD _n , and may be configured by, for example, a circuit using resistors having different resistance values. current switch circuits ₁₁ 1, ₁₁ 2, the output current _I 1 ~I _n of ... 11 _n as long as the circuit capable of constant current control may be a circuit of any structure.

In the current switching circuit 11 _1, a first drain of the transistor QA ₁ is connected to the current output terminal 13. The source of the first transistor QA ₁ is connected to the drain of the current mirror output side transistor QD _1. The source of the current mirror output side transistor QD ₁ is connected to the drain of _{the second transistor QB 1.} The source of the second transistor QB ₁ is connected to the ground. The source of the third transistor QC ₁ is connected to the first gate of the transistor QA _1, the third drain of the transistor QC ₁ is connected to the first source of the transistor QA _1. The gates of the second transistor QB ₁ and the third transistor QC ₁ are connected to the switch control unit 12.

In the current switching circuit 11 _1, the first transistor QA _1, for example, operate to ON when the power supply voltage Vdd is applied to the gate. For example, when the switch control signal SC ₁ is input to the gate, the second transistor QB ₁ operates so as to turn on / off the current flowing from the source of the first transistor QA _{1 to the ground via the QD 1.} For example, when the switch control signal SC ₁ is input to the gate, the third transistor QC ₁ operates so as to turn off / on the connection between the gate and the source of the first transistor QA _1.

In current switch circuit 11 _2, the drain of the first transistor QA ₂ is connected to the current output terminal 13. The source of the first transistor QA ₂ is connected to the drain of the current mirror output side transistor QD _2. The source of the current mirror output side transistor QD ₂ is connected to the drain of _{the second transistor QB 2.} The source of the second transistor QB ₂ is connected to the ground. The drain of the third transistor QC ₂ is connected to the gate of the first transistor QA _2, the source of the third transistor QC ₂ is connected to the first source of the transistor QA _2. The gates of the second transistor QB ₂ and the third transistor QC ₂ are connected to the switch control unit 12.

In current switch circuit 11 _2, the first transistor QA _2, for example, operate to ON when the power supply voltage Vdd is applied to the gate. For example, when the switch control signal SC ₂ is input to the gate, the second transistor QB ₂ operates so as to turn on / off the current flowing from the source of the first transistor QA _{2 to the ground via the QD 2.} For example, when the switch control signal SC ₂ is input to the gate, the third transistor QC ₂ operates so as to turn off / on the connection between the gate and the source of the first transistor QA _2.

In the current switch circuit 11 _n , the drain of the first transistor QA _n is connected to the current output terminal 13. The source of the first transistor QA _n is connected to the drain of the current mirror output side transistor QD _n. The source of the current mirror output side transistor QD _n is connected to the drain of _{the second transistor QB n.} The source of the second transistor QB _n is connected to the ground. The drain of the third transistor QC _n is connected to the gate of the first transistor QA _n, the source of the third transistor QC _n is connected to the source of the first transistor QA _n. The gates of the second transistor QB _n and the third transistor QC _n are connected to the switch control unit 12.

In the current switch circuit 11 _n , the first transistor QA _n operates so as to turn ON when, for example, the power supply voltage Vdd is applied to the gate. For example, when the switch control signal SC _n is input to the gate, the second transistor QB _n operates so as to turn on / off the current flowing from the source of the first transistor QA _{n to the ground via the QD n.} For example, when the switch control signal SC _n is input to the gate, the third transistor QC _n operates so as to turn off / on the connection between the gate and the source of the first transistor QA _n.

The first transistors QA ₁ , QA ₂ , ... QA _n can be, for example, an input / output N-channel MOS field effect transistor. The second transistors QB ₁ , QB ₂ , ... QB _n can be, for example, an N-channel MOS field effect transistor for a core. The third transistors QC ₁ , QC ₂ , ... QC _n can be, for example, a core P-channel MOS field effect transistor. The current mirror output side transistors QD ₁ , QD ₂ , ... QD _n can be, for example, an N-channel MOS field effect transistor for a core. The thickness of the gate insulating film of the first transistor QA ₁ , QA ₂ , ... QA _n , the second transistor QB ₁ , QB ₂ , ... QB _{n and} the third transistor QC ₁ , QC ₂ , ... QC _{n is the semiconductor integrated circuit.} 10 in accordance with the specifications of, and more, specifically, for example, current switch circuit ₁₁ 1, ₁₁ 2, ... 11 in accordance with the operating speed and oN / OFF current ratio is required in _n, be appropriately selected can. The core MOS is a MOS whose gate insulating film is relatively thin in one process, the minimum gate length is short, the withstand voltage is low, but high-speed operation is possible, and the input / output MOS is one. The gate insulating film is relatively thick in the process, the gate length distance is longer than that for the core, and the withstand voltage is high, but high-speed operation is difficult.

Current switch circuits ₁₁ 1, ₁₁ 2, ... 11 each of the circuit configuration of _n is not limited to the circuit configuration described above. Explaining the current switch circuit 11 ₁ as an example, for example, the circuit configuration may be such that the positional relationship between _{the current mirror output side transistor QD 1} and the second transistor QB _{1 is exchanged.} More specifically, for example, the first source of the transistor QA ₁ is connected to the second drain of the transistor QB _1, the second source of the transistor QB ₁ is connected to the drain of the current mirror output transistors QD _1, the current mirror The circuit configuration may be such that the source of the output side transistor QD _{1 is connected to the ground.}

Further, the voltage applied to the gates of the first transistors QA ₁ , QA ₂ , ... QA _n is not limited to the power supply voltage Vdd. For example, the second transistor QB ₁ , which is a MOS electric field effect transistor for a core, _If the voltage is lower than the withstand voltage of QB ₂ , ... QB _n and the third transistors QC ₁ , QC ₂ , ... QC n, and the predetermined voltage is turned on by _{the first transistors QA 1} , QA ₂ , ... QA _n. It may be any voltage.

The current mirror bias circuit 20 includes a constant current source 21 and a current mirror input side transistor QE. The constant current source 21 is a current source that supplies a constant current that is a reference current of the current mirror circuit. Current mirror input transistor QE constitute a current mirror circuit for controlling on the basis of current switch circuits _{11 1,} 11 2, ... each output current I1~In of 11n to the reference current. More specifically, in the current mirror input side transistor QE, the drain is connected to the constant current source 21 and the source is connected to the ground. Further, the gate and drain of the current mirror input side transistor QE are connected. Further, the gate of the current mirror input side transistor QE is connected to each gate of _{the current mirror output side transistors QD 1} , QD ₂ , ... QD _n.

The current mirror bias circuit 20 and the current mirror output transistors _QD 1, _QD 2, ... a current mirror circuit composed of QD _n, the current switch circuits _{11 1, 11 2, ... 11} n output currents _I 1 ~I _n of Is controlled so that the current corresponds to the corresponding bit of the n-bit digital signal. For example, the output current I ₁ of the current switch circuits 11 ₁ controlled by a current mirror output transistor QD ₁ corresponds to 0-th bit of the n-bit digital signal, therefore, the current of 2 ⁰ × (1 ×) Be controlled. Output current I ₂ of the current switch circuits 11 _2, which is controlled by the current mirror output transistors QD ₂ corresponds to 1 bit of the n-bit digital signal, therefore, it is controlled to a current of 2 x ¹ (2 times) To. Output current I _n of the current switch circuits 11 _n are controlled by a current mirror output transistor QD _n corresponds to n-1 th bit of the n-bit digital signal, therefore, is controlled by the 2 ^n-1 times the current To. As another embodiment, the current mirror bias circuit 20 and the current mirror output transistors _QD 1, _QD 2, the current mirror circuit composed of ... QD _n, the current switch circuits _{11 1, 11 2, ... 11} n of the output current I ₁ ~I _n may be controlled so that all the same current. In this case, the current switch circuits _{11 1, 11 2, ... 11} n , compared N-bit digital signal, may be provided as many as the n = ^{2 N.}

The control circuit 30 generates, for example, a digital control signal based on an n-bit digital signal and outputs the digital control signal to the switch control unit 12. The control circuit 30 is, for example, a circuit that inputs a digital signal of parallel data, converts it into a digital signal of serial data, and outputs the digital signal to the switch control unit 12, but the control circuit 30 is not particularly limited thereto.

Analog signal output circuit 40, for example, current switch circuits _{11 1, 11 2, ... 11} n output currents _I 1 analog signal corresponding to the total current of ~I _n, i.e., the value corresponding to n-bit digital signal Output an analog signal. The analog signal output circuit 40 may include, for example, a constant current source and a current mirror circuit (not shown) having a power supply voltage Vdd as a power source, but the analog signal output circuit 40 is not particularly limited thereto.

<First Example>
Current switch circuits ₁₁ 1, ₁₁ 2, the operation of ... 11 _n, the current switch circuits 11 ₁ to example will be explained with reference to FIGS.

FIG. 2 is an example of _{a circuit diagram of the current switch circuit 11 1 according} to the first embodiment, and shows a state in which the current switch circuit 11 _{1 is turned on.} Further, FIG. 3 is an example of _{a circuit diagram of the current switch circuit 11 1 according} to the first embodiment, and shows a state in which the current switch circuit 11 ₁ is turned off.

The driving method of the current switch circuit 11 ₁ is, for example, applying a power supply voltage Vdd to the gate of _{the first transistor QA 1 to turn on the first transistor QA 1} and switching control signal SC to the gate of the second transistor QB _{1. 1} is input, and the switch control signal SC ₁ is input to the gate of the third transistor QC _1.

For example, the current switch circuit 11 ₁ is in a state where it can be operated by the _{switch control signal SC 1} while the power supply voltage Vdd is applied to the gate of _{the first transistor QA 1 and is turned on.} In the operating current switch circuit 11 ₁ , the second transistor QB ₁ is turned on while the switch control signal SC ₁ is at H level, whereby the current output terminal 13 to the first transistor QA ₁ and the current mirror output side are turned on. _{The output current I 1} flows to the ground through the transistor QD ₁ and the second transistor QB ₁ (FIG. 2). As described above, the current value of the output current I ₁ is controlled by a constant current by the _{current mirror output side transistor QD 1 and becomes a predetermined value.}

On the other hand, while the switch control signal SC ₁ is at the L level, the output current I ₁ is cut off _{by turning off the second transistor QB 1.} Further, while the switch control signal SC ₁ is at the L level, the third transistor QC ₁ is turned on and the _{gate and the source of the first transistor QA 1} are connected and short-circuited, whereby the first transistor QA ₁ is also short-circuited. Turn off (Fig. 3).

In Figure 3, the leakage current _{I a} of the first transistor QA ₁ flows from the current output terminal 13 first transistor QA _1, to the ground through the current mirror output transistors QD ₁ and the second transistor QB _1. On the other hand, the leak current I _{b of the second transistor QB 1} flows from the gate of the first transistor QA ₁ to the ground via _{the third transistor QC 1.} Therefore, current switching circuit 11 ₁ of the leakage current, i.e., current flowing from the first transistor QA ₁ drain to ground, received only a negligible influence of the second transistor QB ₁ of the leakage current I _b.

Therefore, the switch control signal between SC ₁ is at the L level, the leakage current to the current switch circuit 11 ₁ of the output side, i.e., the first transistor QA ₁ from the current output terminal 13, the current mirror output transistors QD ₁ and the second leakage current flowing through the transistor QB ₁ to ground is equal to the first transistor QA ₁ of the leakage current _{I a.} The first transistor QA ₁ is an input / output MOS field effect transistor. Therefore, under the same conditions where the potential difference between the gate and the source is 0 V, the leak current I _{a of the first transistor QA 1} becomes smaller than before. Therefore, by reducing the first transistor QA ₁ of the leakage current _{I a,} it is possible to increase the ON / OFF current ratio of the current switch circuits 11 _1, the reduction of ON / OFF current ratio due to the leakage current The risk of malfunction can be reduced.

Further, since the third transistor QC ₁ can have a thinner gate insulating film than the first transistor QA ₁ , high-speed switch operation is possible. Therefore, the timing of the switch control signal SC ₁ becomes L level, the time until the leakage current of the current switch circuits 11 ₁ first transistor QA ₁ is turned OFF becomes the first transistor QA ₁ of the leakage current _{I a} very Can be shortened.

Further, as described above, since the first transistor QA ₁ is an input / output MOS field effect transistor, the leakage current is smaller than that of _{the second transistor QB 1.} Therefore, the size between the current switching circuit 11 ₁ of the leakage current switch control signal SC ₁ is at L level depends on the size of the first transistor QA ₁ of the leakage current. Further, since the _{gate insulating film of the second transistor QB 1} can be thinned to such an extent that sufficiently high-speed operation is possible, high-speed switch operation is possible. Then, the operation speed of the current switch circuit 11 ₁ is dependent on the second operating speed of the transistor QB _1. Therefore, the current switch circuit 11 ₁ can operate at high speed according to the switch control signal SC _1.

This makes it possible to provide a semiconductor integrated circuit 10 that operates at high speed and has a low risk of malfunction.

<Second Example>
A second embodiment of the current switch circuit 11 ₁ will be described with reference to FIG.
Figure 4 is an example of a circuit diagram of a current switching circuit 11 ₁ of the second embodiment.

Current switch circuit 11 ₁ of the second embodiment, for example, the power supply voltage Vdd is applied to the gate turned ON, and the first transistor _{QA 1a} having a drain connected to the current output terminal 13 _a, the gate switch control signal SC ₁ are input, a second transistor _{QB 1a} to oN / OFF a current flowing from the source to the ground of the first transistor _{QA 1a,} the switch control signal SC ₁ is input to the gate, the gate of the first transistor _{QA 1a} - between the source Includes a _{third transistor QC 1a} , which turns on / off the connection of the above. The source of the first transistor QA _1a is connected to the drain of the second transistor QB _1a. The source of the second transistor QB _1a is connected to the drain of the current mirror output side transistor QD _1. The source of the current mirror output side transistor QD ₁ is connected to the ground. The drain of the third transistor _{QC 1a} is connected to the gate of the first transistor _{QA 1a,} the source of the third transistor _{QC 1a} is connected to the source of the first transistor _{QA 1a.}

Moreover, current switch circuit 11 ₁ of the second embodiment, for example, the power supply voltage Vdd is applied to the gate turned ON, the fourth transistor QA _1b having a drain connected to the current output terminal 13 _b, switch control to the gate is input logic inversion signal _{SC 1R} signal SC _1, and a fifth transistor _{QB 1b} to oN / OFF a current flowing from the source to the ground of the fourth transistor _{QA 1b,} the logic inversion signal of the switch control signal SC ₁ to the gate _{SC 1R} Is input, and includes a _{sixth transistor QC 1b} that turns on / off the connection between the gate and the source of the fourth transistor QA _1b. The source of the fourth transistor QA _1b is connected to the drain of the fifth transistor QB _1b. The source of the fifth transistor QB _1b is connected to the drain of the current mirror output side transistor QD _1. The drain of the sixth transistor _{QC 1b} is connected to the gate of the fourth transistor _{QA 1b,} the source of the sixth transistor _{QC 1b} is connected to a source of the fourth transistor QA ₁ b. The source of the fifth transistor QB _1b is connected to the source of the second transistor QB _1a.

The first transistor QA _1a may be, for example, an input / output N-channel MOS field effect transistor. The second transistor QB _1a may be, for example, an N-channel MOS field effect transistor for a core. The third transistor QC _1a can be, for example, a core P-channel MOS field effect transistor. Similarly, the fourth transistor QA _1b can be, for example, an input / output N-channel MOS field effect transistor. The fifth transistor QB _1b may be, for example, an N-channel MOS field effect transistor for a core. The sixth transistor QC _1b can be, for example, a core P-channel MOS field effect transistor. The current mirror output side transistor QD ₁ may be, for example, an N-channel MOS field effect transistor for a core.

As described above, the current switch circuit 11 ₁ of the second embodiment is a differential amplifier circuit. According to the current switch circuit 11 ₁ of the second embodiment, it is possible to provide a semiconductor integrated circuit 10 including a _{current switch circuit 11 1} composed of a differential amplifier circuit that operates at high speed and has a low risk of malfunction. ..

<Third Example>
Figure 5 is an example of a circuit diagram of a current switching circuit 11 ₁ of the third embodiment.

Current switch circuit 11 ₁ of the third embodiment does not include the current mirror output transistors QD _1, the first source of the transistor QA ₁ is connected to the second drain of the transistor QB _1, the second transistor QB ₁ in that the source is connected to the ground, different from the current switching circuit 11 ₁ of the first embodiment. The circuit configuration of the other is omitted since the same circuit configuration as the current switch circuit 11 ₁ of the first embodiment, the same to the components detailed denoted by the same reference numerals explained.

Current switch circuit 11 ₁ of the third embodiment of such a circuit configuration, similar to the current switch circuit 11 ₁ of the first embodiment, and operates at high speed, and to provide a semiconductor integrated circuit 10 possibly with less malfunction be able to.

<Fourth Example>
Figure 6 is an example of a circuit diagram of a current switching circuit 11 ₁ in the fourth embodiment.

The current switch circuit 11 ₁ of the fourth embodiment does not include the current mirror output side transistor QD ₁ , and the source of the second transistor QB _{1a and} the source of the second transistor QB _1b are connected to the ground. differs from the current switching circuit 11 ₁ of the second embodiment. The circuit configuration of the other is omitted since the same circuit configuration as the current switch circuit 11 ₁ of the second embodiment, the same to the components detailed denoted by the same reference numerals explained.

Current switch circuit 11 ₁ of the fourth embodiment of such a circuit configuration, similar to the current switch circuit 11 ₁ of the second embodiment operates in high speed, and is composed of a differential amplifier circuit risk is small malfunction it is possible to provide a semiconductor integrated circuit 10 which current comprises a switch circuit 11 ₁ that.

<Control circuit>
The configuration of the control circuit 30 will be described in detail with reference to FIGS. 7 to 10.

FIG. 7 is a circuit diagram illustrating an example of the circuit configuration of the control circuit 30. _{As shown in the figure, the control circuit 30 inputs digital signals VL 0 to VL 3} , which are 4-bit parallel data, as an example of an n-bit digital signal, and digitally controls the digital signals, which are serial data. It is a digital logic circuit that converts to a signal VO_SEL and outputs it. The control circuit 30 includes, for example, two NAND circuits 311 and 312, two NOR circuits 313 and 314, a NOT circuit 315 and a buffer circuit 316.

The NAND circuit 311 is, for example, a two-input NAND circuit. _{The 0th bit digital signal VL 0} and the 1st bit digital signal VL ₁ of the 4-bit digital signal are input to the NAND circuit 311. The NAND circuit 312 is, for example, a two-input NAND circuit. The second-bit digital signal VL ₂ and the third-bit digital signal VL ₃ of the 4-bit digital signal are input to the NAND circuit 312. The NOR circuit 313 is, for example, a 2-input NOR circuit. The output signal of the NAND circuit 311 and the output signal of the NAND circuit 312 are input to the NOR circuit 313. The NOR circuit 314 is, for example, a 2-input NOR circuit. The output signal of the NOR circuit 313 and the output signal of the buffer circuit 316 are input to the NOR circuit 314. For example, the output signal of the NOR circuit 314 is input to the NOT circuit 315. The output signal of the NOT circuit 315 is input to the switch control unit 12 (FIG. 1) of the semiconductor integrated circuit 10 as a digital control signal VO_SEL. For example, the output signal of the NOR circuit 313 is input to the buffer circuit 316.

Digital signals VL _{0 to VL 3} are, for example, negative logic digital signals. When the digital signals VL _{0 to VL 3} are all H level, the control circuit 30 outputs the H level digital control signal VO_SEL. On the other hand, when _{any one of the digital signals VL 0 to VL 3} reaches the L level, the control circuit 30 outputs the L level digital control signal VO_SEL.

The buffer circuit 316 typically functions as a delay circuit, and the fall timing of the digital control signal VO_SEL with respect to the fall timing (timing from H level to L level) of _{the 4-bit digital signals VL 0 to VL 3 (No. 1).} This is a circuit for shifting (delaying) (timing corresponding to the timing at which the two-transistor QB _{1 switches from ON to OFF).} In the NOR circuit 314, the output signal changes from the L level to the H level when both of the two input signals change from the H level to the L level. Therefore, for example, when any of the 4-bit digital signal _VL 0 _{~VL 3} changes from the H level to the L level, after the output signal of the NOR circuit 313 is changed from H level to L level, further, the output of the buffer circuit 316 When the signal changes from H level to L level, the output signal of the NOR circuit 314 changes from L level to H level. Therefore, with respect to the fall timing of the 4-bit digital signals VL _{0 to VL 3} , a deliberate delay occurs in the fall timing of the digital control signal VO_SEL by the delay time generated in the buffer circuit 316.

On the other hand, in the NOR circuit 314, when one of the two input signals changes from the L level to the H level, the output signal changes from the H level to the L level at that time. Therefore, when any of the 4-bit digital signal _VL 0 _{~VL 3} changes from L level to H level, when the output signal of the NOR circuit 313 is changed from L level to H level, the output signal of the NOR circuit 314 is H From level to L level. Therefore, there is no intentional delay in the rising timing of the digital control signal VO_SEL with respect to the rising timing of the 4-bit digital signals VL _{0 to VL 3.}

Although a circuit that shifts (delays) the fall timing of the digital control signal VO_SEL with respect to the fall timing of the 4-bit digital signals VL _{0 to VL 3 has been described as an example, the present invention is particularly limited to this.} is not it. For example, when the rising timing (timing from L level to H level) of the 4-bit digital signals VL _{0 to VL 3 corresponds to the timing at which the second transistor QB 1} switches from ON to OFF, 4 The rising timing of the digital control signal VO_SEL with respect to the rising timing of the digital signals VL _{0 to VL 3 of the bit may be shifted (delayed).}

Figure 8 is a graph showing the output signal waveform of the current switch circuit 11 _1. In the graph of FIG. 8, the horizontal axis represents time t, the vertical axis represents the output current I of the current switch circuit 11 _1. The solid line waveform in FIG. 8, an illustration of the output current waveform of the current switch circuits 11 ₁ of the first embodiment shown in FIGS. 1 to 3, the broken line waveform in FIG. 8, FIGS. 1 to 3 The output current waveform in the case where the third transistor QC ₁ is not provided in the current switch circuit 11 _{1 of the first embodiment shown in the above is illustrated.}

As compared with the configuration in which the third transistor QC ₁ is not provided, the current switch circuit 11 _{1 according} to the present invention has a reduced leakage current to the output side as described above. The reduction width ΔI of the leak current to the output side of the current switch circuit 11 ₁ corresponds to the difference between the leak current of _{the first transistor QA 1 and} the leak current of the second transistor QB _1. When compared with the configuration in which the third transistor QC ₁ is not provided, the current switch circuit 11 _{1 according} to the present invention has a time delay from the rising timing of the digital control signal VO_SEL to the rising timing of the output current I, as shown in the figure. It increases by t1. Increase itself delay the rise timing of the output current I, in terms of operating the current switch circuit 11 ₁ at high speed, it is the degree of extremely small that matters little. However, ON / OFF duty ratio of the output current I of the current switch circuits 11 ₁ would error caused by an increase in the delay of the rising timing of the output current I.

FIG. 9 is a graph showing the voltage waveform of the digital control signal VO_SEL output by the control circuit 30. In FIG. 9, the horizontal axis is time t, and the vertical axis is the voltage V of the digital control signal VO_SEL. The waveform of the solid line in FIG. 9 shows the voltage waveform of the digital control signal VO_SEL output by the control circuit 30 shown in FIG. 7, and the waveform of the broken line in FIG. 9 shows the waveform in the control circuit 30 shown in FIG. The voltage waveform of the digital control signal VO_SEL is shown in the case where the NOR circuit 314 is replaced with the NOT circuit without providing the buffer circuit 316.

Figure 10 is a graph illustrating an output signal waveform of the current switch circuit 11 _1. In the graph of FIG. 10, the horizontal axis represents time t, the vertical axis represents the output current I of the current switch circuit 11 _1. The waveform of the solid line in FIG. 10 performs switch control of _{the current switch circuit 11 1} of the first embodiment shown in FIGS. 1 to 3 based on the digital control signal VO_SEL output by the control circuit 30 shown in FIG. 7. It is an output current waveform in the case of. The waveform of the broken line in FIG. 10 is based on the digital control signal VO_SEL in the control circuit 30 shown in FIG. 7 in which the NOR circuit 314 is changed to the NOT circuit without providing the buffer circuit 316. It is an output current waveform when the switch control _{of the current switch circuit 11 1} of the 1st Embodiment illustrated in FIG. 3 is performed.

As described above, with respect to the falling timing of the 4-bit digital signals VL _{0 to VL 3} , there is an intentional delay in the falling timing of the digital control signal VO_SEL by the delay time t2 generated in the buffer circuit 316. Occurs (Fig. 9). Thus, by delaying the fall timing of the digital control signal VO_SEL respect to the falling timing of the digital signal _VL 0 _{~VL 3,} the amount corresponding the delay time _{t 2,} the fall of the output current I of the current switch circuits 11 ₁ The timing can be delayed. Thereby, it is possible to cancel out the delay time t ₁ of the rising timing of the output current I of the current switch circuits 11 _1, ON / OFF caused due to the delay of the rising timing of the output current I of the current switch circuits 11 ₁ The duty ratio error can be reduced (FIG. 10).

<Other embodiments>
Each of the above embodiments is an example for explaining the present invention, and is not intended to limit the present invention to these embodiments only. The present invention can be carried out in various forms as long as it does not deviate from the gist thereof.

For example, in the methods disclosed herein, steps, actions or functions may be performed in parallel or in a different order, as long as the results are not inconsistent. The steps, actions and functions described are provided merely as examples, and some of the steps, actions and functions may be omitted or combined with each other to the extent that they do not deviate from the gist of the invention. It may be one, or other steps, actions or functions may be added.

Further, although various embodiments are disclosed in the present specification, the specific features (technical matters) in one embodiment may be added to other embodiments or the other embodiments while appropriately improving the features (technical matters). It can be replaced with specific features in the form, such form is also included in the gist of the invention.

The present invention can be widely used in the field of semiconductor integrated circuits.

10 Semiconductor integrated circuit 11 ₁ and 11 _{2 to} 11 _n Current switch circuit 12 Switch control unit 13 and 13 _a , 13 _b Current output terminal 20 Current mirror bias circuit 21 Constant current source 30 Control circuit 40 Analog signal output circuit 311 and 312 NAND Circuit 313, 314 NOR circuit 315 NOT circuit 316 Buffer circuit QA ₁ and QA _{2 to QA n} 1st transistor QB ₁ and QB _{2 to QB n} 2nd transistor QC ₁ and QC _{2 to QC n} 3rd transistor QD ₁ and QD ₂ ~ QD _n Current mirror output side transistor QE Current mirror input side transistor

Claims (3)

A digital-to-analog conversion circuit including a semiconductor integrated circuit, a control circuit, and an analog signal output circuit.
The semiconductor integrated circuit is
N current switch circuits connected in parallel corresponding to each bit of a digital signal of n (n is an integer of 1 or more) bits, and
The output current of each of the n current switch circuits is controlled so that the output current of each of the n current switch circuits becomes a current corresponding to the corresponding bit of the n-bit digital signal. Constant current control circuit and
A switch control unit that outputs a switch control signal corresponding to each of the n current switch circuits based on the digital control signal is provided.
The current switch circuit is
The first transistor, which is an input / output N-channel MOS field effect transistor in which a predetermined voltage is applied to the gate to turn it on and the drain is connected to the current output terminal,
A second transistor, which is an N-channel MOS field effect transistor for the core, which turns on / off the current flowing from the source of the first transistor to the ground when a switch control signal is input to the gate, and
The switch control signal is input to the gate, and the third transistor, which is a P-channel MOS field effect transistor for a core that turns on / off the connection between the gate and the source of the first transistor, is included.
The gate insulating film of said first transistor, rather thick than the second preparative transistor and the respective gate insulating film of the third DOO transistor,
The control circuit generates the digital control signal based on the n-bit digital signal.
The control circuit is a delay circuit that delays the rise or fall timing of the digital control signal with respect to the rise or fall timing of the digital signal of the n bits so as to correspond to the timing at which the second transistor switches from ON to OFF. Including
The analog signal output circuit outputs an analog signal corresponding to the total output current of the n current switch circuits.
Digital-to-analog conversion circuit. The digital-to-analog conversion circuit according to claim 1 , wherein the constant current control circuit includes a current mirror output side transistor constituting a current mirror circuit that controls the output current of the current switch circuit based on a reference current. , Digital-to-analog conversion circuit . The digital-to-analog conversion circuit according to claim 1 or 2 , wherein the current switch circuit is
The fourth transistor, which is an input / output N-channel MOS field effect transistor in which the predetermined voltage is applied to the gate to turn it on and the drain is connected to another current output terminal,
A fifth transistor, which is an N-channel MOS field effect transistor for the core, in which a logic inversion signal of the switch control signal is input to the gate and turns on / off the current flowing from the source of the fourth transistor to the ground, and
A sixth transistor, which is a core P-channel MOS field effect transistor in which a logic inversion signal of the switch control signal is input to the gate and turns on / off the connection between the gate and the source of the fourth transistor, is included.
A digital-to-analog conversion circuit in which the source of the second transistor and the source of the fifth transistor are connected.

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