KR20040042774A - Display device - Google Patents

Abstract

PURPOSE: A display device is provided to suppress noises by offsetting noises having opposite polarities overlapped on a grayscale voltage. CONSTITUTION: A display device includes a pixel representing a brightness according to an applied voltage, a grayscale voltage generating circuit generating 2¬N grayscale voltages on 2¬N voltage nodes, respectively, and a decode circuit for selecting one of the grayscale voltages and outputting the selected grayscale voltage. The decode circuit includes 2¬N decode units which, respectively, are arranged corresponding to the n¬N grayscale voltages. The decode unit includes a first field effect transistor of a first conductive type and a second field effect transistor of a second conductive type. The first transistor corresponds to each of N bits of a digital signal and is coupled between an output node and a voltage node in series. The second transistor corresponds to each of N bits of a digital signal and is coupled between the output node and the voltage node in series. One of the first and second transistors receives a common bit and an inverted bit at control electrode thereof.

Description

Display device {DISPLAY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device such as a character or an image, and more particularly to a display device capable of executing gradation display based on a digital signal.

As display panels, such as a personal computer, a television receiver, a portable telephone, and a portable information terminal, the display apparatus which has a liquid crystal element and an electroluminescence (EL) element as a display pixel is used. This display device has advantages in terms of low power consumption and small size and light weight as compared with the conventional type.

The display luminance of the pixel including the liquid crystal element or the EL element changes depending on the level of the applied voltage (hereinafter, the voltage applied to the pixel is also referred to as "display voltage"). Therefore, in these pixels, gray scale display can be performed by setting the display voltage step by step so as to correspond to the intermediate luminance. In general, a configuration is adopted in which the display voltage is set in response to the decoding result of the plural-bit digital signal for showing the gradation display brightness.

Therefore, in the display device capable of gray scale display, a decoding circuit for decoding the digital signal and recognizing the indicated gray scale luminance is required. In general, in the decoding circuit, since a large number of transistor switches are required for decoding, reducing the circuit scale becomes a problem.

In order to solve this problem, for example, Japanese Patent Laid-Open No. 2001-34234 (Figs. 8 and 9) discloses a configuration of a decode circuit called a tournament system.

In this system, in order to display the grayscale luminance of ^2N levels by the N-bit (N: integer of 2 or more) digital signal, between the node where the ^2N grayscale voltages are respectively generated and the node where the display voltage is generated. A structure of a decode circuit in which N N-MOS (Metal Oxide Semiconductor) transistors are connected in series, and a structure of a decode circuit in which the number of N-MOS transistors connected in series in the transfer path of the gradation voltage are reduced is disclosed.

However, in the configuration of the decode circuit shown in Fig. 8 of the above publication, the decode circuit area can be reduced in size, but it is necessary to compensate for the voltage drop caused by the threshold voltage of the N-MOS transistor. For this reason, it is necessary to set the gate voltage of the N-MOS transistor which comprises a decode circuit at least as much as a threshold voltage with respect to the gray voltage to be transmitted.

As a result, since the amplitude of the gate voltage is increased, the noise amplitude that can be transmitted through the parasitic capacitance between the gate electrode and the source electrode or the drain electrode of the N-MOS transistor is also increased, and the influence on the display voltage applied to the pixel is increased. The problem arises.

In the decoding circuit shown in Fig. 9 of the above publication, the voltage drop of the gray voltage is suppressed by reducing the number of N-MOS transistors included in the gray voltage transfer path. On the other hand, however, since the number of transistors required in the entire decode circuit increases, problems arise in terms of miniaturization of circuits, production yields, and the like.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to provide an gradation displayable image display device having a decode circuit having a high noise resistance and a small circuit area.

1 is a block diagram showing an overall configuration of a liquid crystal display device shown as a representative example of a display device according to an embodiment of the present invention.

2 is a circuit diagram illustrating a configuration example of a pixel including an EL element.

3 is a circuit diagram showing a configuration of a decode circuit according to the first embodiment.

4 is a circuit diagram showing a first configuration example of a decode circuit according to the second embodiment.

5 is a circuit diagram showing a second configuration example of a decode circuit according to the second embodiment.

6 is a circuit diagram showing a third configuration example of the decode circuit according to the second embodiment.

7 is a circuit diagram showing a configuration of a decode circuit according to the third embodiment.

FIG. 8 is a circuit diagram illustrating a configuration example of the electrical resistance shown in FIG. 7.

9 is a circuit diagram illustrating a configuration example of the electrical resistance shown in FIG. 7.

10 is a structural diagram showing a structural example of a P-type TFT and an N-type TFT constituting a decode circuit according to the present invention;

<Explanation of symbols for the main parts of the drawings>

10: liquid crystal display device

20: liquid crystal array unit

25 pixels

26: switch element

27: maintenance capacity

28: liquid crystal display element

30: gate driver

40: source driver

50: shift register

52, 54: data latch circuit

60: gradation voltage generating circuit

70, 71, 71 #, 72: decode circuit

75, 76: current limiting element

77: gradation voltage transfer gate

90: insulator substrate

95 semiconductor film

101, 102, 151, 152: drain region

103 and 153: gate insulating film

104, 154: gate electrode

105, 106, 155, 156: electrode

D0 to D5: Display signal bits

/ D0 to / D5: Invert bit

DL, DL1, DL2: data line

DU (61) to DU (64), DU: decode unit

GL, GL1: Gate Line

N1 to N64: gradation voltage node

N61a #, N61b #, N62a #, N62b #, N63a, N63b, N63a #, N63b #, N64a, N64b, N64a #, N64b #

Nd, Nd1: Decode output node

Nc: common electrode node

Ng (64), / Ng (64): control node

Np: pixel node

SIG: Display signal

T0a (j) to T5a (j), 78a, 79a, 80a: N-type transistor (j: natural number)

T0b (j) to T5b (j), 78b, 79b, 80b: N-type transistor (j: natural number)

V1 to V64: Gradation Voltage

A display device according to the present invention is a display device for performing gradation display in accordance with a digital signal of N bits (N: integer of 2 or more), comprising: a pixel displaying luminance according to an applied display voltage, and a stepwise ^2N gradation A gradation voltage generation circuit for generating a voltage at each of the 2 ^N voltage nodes, and a decode circuit for selecting one of the 2 ^N gradation voltages according to a digital signal and outputting the selected gradation voltage as a display voltage to an output node. do. The decode circuit includes 2 ^N decode units provided respectively corresponding to the 2 ^N gray voltages, each decode unit corresponding to N bits of the digital signal, respectively, in series between the output node and the corresponding voltage node. N first field-effect transistors of the first conductivity type to be connected and N second electric fields of the second conductivity type respectively corresponding to N bits of the digital signal and connected in series between the output node and the corresponding voltage node. Has an effect transistor, and the first and second conductivity types are opposite conductivity types, one of N first field effect transistors and N second field effect transistors, one corresponding to the same bit of the digital signal. Receives one of the same bit and its inverted bit into each control electrode.

A display device according to another aspect of the present invention is a display device for performing gradation display according to an N bit (N: integer of 2 or more), a pixel for displaying luminance according to an applied display voltage, and stepwise two. and a gradation voltage generation circuit for generating the ^N number of gray-scale voltages to the 2 ^N different voltage nodes, respectively, a decoding circuit for selecting in accordance with one of the 2 ^N of gray-scale voltage to a digital signal, and output to the output node as the display voltage to the selected gray scale voltage Equipped. The decode circuit includes 2 ^N decode units provided corresponding to the 2 ^N gray voltages, respectively, each decode unit corresponding to N bits of the digital signal, the first control being electrically coupled with the first voltage. N first field-effect transistors of the first conductivity type connected in series between the node and the second voltage, a second control node corresponding to N bits of the digital signal, respectively, and electrically coupled to the second voltage; A first conductivity type having N second field effect transistors of a second conductivity type connected in series between the first voltages, and a control electrode connected between the output node and a voltage node corresponding to the second control node; A third field effect transistor of a type and a fourth field effect transistor of a second conductivity type having a control electrode connected between an output node and a voltage node corresponding to the first control node, and having a first And second degree The typical type is opposite to each other, and among the N first field-effect transistors and the N second field-effect transistors, one corresponding to the same bit of the digital signal is the same bit and one of the inverted bits thereof. By the control electrode.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same code | symbol in a figure shall show the same or an equivalent part.

[First Embodiment]

1 is a block diagram showing the overall configuration of a liquid crystal display device 10 shown as a representative example of a display device according to an embodiment of the present invention.

Referring to FIG. 1, the liquid crystal display device 10 according to the exemplary embodiment includes a liquid crystal array unit 20, a gate driver 30, and a source driver 40.

The liquid crystal array unit 20 includes a plurality of pixels 25 arranged in a matrix. The gate line GL is disposed corresponding to each of the pixel rows (also referred to as "pixel rows"), and the data lines DL are disposed respectively corresponding to the columns of pixels (also referred to as "pixel columns" below). . In Fig. 1, the pixels in the first and second columns of the first row and the gate lines GL1 and the data lines DL1 and DL2 corresponding thereto are representatively shown.

Each pixel 25 includes a switch element 26 provided between a corresponding data line DL and a pixel node Np, a storage capacitor 27 and a liquid crystal display element connected in parallel between the pixel node Np and the common electrode node Nc. Has 28. According to the voltage difference between the pixel node Np and the common electrode node Nc, the orientation of the liquid crystal in the liquid crystal display element 28 is changed, and in response, the display luminance of the liquid crystal display element 28 is changed. This makes it possible to control the luminance of each pixel in accordance with the display voltage transmitted to the pixel node Np through the data line DL and the switch element 26. The switch element 26 is comprised with an N-type field effect transistor, for example.

That is, intermediate luminance can be obtained by applying an intermediate voltage difference between the voltage difference corresponding to the maximum brightness and the voltage difference corresponding to the minimum brightness between the pixel node Np and the common electrode node Nc. That is, by setting the display voltage step by step, it becomes possible to obtain gradational brightness.

The gate driver 30 activates the gate line GL in order based on a predetermined scanning period. The gate of the switch element 26 is connected to the corresponding gate line GL. Therefore, during the activation (H level) period of the corresponding gate line GL, the pixel node Np is connected to the corresponding data line DL. The switch element 26 is generally comprised from TFT (Thin-Film Transistor) element formed on the same insulator substrate (glass substrate, resin substrate, etc.) as the liquid crystal display element 28. FIG. The display voltage transmitted to the pixel node Np is maintained by the storage capacitor 27.

Alternatively, the pixel 25 in FIG. 1 may be replaced by the pixel including the EL element shown in FIG. 2.

Referring to FIG. 2, the pixel 25 # includes a switch element 26, a storage capacitor 27 #, an EL display element 28 #, and a current driving transistor 29. The switch element 26 is provided between the corresponding data line DL and the pixel node Np similarly as in the pixel 25, and its gate is connected with the corresponding gate line GL. The storage capacitor 27 # is connected between the pixel node Np and the voltage VDD. The EL display element 28 # and the current driving transistor 29 are connected in series between the voltage VDD and the voltage VSS. The current drive transistor 29 is composed of, for example, a P-type field effect transistor. The switch element 26 and the current drive transistor 29 are generally formed on the same insulator substrate as the EL display element 28 #.

The switch element 26 connects the pixel node Np with the data line DL during the activation (H level) period of the corresponding gate line GL. As a result, the display voltage on the data line DL is transmitted to the pixel node Np. The voltage of the pixel node Np is maintained by the storage capacitor 27 #.

The current driving transistor 29 has a gate connected to the pixel node Np, and supplies the current Iel corresponding to the voltage of the pixel node Np to the EL display element 28 #. The display luminance of the EL display element 28 # changes in accordance with the supplied passing current Iel. Therefore, also in the pixel 25 #, by setting the display voltage applied to the pixel in stages, the luminance of the EL display element can be set to be gray level.

As will be apparent from the following description, the present invention focuses on the configuration of peripheral circuits, particularly decoder circuits, in a display device capable of displaying intermediate luminance according to the display voltage to which each pixel is applied. Therefore, in the liquid crystal display device shown as a representative example of the display device in the embodiment of the present invention described below, the pixel 25 including the liquid crystal display element is replaced with the pixel 25 # including the EL element. The display device according to the present invention which performs display by the EL element can be configured by using the peripheral circuit having the same configuration.

Referring back to FIG. 1, the source driver 40 outputs the display voltage set in stages by the display signal SIG, which is an N-bit digital signal, to the data line DL. In the present embodiment, the configuration in the case where N = 6, that is, when the display signal SIG consists of the display signal bits D0 to D5 will be described.

On the basis of the 6-bit display signal SIG, gray scale display of 2 ⁶ = 64 steps is enabled in each pixel. Further, when one color display unit is formed from one pixel of R (Red), G (Green), and B (Blue), color display of about 260,000 colors is possible.

The source driver 40 includes a shift register 50, data latch circuits 52 and 54, a gradation voltage generation circuit 60, a decode circuit 70, and an analog amplifier 80.

The display signal SIG is generated in series corresponding to the display luminance of each pixel 25. That is, the display signal bits D0 to D5 at each timing indicate the display luminance in one pixel 25 in the liquid crystal array unit 20.

The shift register 50 instructs the data latch circuit 52 to receive the display signal bits D0 to D5 at a timing synchronized with a predetermined period in which the setting of the display signal SIG is switched. The data latch circuit 52 receives and holds display signal SIG for one pixel row generated in series in order.

At the timing when the display signal SIG for one pixel row is received by the data latch circuit 52, in response to the activation of the latch signal LT, the display signal group latched by the data latch circuit 52 is transferred to the data latch circuit 54. Delivered.

The gray voltage generator 60 is composed of 64 voltage divider resistors connected in series between the high voltage VH and the low voltage VL, and generates gray level voltages V1 to V64 at the gray level voltage nodes N1 to N64, respectively.

The decode circuit 70 decodes the display signal latched by the data latch circuit 54 and selects gradation voltages V1 to V64 based on the decode. The decode circuit 70 generates the selected gradation voltage (one of V1 to V64) as the display voltage to the decode output node Nd. In the present embodiment, the decode circuit 70 outputs display voltages for one row in parallel based on the display signals latched by the data latch circuit 54. In addition, in FIG. 1, the decode output nodes Nd1 and Nd2 corresponding to the data lines DL1 and DL2 of a 1st column and a 2nd column are shown typically.

The analog amplifier 80 includes the decode output nodes Nd1, Nd2,... The analog voltages corresponding to the display voltages outputted by the data lines are denoted by the data lines DL1, DL2,. Will be printed respectively.

In addition, although FIG. 1 illustrates the configuration of the liquid crystal display device 10 in which the gate driver 30 and the source driver 40 are integrally formed with the liquid crystal array unit 20, the gate driver 30 and the source driver ( For 40, it can also be provided as an external circuit of the liquid crystal array unit 20.

Next, the configuration of the decode circuit will be described in detail.

FIG. 3 is a circuit diagram showing the configuration of the decode circuit according to the first embodiment shown in FIG.

In FIG. 3, only the structure of the part corresponding to gradation voltage V64 and V63 among the structure corresponding to decode output node Nd1 is shown typically.

Referring to FIG. 3, the decode circuit 70 according to the first embodiment includes a decode unit DU 64 corresponding to the gray voltage V64 and a decode unit DU 63 corresponding to the gray voltage V63.

The decode unit DU 64 is provided between the N-type field effect transistors T0a (64) to T5a (64) connected in series between the gradation voltage node N64 and the decode output node Nd1, and the gradation voltage node N64 and the decode output node Nd1. P-type field effect transistors T0b (64) to T5b (64) connected in series. In the following description, the N-type field effect transistor and the P-type field effect transistor are simply referred to as N-type transistor and P-type transistor, respectively.

The display signal bits D0 to D5 are respectively input to the gates of the N-type transistors T0a (64) to T5a (64). In contrast, inverting bits / D0 to / D5 of the display signal bits D0 to D5 are respectively input to the gates of the P-type transistors T0b (64) to T5b (64).

As a result, when the display signal bits (D0, D1, D2, D3, D4, D5) = (1, 1, 1, 1, 1, 1), the N-type transistor T0a 64 in the decode unit DU 64. T5a (64) and P-type transistors T0b (64) to T5b (64) are both turned on, and the gradation voltage V64 of the gradation voltage node N64 is transferred to the decode output node Nd1.

Similarly, the decode unit DU 63 is provided between the N-type transistors T0a 63 to T5a 63 connected in series between the gray voltage node N63 and the decode output node Nd1, and between the gray voltage node N63 and the decode output node Nd1. P type transistors T0b (63) to T5b (63) connected in series.

Inverting bits / D0 and display signal bits D1 to D5 of the display signal bit D0 are respectively input to the gates of the N-type transistors T0a (63) to T5a (63). In contrast, the inverting bits / D1 to / D5 of the display signal bits D0 and the display signal bits D1 to D5 are respectively input to the gates of the P-type transistors T0b 63 to T5b 63.

As a result, when the display signal bits (D0, D1, D2, D3, D4, D5) = (0, 1, 1, 1, 1, 1), the N-type transistor T0a (63) in the decode unit DU (63). T5a (63) and P-type transistors T0b (63) to T5b (63) are all turned on, and the gradation voltage V63 of the gradation voltage node N63 is transferred to the decode output node Nd1.

Although not shown in the figure, the decode units configured in the same manner are also arranged for the gradation voltages V1 to V62. Further, the state of the display signal bits (D0, D1, D2, D3, D4, D5) = (0, 0, 0, 0, 0, 0) corresponds to the gradation voltage V1, and (D0, D1, D2, D3). , D4, D5) = (1, 1, 1, 1, 1, 1) corresponds to the gray voltage V64, and corresponding to the increment of the display signal bits D0 to D5, the gray voltage is changed from V1 to V64. Step by step. Thereby, according to the display signal bits D0 to D5, one of the gradation voltages V1 to V64 can be selectively output to the decode output node Nd1. Although not shown in figure, the same structure is also arrange | positioned in the other decoding output node Nd in the decoding circuit 70. As shown in FIG.

As described above, in the decode circuit 70 according to the first embodiment, the same number of N-type transistors and P-type transistors are connected in parallel in each transfer path of the gradation voltages V1 to V64, and the display signal bit D0. Each of the N-type transistors and the P-type transistors corresponding to the same bit in -D5 is configured to be driven by receiving one of the same bit and its inverted bit as a gate.

Therefore, between the corresponding N-type transistors and P-type transistors, through the parasitic capacitance between the gate electrode and the source electrode or the drain electrode, the noises superimposed on the gradation voltage are reversed from each other and canceled with each other. As a result, it becomes possible to suppress the noise to the display voltage, which is a problem in the decoding circuit according to the prior art, and to improve the display accuracy.

Second Embodiment

4 is a circuit diagram showing a first configuration example of the decode circuit 71A according to the second embodiment. In the configuration according to the second embodiment, in the liquid crystal display device 10 shown in FIG. 1, the decode circuit 70 is replaced only by the decode circuits 71A (71B, 71C), and the configuration of the other parts is the same. to be.

Referring to Fig. 4, in the decode circuit 71A according to the first configuration example of the second embodiment, in addition to the configuration of the decode circuit 70 shown in Fig. 3, corresponding display signal bits are provided between adjacent decode units. Since the paths of the group of N-type transistors received by the gate with the same polarity are shared, one of the connection nodes of these N-type transistors is electrically coupled.

Similarly, since the paths of the P-type transistor groups that receive the corresponding display signal bits as gates with the same polarity are shared between adjacent decode units, one of the connection nodes of these P-type transistors is also electrically coupled.

For example, the connection node N64a of the N-type transistors T0a 64 and T1a 64 in the decode unit DU 64 and the connection of the N-type transistors T0a 63 and T1a 63 in the decode unit DU 63. Node N63a is electrically coupled. Display signal bits D1 to D5 are respectively input to the gates of the N-type transistors T1a (64) to T5a (64) connected between the connection node N64a and the decode output node Nd1, and are connected between the connection node N63a and the decode output node Nd1. Display signal bits D1 to D5 having the same polarity as the N-type transistors T1a (64) to T5a (64) are respectively input to the gates of the connected N-type transistors T1a (63) to T5a (63).

As a result, the respective paths of the N-type transistors T1a (64) to T5a (64) and T1a (63) to T5a (63) in which respective gates are driven by the display signals bits D1 to D5 of the same polarity are provided. By connecting in parallel, the electrical resistance between the gradation voltage nodes N63 and N64 and the decode output node Nd1 is reduced.

Similarly, connection node N64b of P-type transistors T0b 64 and T1b 64 in decode unit DU 64 and connection node N63b of P-type transistors T0b 63 and T1b 63 in decode unit DU 63. Is electrically coupled. Inverting bits / D0 to / D5 of the display signal bits D1 to D5 are respectively input to the gates of the P-type transistors T1b (64) to T5b (64) connected between the connection node N64b and the decode output node Nd1, respectively. Inverting bits / D1 to / D5 having the same polarity as the P-type transistors T1b (64) to T5b (64) are provided at the gates of the P-type transistors T1b (63) to T5b (63) connected between the N63b and the decode output node Nd1. Are input respectively.

Thereby, the P-type transistors T1b (64) to T5b (64) and T1b (63) to T5b (63), each gate being driven by the display signal bits (inverting bits / D1 to / D5) of the same polarity. Each path by is connected in parallel, and the electrical resistance between the gradation voltage nodes N63 and N64 and the decode output node Nd1 is reduced.

Although not shown, similarly provided in the decoding units corresponding to the other gradation voltages V1 to V62, a transistor group in which a gate is driven by display signal bits of the same polarity between adjacent decode units is parallel to the decode output node Nd1. It is assumed that intermediate connection nodes are electrically coupled to each other so as to be connected to each other.

By setting it as such a structure, the electrical resistance of the transfer path of a gray voltage can be reduced in the decoding circuit 71A, and the transfer time of a gray voltage can be shortened. As a result, in addition to the effect of the decode circuit according to the first embodiment, it is possible to shorten the time required for writing the display voltage to the pixel and achieve high speed operation.

In addition, in the structural example of FIG. 4, although the structure which connected all the path | routes by the transistor group in which a gate is driven by the display signal bit of the same polarity was shown, you may make it the structure which connects only a part of the said paths in parallel. For example, in Fig. 4, instead of between the connection nodes N64a and N63a, between the connection nodes of the N-type transistors T2a 64 and T3a 64 and between the connection nodes of the N-type transistors T2a 63 and T3a 63. It is good also as a structure which electrically couples.

5 is a circuit diagram showing a second configuration example of the decode circuit according to the second embodiment.

Referring to FIG. 5, the decoding circuit 71B according to the second configuration example of the second embodiment includes the display signal bits D2 to D5 that are higher when selected, in addition to the configuration of the decoding circuit 70 shown in FIG. 3. Between the decode units corresponding to the four gray voltages having the same level, the paths by the N-type transistors and the paths by the P-type transistors corresponding to the display signal bits D2 to D5 are connected in parallel to each other. Form a delivery path.

That is, the decode unit DU 61 corresponding to the gradation voltages V61 to V64 common to the display signal bits D2 to D5 at the time of selection to (D2, D3, D4, D5) = (1, 1, 1, 1), respectively. ) To DU 64, the connection node N64a # of the N-type transistors T1a 64 and T2a 64, the connection node N63a # of the N-type transistors T1a 63 and T2a 63, and the N-type transistor. The connection node N62a # of T1a 62 and T2a 62 and the connection node N61a # of N-type transistors T1a 61 and T2a 61 are electrically coupled to each other.

Similarly, the connection node N64b # of the P-type transistors T1b 64 and T2b 64, the connection node N63b # of the P-type transistors T1b 63 and T2b 63, and the P-type transistors T1b 62 and T2b ( The connection node N62b # of 62 and the connection node N61b # of the P-type transistors T1b 61 and T2b 61 are electrically coupled to each other.

Although not shown, similarly in the decoding units corresponding to the other gradation voltages V1 to V60, a transistor group in which the gate is driven by the display signal bits of the same polarity is arranged in parallel with respect to the decode output node Nd1 among four decode units. It is assumed that intermediate connection nodes are electrically connected to each other so as to be connected.

As a result, in the decode circuit 71B, the electrical resistance of the transfer path of the gradation voltage can be further reduced, and the time required for writing the display voltage to the pixel can be further shortened.

As described above, in the decode circuit according to the second embodiment, one of the connection nodes and the P-type transistors between the N-type transistors are connected in parallel in each of the decode units so that the transistor groups whose gates are driven by the display signal bits of the same polarity are connected in parallel. One of the connection nodes between is electrically coupled with a corresponding one of the connection nodes between the N-type transistors in the other at least one decode unit and a corresponding one of the connection nodes between the P-type transistors, respectively. That is, it is possible to set it as the structure which electrically couples the intermediate connection nodes between arbitrary number of decoding units, and reduces the electrical resistance of the transfer path of gradation voltage.

6 is a circuit diagram showing a third configuration example of the decode circuit according to the second embodiment.

Referring to FIG. 6, the decode circuit 71C according to the third configuration example of the second embodiment is similar to the decode circuit 71A shown in FIG. 4 in addition to the configuration of the decode circuit 71B shown in FIG. 5. The paths corresponding to the display signal bits D0 and D1 are connected in parallel between adjacent decode units having the same level of the display signal bits D0 and D1 at the time of selection.

In the decode units DU 64 and DU 63 representatively shown in FIG. 6, between the connection nodes N64a and N63a and between the connection nodes N64b and N63b are also electrically coupled. Similarly, in the decoding units DU 62 and DU 61, the connection nodes N62a and N61a and the connection nodes N62b and N61b are also electrically coupled. That is, in each decode unit, a plurality of intermediate connection nodes are electrically coupled with corresponding connection nodes in at least one other decode unit, respectively.

Although not shown, similarly in the decoding units corresponding to the other gradation voltages V1 to V60, a transistor group in which the gate is driven by the display signal bits of the same polarity is arranged in parallel with respect to the decode output node Nd1 among four decode units. The intermediate connection nodes are electrically connected to each other in a plurality of places such that the transistor groups in which the gates are driven by the display signal bits of the same polarity are connected in parallel between the two decode units, in parallel to the decode output node Nd1. It is to be combined.

As a result, the electric resistance of the path corresponding to the display signal bits D0 and D1 is reduced as compared with the decode circuit 71B shown in Fig. 5, so that the time required for writing the display voltage to the pixel can be further shortened. .

Third Embodiment

7 is a circuit diagram showing the configuration of the decode circuit 72 according to the third embodiment. Also in the configuration according to the third embodiment, in the liquid crystal display device 10 shown in FIG. 1, the decode circuit 70 is replaced only by the decode circuit 72, and the configuration of the other parts is the same.

Also in FIG. 7, only the configuration corresponding to the gradation voltage V64 in the portion corresponding to the decode output node Nd1 in the decode circuit 72 is representatively shown.

Referring to Fig. 7, the decode circuit 72 according to the third embodiment includes a current limiting element 75 connected between the power supply voltage Vdd and the control node / Ng 64, the power supply voltage Vdd and the control node Ng ( N-type transistors T0a (64) to T5a (64) connected in series between the current limiting device 76 connected between the 64, the control node / Ng 64, and the ground voltage Vss, and the control node Ng (64). ) And P-type transistors T0b (64) to T5b (64) connected in series between the power supply voltage Vdd and the gradation voltage transfer gate (77).

Like the decode circuit 70 shown in FIG. 3, display signal bits D0 to D5 are input to the gates of the N-type transistors T0a (64) to T5a (64), and the P-type transistors T0b (64) to T5b (64). Inverting bits / D0 to / D5 are input to each gate.

The gradation voltage transfer gate 77 has an N-type transistor 78a and a P-type transistor 78b connected in parallel between the gradation voltage node N64 and the decode output node Nd1. The gate of the N-type transistor 78a is connected to the control node Ng 64, and the gate of the P-type transistor 78b is connected to the control node / Ng 64.

When the gradation voltage V64 is selected, that is, when the display signal bits (D0, D1, D2, D3, D4, D5) = (1, 1, 1, 1, 1, 1), the N-type transistors T0a (64) to T5a. Each of 64 and the P-type transistors T0b 64 to T5b 64 is turned on, and the control nodes Ng 64 and / Ng 64 are driven to the power supply voltage Vdd and the ground voltage Vss, respectively. As a result, both the N-type transistor 78a and the P-type transistor 78b constituting the gradation voltage transfer gate 77 are turned on, and the gradation voltage V64 is transmitted to the decode output node Nd1.

On the other hand, when the gray voltage V64 is not selected, that is, when the display signal bits (D0, D1, D2, D3, D4, D5) ≠ (1, 1, 1, 1, 1, 1), the N-type transistor T0a (64). Since at least one of the &lt; RTI ID = 0.0 &gt; T5a &lt; / RTI &gt; 64 and at least one of the P-type transistors T0b (64) to T5b (64) are turned off, the control nodes Ng 64 and / Ng 64 are connected to the ground voltage Vss and the power supply voltage Vdd. Are each set to. As a result, since both the N-type transistor 78a and the P-type transistor 78b constituting the gradation voltage transfer gate 77 are turned off, the decode output node Nd1 and the gradation voltage node N64 (gradation voltage V64) are separated.

Similar configurations are formed for each of the gradation voltages V1 to V63, and correspond to the transistors T0a (j) to T5a (j) and the P-type transistors T0b (j) to corresponding to the gradation voltage Vj (an integer from 1 to 63). The display signal bits D1 to D5 or the inverting bits / D0 to / D5 for selecting the corresponding gray voltage Vj are input to the gates of each of the T5b (j). The gray voltage transfer gate 70 is connected between the gray voltage node Nj where the gray voltage Vj is generated and the decode output node Nd1.

Next, a configuration example of the current limiting elements 75 and 76 will be described.

Referring to FIG. 8, the current limiting element 75 is connected in series between the P-type transistor 79b connected between the power supply voltage Vdd and the control node / Ng 64 and the power supply voltage Vdd and the ground voltage Vss. P-type transistor 80b and resistance element 81b are provided. The connection node of the P-type transistor 80b and the resistance element 81b is connected to each gate of the P-type transistors 79b and 80b. The resistor element 81b can be formed of a thin film resistor, a channel resistance of a transistor, an impurity diffusion resistor, or the like.

Referring to FIG. 9, the current limiting device 76 includes an N-type transistor 79a connected between the ground voltage Vss and the control node Ng 64 and an N connected in series between the power supply voltage Vdd and the ground voltage Vss. It has a type transistor 80a and a resistance element 81a. The connection node of the N-type transistor 80a and the resistance element 81a is connected to each gate of the N-type transistors 79a and 80a. Similar to the resistor element 81b, the resistor element 81a can be formed of a thin film resistor, a channel resistor of a transistor, an impurity diffusion resistor, or the like.

Alternatively, as the current limiting elements 75 and 76 in Fig. 7, it is also possible to apply a constant current circuit such as a current mirror configuration.

As described above, in the decode circuit according to the third embodiment, since the number of transistors connected in series between the gradation voltage node and the decode output node is small, the electrical resistance of the transfer path of the gradation voltage can be further reduced. In addition, since the gray voltage transfer gate 77 is constituted by a pair of N-type transistors and P-type transistors, no voltage drop occurs in the gray voltage transfer gate 77. As a result, it is possible to suppress the influence of noise on the display voltage and to shorten the writing time of the display voltage on the pixel. In particular, compared with the decoding circuit shown in Fig. 9 of JP-A-2001-34234, the voltage drop of the display voltage (gradation voltage) can be suppressed without significantly increasing the number of arrangement of transistors.

Further, the P-type and N-type transistor groups constituting the decode circuits according to the third to third embodiments can be formed of TFT elements, similarly to the switch elements in the pixel 25. Thus, by shaping | molding drive circuit groups, such as a decoding circuit, on the same insulator substrate (glass substrate, resin substrate) as a pixel, miniaturization of a display apparatus is attained and cost reduction can be aimed at.

10 shows an example of the structure of a P-type TFT and an N-type TFT constituting a decode circuit according to the present invention.

Referring to FIG. 10, a P-type TFT is formed using a semiconductor film 95 formed on an insulator substrate 90, and source / drain regions 101 and 102 into which p-type impurities are implanted and a gate electrode ( 104 and electrodes 105 and 106 with electrical contacts secured to the source / drain regions 101 and 102, respectively. A gate insulating film 103 formed of SiO ₂ or the like is formed between the semiconductor film 95 and the gate electrode 104.

The N-type TFT is formed using a semiconductor film 95 such as polysilicon, and source / drain regions 151 and 152 into which n-type impurities are implanted, a gate electrode 154, and a source / drain region 151 , 152, electrodes 155 and 156 having electrical contacts, respectively, and a light-doped-drain (LDD) region 160. A gate insulating film 153 is formed between the semiconductor film 95 and the gate electrode 154 similarly to the P-type TFT. Since the drain electric field is relaxed by forming the LDD region 160, the breakdown voltage of the N-type TFT is improved.

The electrodes 105, 106, 155, and 156 corresponding to the source and drain are generally formed of aluminum or the like, and the gate electrodes 104 and 154 are formed of chromium or the like. In addition, since the TFT element of the structural example shown in FIG. 10 can be manufactured by the process similar to the TFT element which comprises a pixel, description is abbreviate | omitted about the detailed manufacturing method.

The presently disclosed embodiment is to be considered in all respects only as illustrative and not restrictive. The scope of the invention is defined not by the foregoing description but by the claims, and is intended to include any modifications within the meaning and range of equivalency of the claims.

As described above, in the present invention, in each transfer path of the gradation voltage in the decoding circuit which decodes the digital signal to generate the display voltage, field effect transistors of equal numbers of opposite conductivity types are connected in parallel. In addition, one of these counter-conducting field effect transistors is driven by receiving signals of opposite polarities to each other through a gate (control electrode). Therefore, between these counter-conducting field effect transistors, noises superimposed on the gray scale voltage through parasitic capacitance become reverse polarity with each other and cancel each other out. As a result, noise to the display voltage can be suppressed and the display accuracy can be improved.

In addition, by reducing the number of field effect transistors connected in series in each transfer path of the gray scale voltage in the decode circuit, and connecting the field effect transistors of opposite conductivity type in parallel, the electrical resistance of the transfer path and the corresponding The voltage drop in the transmission path can be reduced. As a result, it is possible to suppress the influence of noise on the display voltage and to shorten the writing time of the display voltage on the pixel. In particular, it is possible to suppress the voltage drop of the display voltage without significantly increasing the number of arrangement of the field effect transistor.

Claims (3)

A display device for performing gradation display in accordance with N bits (N: integer of 2 or more), A pixel for displaying luminance according to the applied display voltage; A gradation voltage generation circuit for generating stepped 2 ^N gradation voltages at each of the 2 ^N voltage nodes, A decode circuit for selecting one of the 2 ^N gray voltages according to the digital signal, and outputting the selected gray voltages to the output node as the display voltage; The decode circuit has 2 ^N decode units provided corresponding to the 2 ^N gray voltages, respectively. Each decode unit is N first field-effect transistors of a first conductivity type each corresponding to the N bits of the digital signal and connected in series between the output node and the voltage node corresponding thereto; Respectively corresponding to the N bits of the digital signal, and having N second field effect transistors of a second conductivity type connected in series between the output node and the corresponding voltage node, The first and second conductivity types are opposite conductivity types, One of the N first field-effect transistors and the N second field-effect transistors, each corresponding to the same bit of the digital signal, receives one of the same bit and its inverted bit to each control electrode. Display device. The method of claim 1, In each of the decode units, at least one first connection node of the (N-1) first connection nodes between the N first field effect transistors is the N first of at least one other decode unit. Is electrically coupled with the corresponding at least one first connection node of the (N-1) first connection nodes between the field effect transistors, One by one corresponding to the same bit of the digital signal in the first field-effect transistor connected to each other in parallel with the output node by electrical coupling of the at least one first connection node is the same bit. Or a display device receiving the inverting bits to the respective control electrodes with the same polarity. A display device for performing gradation display in accordance with N bits (N: integer of 2 or more), A pixel for displaying luminance according to the applied display voltage; A gradation voltage generation circuit for generating stepped 2 ^N gradation voltages at each of the 2 ^N voltage nodes, A decode circuit for selecting one of the 2 ^N gray voltages according to the digital signal, and outputting the selected gray voltages to the output node as the display voltage; The decode circuit has 2 ^N decode units provided corresponding to the 2 ^N gray voltages, respectively. Each decode unit is N first field effect transistors of a first conductivity type, respectively corresponding to the N bits of the digital signal, connected in series between a first control node electrically coupled with a first voltage and a second voltage; Wow, N second field-effect transistors of a second conductivity type respectively corresponding to the N bits of the digital signal and connected in series between the first control voltage and a second control node electrically coupled with the second voltage; , A third field effect transistor of the first conductivity type connected between the output node and the voltage node corresponding to the output node and having a control electrode connected to the second control node; A fourth field effect transistor of the second conductivity type connected between the output node and the corresponding voltage node and having a control electrode connected to the first control node, The first and second conductivity types are opposite conductivity types, One of the N first field-effect transistors and the N second field-effect transistors, each corresponding to the same bit of the digital signal, receives one of the same bit and its inverted bit to each control electrode. Display device.