TW200407822A - Display device - Google Patents

Abstract

An image display device being capable of gradation display and having a decode circuit with high noise resistance and small circuit area is provided, wherein a transmission route of each gradation voltage is parallelly connected with a serial route formed by 6 N-type transistors T0a to T5a and a serial route formed by 6 P-type transistors T0b to T5b within a decode circuit 70 of a display device, which performs gradation display by selecting gradation voltage of a plural of stages responding to display signal bits D0 to D5. Display signal bits D0 to D5 or their reverse bits are input into gates of the N-type transistors T0a to T5a. Display signal bits D0 to D5 or their reverse bits are input in a reversed polarity against N-type transistors T0a to T5a, respectively, into gates of the P-type transistors T0b to T5b.

Description

200407822 Main and invention description (1) Technical field to which the invention belongs] The present invention relates to a display device for text or video, and more particularly to a display device capable of performing hue display based on a digital signal. [Prior art] As display panels for personal computers, televisions, mobile phones, and personal digital assistants, display devices using liquid crystal elements and electroluminescence elements (EL elements) as display pixels are used. Compared with conventional display devices, this type of display device has considerable advantages in terms of lower power consumption and lighter weight. _ For pixels containing liquid crystal elements or EL elements, the display brightness is changed according to the level of the applied voltage (hereinafter, the applied voltage to the pixels is referred to as "display voltage"). Therefore, in such pixels, the hue display can be performed by setting the display voltage to a level setting corresponding to the intermediate brightness. Generally speaking, the structure of setting the display voltage after reflecting the decoding result of the digital signal of one bit for display brightness of display hue is used. Therefore, a display device capable of displaying hue must have a decoding circuit φ that decodes a digital signal and recognizes the specified hue and brightness. In general, since the decoding circuit must have a large number of solutions The use of transistor switches has made it a problem to reduce the circuit scale. In order to solve the foregoing problem, a structure of a so-called race-type decoding circuit as shown in Japanese Patent Application Laid-Open No. 2000-1-3 4 2 3 4 (shown in Figs. 8 and 9) is proposed. In this way, it is proposed that N bits are transmitted (N: an integer of 2 or more)

314403.ptd Page 6 200407822 V. Description of the invention (2) Digital signals are displayed 2 _ When the gradation of the gradation is 2 gradations, the nodes that generate 2 N gradation voltages and the nodes that generate the display voltage are set with a series N The structure of a decoding circuit of N-M0S (metal oxide semiconductor) transistors, and the structure of a decoding circuit that reduces the number of N-M0S transistors connected in series to the transmission path of the tone voltage. However, in the structure of the decoding circuit shown in Figure 8 of the aforementioned publication, although the area of the decoding circuit can be reduced in size, it is necessary to compensate for the voltage drop caused by the threshold voltage of the N-MOS transistor. Therefore, the gate voltage of the N-M0S transistor constituting the decoding circuit must be set at least at the threshold voltage level to the transmitted hue voltage. As a result, as the amplitude of the gate voltage increases, the amplitude of the noise obtained by passing the parasitic capacitance between the gate electrode and the source electrode or the drain electrode of the N-M0S transistor will also increase. There is a problem that the influence on the display voltage applied to the pixels is increased. Further, in the decoding circuit shown in Fig. 9 of the aforementioned publication, by reducing the number of N-MOS transistors included in the transmission path of the tone voltage, the voltage drop of the tone voltage can be suppressed. However, in contrast, since the number of transistors of the entire decoding circuit needs to be increased, there are problems in terms of circuit miniaturization and manufacturing yield. [Content] The present invention is an invention proposed in order to solve the foregoing problems, and an object of the present invention is to provide an image display device capable of displaying tones with a high noise immunity and a decoding circuit having a small circuit area.

314403.ptd Page 7 200407822 i. Description of the invention (3) r The display device according to the present invention is a display device that performs hue display based on a digital signal of N bits (N: an integer of 2 or more). There are pixels that display the brightness according to the applied display voltage, a tone voltage generating circuit that generates a level of 2 tone voltages to the 2 _ voltage nodes, and one of the 2 嗰 tone voltages is selected according to the digital signal, and the selected one is The tone voltage is output to a decoding circuit of an output node as a display voltage. The decoding circuit includes 2 _ decoding units that are respectively set to correspond to 2 嗰 tone voltages. Each decoding unit has N bits t corresponding to digital signals and is connected in series between the output node and the first Λ between the corresponding voltage nodes. : N first field-effect transistors of the type, corresponding to N-bit two of the digital signal, and connected in series between the output node and its corresponding voltage node < N second field-effects of the electrical type Type transistors, the first conductivity type and the second conductivity type are mutually opposite conductivity types. Among the N field-effect transistor and the N field-effect S transistor, they correspond to the digital signal Each one of the same bit-accepts one of the same bit and its opposite bit at each control electrode. The display device according to another aspect of the present invention is a display for performing hue display based on a digital signal of N bits (N: an integer of 2 or more). The display device is provided with: For example, a tone voltage generating circuit that generates a hierarchical tone voltage of 2 嗰 for a 2 嗰 voltage node, selects one of 2_tone voltages according to the digital signal, and outputs the selected tone voltage to the output node m as a display voltage for decoding. Circuit; the decoding circuit contains 2 _ tone voltages that correspond to 2 _ tone voltages, and 2 _ decoding units are provided; each decoding unit has a corresponding response

314403.ptd Page 8 200407822 V. Description of the invention (4) N bits of digital signal are connected in series between the first control node electrically connected to the first voltage and the first N conductive type between the second voltage The first field-effect transistor, corresponding to the N bits of the digital signal, is connected in series between the second control node electrically connected to the second voltage and the N second field-effects of the second conductivity type between the first voltage. Type transistor, field-effect transistor of the first conductivity type, and field-effect transistor of the first conductivity type connected between the output node and the corresponding voltage node and having a control electrode connected to the second control node, connected to the output node, and the corresponding voltage Field-effect transistors of the second conductivity type and the fourth conductivity type having control electrodes connected to the first control node between the nodes, the first conductivity type and the second conductivity type are mutually conductive conductivity types. The field-effect transistor and the N second field-effect transistors correspond to one of the same bit of the digital signal, respectively, and receive one of the same bit and its opposite bit at each control electrode. [Embodiment] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same symbols shown in the drawings represent the same or equivalent parts. (First Embodiment) Fig. 1 is a block diagram showing the entire configuration of a liquid crystal display device 10 described as a representative example of a display device according to an embodiment of the present invention. Referring to FIG. 1, a liquid crystal display device 10 according to an embodiment of the present invention includes a liquid crystal array section 20, a gate driver 30, and a source driver 40. The liquid crystal array section 20 includes a plurality of pixels arranged in a matrix.

314403.ptd page 9 200407822 i. Description of the invention (5) 2 5. The gate lines GL are arranged corresponding to the pixel rows (hereinafter referred to as “pixel rows”), and the data lines DL are respectively arranged corresponding to the pixel rows (hereinafter referred to as “pixel rows”). In the first figure, the pixels in the first and second rows of the first column, and the gate lines GL1 and data lines DL1 and DL2 corresponding to the pixels are used as a description. Each pixel 25 has a switching element 26 provided between the corresponding data line DL and the pixel node N p, and a sustaining capacitor 27 and a liquid crystal display connected in parallel between the pixel node N p and the common electrode node N c Not the component 2 8. Liquid crystal display element ^^ 2 The orientation of the liquid crystal in 8 will be changed according to the voltage difference between the pixel node Np and the common electrode node black Pn c. In response to this, the display brightness of the liquid crystal display element 28 will be changed. Accordingly, the brightness of each pixel can be controlled based on the display voltage transmitted to the pixel node Np via the data line DL and the switching element% Nu26. The switching element 26 can be composed of, for example, an N-type field effect transistor. -That is, the intermediate brightness can be obtained by applying an intermediate voltage difference between the voltage difference corresponding to the maximum brightness and the voltage difference corresponding to the minimum brightness to the pixel node N p and the common electrode N c. In other words, by setting the display voltage stepwise, the readability of hue can be obtained. " The gate driver 30 is to sequentially activate the gate lines according to a predetermined scanning period. The gate of the switching element 26 is connected to the corresponding gate line GL. Therefore, during the activation (Η level) of the corresponding gate line GL, the pixel node Nρ is connected to the corresponding data line DL. The on / off element 2 6 is generally formed in the same manner as the liquid crystal display element 2 8.

314403.ptd Page 10 200407822 V. Description of the invention (6) = edge body substrate (broken glass substrate, resin substrate)

Ugly). ^% TFT (Thin Film E

It is maintained by the holding capacitor 27 '] like "The power is displayed with the heart, then the image containing the el element shown in the second circle of V in Fig. 2 is replaced by τ < 彳 豕 $ 2 5. m can be replaced by Figure 2 of the second heart, like Xin 25: # 6 人 27 #, ELe, #, which contains the switching element 26, _ β? R, inferior piece 28 #, and the current-driven sun engraving Qn, and the holding capacitor 26, Same as in pixel 25: [动 电 日 日 体 29. Between the switching element prime node Np,: i 0 is placed in the corresponding data line DL holding capacitor 27 #, then 0 its car ^ = and Corresponding idle pole line GL is connected. 1 Display element 28 # is connected only by a single pixel, between the pixel Np and the voltage VDD. EL display vss ^ fBl 0 The crystal is composed of a melon-driving electric sun and limb 29, for example, P type The field-effect type electric word is similar to the EL display: the closing element 26 and the current-driving transistor 29. Generally, it is opened π? No 7 pieces 2 8 # are formed on the same insulator substrate.) During the period, the last 6 is at the corresponding gate. The epipolar line GL is activated (the display on the level line DL + the element 0 node Nρ is connected to the data line DL. Therefore, the data pressure is transmitted to the pixel node NP by the dimension = Ϊ pressure. The pixel node Np Electric current = Maintain. Corresponding pixel node N1 = 29, with gate connected to pixel node Np, EL display element 28 # current Iel is supplied to EIJf, display element 28 #. 1 e 1 is changed. The ratio is based on the display voltage of the current supplied and supplied. Even in pixels 2 5 #, it can be applied to the image in a hierarchical setting. The passive setting can increase the brightness of the EL display element.

Page 11 200407822 i. Description of the invention (7) As explained below, the present invention is directed to the peripheral circuits, especially the structure of decoding circuits, in a display device in which each pixel can display intermediate brightness according to the applied display voltage. Therefore, in the embodiment of the present invention described below, in a liquid crystal display device described as a representative example of a display device, a pixel 2 5 including a liquid crystal display element and a pixel 2 5 # including an EL element are replaced. In this case, it is possible to configure a display device according to the present invention in which display is performed by an EL element using a peripheral circuit having the same configuration. Referring to FIG. 1 again, the source driver 40 will output the display voltage D L that is set in stages through the display signal S I G of the N-bit digital 4 ^ tiger. Hereinafter, in the present embodiment, the case where N = 6, that is, the second, will be described. The configuration when the display signal S I G is composed of display signal bits D 0 to D 5 will be representatively described. According to the 6-bit display signal S I G, the hue display in the 2 I 6 4 stage can be performed in each pixel. In addition, if one color display unit is formed by each pixel of R (Red), G (Green), and B (B · 1 u e), approximately 260,000 colors of color display can be performed. The source driver 40 includes a shift register 50, a data latch g 5 2, 5 4, a tone voltage generating circuit 60, a decoding circuit 70, and an analog amplifier 80. The 1 display signal S I G is continuously generated corresponding to the display brightness of each pixel 25. In other words, the display signal bits D 0 to D 5 in each timing sequence represent the display brightness of one pixel 25 in the liquid crystal array section 20. • Shift register 50, which is a fixed switching time set with the display signal S I G. The timing of the synchronization cycle is used to indicate the data latch circuit 5 2 to display the display signal bits 1P 1111! 1 Έ111Ι

W 嶋 3] 4403.ptd Page 12 200407822 V. Description of the invention (8) Access to D0 to D5. The data latch circuit 5 2 sequentially takes in and maintains the display signal S I G of one pixel row generated continuously. The display signal group latched in the data latch circuit 5 2 is taken into the timing of the data latch circuit 5 2 with the display signal SIG of one pixel row, and is transmitted to the data latch circuit after responding to the activation of the latch signal LT. 5 4. The tone voltage generating circuit 60 is composed of 64 voltage-dividing resistors connected in series between the high voltage V Η and the low voltage VL, and generates 64 levels at the tone voltage nodes N 1 to N 6 4 respectively. Tone voltage VI to V 64. The decoding circuit 70 decodes the display signal latched to the data latch circuit 54, and selects the hue voltages V 1 to V 6 4 according to the decoding. The decoding circuit 70 generates the selected tone voltage (one of V 1 to V 6 4) as a display voltage at the decoding output node N d. In this embodiment, the decoding circuit 70 outputs a row of display voltages in parallel based on the display signal latched to the data latch circuit 54. In Fig. 1, the decoding output nodes Nd1 and Nd2 corresponding to the data lines DL1 and DL2 of the first and second rows are representatively described. The analog amplifier 8 0 outputs analog voltages corresponding to the display voltages output to the decoding output nodes N d 1, N d 2, ... to the data lines D L 1, D L 2, ..., respectively. In FIG. 1, although the gate driver 30 and the source driver 40 are integrally formed with the liquid crystal array unit 20 as an example, the structure of the liquid crystal display device 10 is described as an example. However, the gate driver For 30 and source driver 40, they can also be provided as external circuits of the liquid crystal array section 20. Next, the configuration of the decoding circuit will be described in detail.

1 1 in Η J;

3] 4403.ptd Page 13 200407822 V. Description of the invention (9) Figure 3 is a circuit diagram showing the first structure shown in Figure 1. The first figure of the decoding circuit of the known form of complaint is shown in FIG. 3, which corresponds to the portion of the decoded output node ^ = tonal voltages V64 and V63. As shown in FIG. 3, it is described in the first embodiment. Decoding circuit 70, spoon

Decoding unit DU (64) of Ui 2 modulation voltage V64, and corresponding: Decoding unit DU (6 3) of tone compression V 6 3

Mu solution: ^ element DU (64), which includes N-type field-effect transistors T〇a (64) to T5a connected in series between the hue voltage node N64 and the horse point Ndl (6f and 6f) The p-type field effect transistors TOb (64) to T5b (64) between the hue voltage node N64 and the decoding output node. Also, in the following, _ field-effect transistors and P-type field-effect transistors are only P-type transistor is used to name it. Including the Japanese-Japanese version of the ^ _ ^^-type transistor? 〇3 (64) to 53 (64) at the gate, input the display signal bits DO to D5. At the gates of the p-type transistors T0b (64) to T5b (6 4), input the inverted bits of the display signal bits D 0 to D 5 / ′ 0 to / 〇5, respectively. • Results, When the display signal bits (D0, M, D2, D3, D4, D5) = C1, 1, 1, 1, 1, 1), the N-type transistor T 0 a ( 6 4) to T 5 a (6 4) and p-type transistor τ 〇b (6 4) to T 5 b (6 4) will all be turned on. The tone voltage V 6 4 of the tone voltage node N 6 4 will be turned on. Pass to the decoding output node N d 1. Similarly, the decoding unit DU (63) contains a series connected to the tone voltage section

3] 4403.ptd Page 14 200407822 V. Description of the invention (10) N-type field effect transistors T0a (63) to T 5 a (6 3) between the point N63 and the decoding output node Ndl, and the hue voltage in series The node n 6 3 and the decoded output node "between 1? Type field-effect transistor D0] 3 (63) to 51) (63). The gate of the N-type transistor T0a (63) to T5a (63) At the pole, input the inverted bit of the hot page display signal bit D 0 / D 0 and the display signal bits d 0 to d 5. For this, the P-type transistor T 0 b (6 3) to T 5 At the gate of b (6 3), input display signal bits DO and display signal bits ^ to D5 reverse bits / to / D5 respectively. As a result, the display signal bits (D 0, d 2, D 3. D 4, D 5) = (〇, 卜卜卜卜 1), the calendar transistors T0a (63) to T5a (63) and p-type transistor T〇b ( 63) to T5b (63): Turn on, the hue voltage of node N63 is the code output node Ndl. N ^ J ^ Although it is not shown in the figure, the Dohu Dibe configuration has the same decoding structure. Units 22 to V62, also divided into units ⑽, IU, D2, D3, D4 'J) (.fi In addition: the state of the display signals 0, 0, n, n, n, and the hue voltage VI correspond to (D0, ni; = (bubbu i, buu state and color, household, D3 ' D4, D5) should show the increment of the signal bits DO to D5, corresponding to / U64 'and change every-stage. "Dagger, according to: color = pressure from V1 towards the voltage of V64 -Choose the tiger bit element to the mental energy, but it is not shown, but it is being solved; == The decoded output node code output node Nd is also configured with the same structure. 'For other solutions, as explained above In the first implementation

3] Decoding circuit described in 4403.ptd% state 〇

200407822 V. Description of the invention (11) In the transmission paths of the hue voltages V 1 to V 6 4, the same number of N-type transistors and P-type transistors are connected in parallel, and correspond to the display signal bit. Each of the N-type transistor and the P-type transistor of the same bit in the elements DO to D5 will be driven by the pole and the opposite bit of the same bit. Therefore, between the corresponding N-type transistor and P-type transistor, the noise superimposed on the tone voltage through the parasitic capacitance between the gate electrode and the source electrode or the drain electrode will become opposite polarities to each other. And offset. The conclusion k can suppress the noise on the display voltage, which is a problem on the decoding circuit in the conventional technology, and improve the accuracy of the display. (Second Embodiment) Fig. 4 is a circuit diagram of a first configuration example of the decoding circuit 7 1 A described in the second embodiment. In the configuration described in the second embodiment, only the decoding circuit 70 in the liquid crystal display device shown in FIG. 1 is replaced with a decoding circuit 7 1 A (7-1 B, 7 1 C). The constitutions are all the same. Referring to FIG. 4, the decoding circuit 7 1 A described in the first configuration example of the second embodiment is added to the configuration of the decoding circuit 70 shown in FIG. 3 between adjacent decoding units. Because of the common ownership of N-type transistor groups that support the corresponding display signal elements with the same polarity by the gates, one connection node of the N-type transistors will be electrically combined with each other. Similarly, between adjacently connected decoding units, because they share the path of P and transistor groups that will bear the corresponding display signal bits with the same polarity by the gate, these P-type transistors Link

! _P 1 ____ 111

Jlf page 16 314403.ptd 200407822 V. Description of the invention (12) The points will also be electrically combined with each other. For example, 'The connection node of Nadine la (64) in the decoding unit DU (64) ^ i Sun Moon beans TO a (64) and crystals T0a (63) and T1 (the second is decoding early element DU (63) The N-type electricity will be input to the remote ... N-type transistors between the decoding output nodes Ndl, and then point-and-closed, and connected to the connection node N6:: 1 stone; (. To 々, of Each of Satoshi's transistors Tla (63) to T5a (63) and 'one horse & exit point = between the crystals—T5a (64) two poles r: = Λη6: one to d 5, each gate T1 ^ Qi Each path formed by the electric βθ limbs Tla (64) to T5a (64) and section 2 N6 ifi5 ^ 63) is connected in parallel by the resistance f between the hue voltages N63, N64 and the decoding output node _ reduced by nb (m ' /, The? -Type transistor T0b (64) and the point b in the code unit DU (64) will be connected to the beans P-type transistor m (63) and Tlb (63) in the decoding unit DU (63). ) Two: two, Ϊ:; J ^ / D1 ^ / D5 ^ ^ ^ ^ f) Each gate of the P-type transistor 222 T5b (64) between the j node and the leg of the decoding output node is connected. Between the connection node and the corner at noon = :: knot = Ndl, every two of the P-type transistors nb (63) to T5b (63) 纟 =, will be Are input to the P-type transistor Tlb (64k T5b (64) of the same polarity reversed bit / D 1 to / D 5.

200407822 V. Description of the invention (13) A 'Through this, through the display signal bits (reverse bits / D1 to / D5) of the same polarity, each gate is driven separately. The p-type transistor is “all paths formed by the (64) and Tlb (63) to T5b (63) are connected in parallel, the resistance combination between the hue voltage nodes N63, N64 and the decoding output node Ndl is reduced. Η Although it is not shown in the figure, it is set in the same way even if it corresponds to the other tone voltage units V1 to Zima, and between the adjacent decoding decoding units, the display signal bits of the same polarity are used. The gate transistor is driven and the transistor group electrically couples the decoded output nodes Ndl to each other by connecting the nodes. '^ By using the aforementioned structure, in the decoding circuit 7 丨 A, the resistance of the transmission path of the low-tone voltage can be = As a result, the transmission time of the hue voltage is shortened. As a result, the effect of the decoding circuit described in the first embodiment can be shortened, and the time required to write the display voltage of the pixel can be shortened, and- The south speed is activated. ^ In the structure of FIG. 4, although it is illustrated that the ^ k bit of the same polarity is used to drive the closed-circuit driven transistor group to form all the paths. Mv will only use this part of the path. As a parallel configuration Also gr. For example, in Figure 4, in the connection node N64 difficult transistor T2a (64) and T3a (64) connection ~ machine /, U / 敝 twrqw ^-contact point, and N-type transistor T2a and T3a (63) can be connected between the + nodes of the connection. The structure of the gross connection is taken as an example. Figure 5 is the m + circuit diagram described in the second embodiment. The second configuration example of the decoding circuit

314403.ptd Page 18 200407822 V. Description of the invention (14) Referring to Fig. 5, the second embodiment of the shape bear 71 B, plus the decoding circuits described in the example of # 弗 2 shown in Fig. 3 correspond to When it is selected, its upper ^ 2 = the structure of path 7 0, and the decoding unit of the 4 tone voltages in common. The level of D2 to D5 is the N-type electric power of the bits D2 to D5. Crystal production: The paths corresponding to the display signal generation are connected in parallel, respectively, with the path of P & T and the P-type transistor, that is, the transmission path of selection = pressure. (D2, D3, D4, D5) = (1, Bu 'Bu': 5 tiger positions D2 to D5, which are the decoding units Du (^ at the tone voltages VI to V64, corresponding to the common transistor Tla ( 64) and T2a (64k, έ &) to DU (64), will _

ThrMh I ^ () Connection node N64a #, N-type electrical μ

The connection node N63a # of Tla (63) and T2a (63) = the connection node N of the sun body (62) and T2a (62). Lianyue (with the ground of wwiJ, the connection r of the P-type transistors Tlb (64) and T2b (64), the connection points P of the type transistors Tlb (63) and T2b (63), the point P is clear, and the p-type transistor Tlb (62) The N 6 2 b of * T2b (62), P-type Lei Yuelin / "shall be used to interoperate with each other 61) The decoding unit of the connection node V60 is not shown in Figure 3, but it corresponds to other tones Repeatedly VI to the gate order, M 4 also do the same setting, in every 4 solutions "generation one: f passes the display signal bit of the same polarity and the gate is affected by: the body group t pairs the decoding output node N d 〖In a parallel manner, the electric crystal nodes of ^ are electrically combined with each other. The connection between bamboo 1 ^, in the decoding circuit 7 1 B, the tone voltage can be lowered.

Page 19 3] 4403.ptd 5. Description of the invention (15) The resistance of the transmission path can shorten the time ^ ~. In order to write the display voltage of a pixel, it is necessary to write the display voltage in the second embodiment. In the second embodiment, the display signal of the same polarity is used in the noon code circuit / each decoding single crystal group is connected in parallel — the L element is turned on. Very driven by the Thai ^ is eight, the N-type thunder ^ and the P-type transistor between the sun and the body of the connection node ~ ~ in the decoding unit between the N-type transistor. Two, and at least one other The connection between the P-type transistor and Mingke +, and the corresponding node is t. In other words, one of the numbers f should be used as an electrical connection between the electrical nodes, which can form the middle two resistors between the noon code units. Fig. 6 is a circuit diagram of the transmission path for reducing the tone voltage. Fig. 6 is a circuit diagram according to the second embodiment. Refer to Figure 6 for the example of the 3rd brother of Jie Ma Lu Road, except for the second implementation path, 7 1 C, except for the addition of %% — the decoded code described in the example of the Xinle 3 configuration. The decoded code code shown in Figure 4 = ”B's composition is the same as that of elements D 0 and D 1.:, 'When selected, the display signal is located between the display signal bits D 0 and D 1 **, which corresponds to the decoding unit. In Figure 6, the ground connection is connected side by side. At (: 63), the connection node is further cleared, and the electrical connection is made between Du DU (64) and Du and N 6 3 b # Between moths 3 a and connected nodes N 6 4

Mum, more: ^ Similarly, between the decoding unit ⑽⑻) and between the N62b and N61b and the connection node-in the middle, a plurality of are connected. That is to say, at least one of the connected points in each solution unit is separately connected to one of the other units.

3] 4403.ptd Page 20 ___ ___Hidden

ZUU4U / 5ZZ 5. Description of the invention (16) Corresponding connection in the decoding unit # Although not shown, it is connected electrically. The decoding unit of V6 0 is also set to correspond to other tone voltages V 1 to V. The display signal of the same polarity is set to ground. In each group of 4 decoding units, the decoding output node N d tiger bit is set. The gate-driven transistor units are connected in parallel through the same polarity. In addition, every 2 decoded transistor groups will decode the output section s and the number of bits, and the gates are driven to connect to each other. Will be in a plurality of places = Nd 1 in parallel, the connection in the middle, and the solution shown in Figure 5 {electrical combination. Although it is lower than the circuit 7 1 of the display signal bits D 0 and D 1, the resistance of the display voltage to the pixel can be reduced from being reduced. Therefore, the time required for writing to the soil is further reduced (third embodiment) . Fig. 7 is a diagram of the third embodiment. In the decoding circuit 72 of the attack described in the third embodiment, the decoding circuit in the LCD circuit device 10 of the structure is also replaced with the same structure in the other parts shown in FIG. 1 only. It is a decoding circuit 72, which is also illustrated in FIG. 7 with the tone signal ^ 72 in the part of the decoding node Nd1 corresponding to the decoding output. < The representative structure corresponding to 6 4 is representative of the households, 、, and '7 Figures 弟 3 贯 施 形态 所 连接 ^ ^ connected to the power supply voltage Vdd and the control node 7 Zema circuit 2 7 with the components 7 5, connected to Current-limiting element limiting element 76 between ground voltage V s S and control ^ 6, N-type transistors T0a (64) to T5a (64) to current in series between control node / N = ^ Ng (64) 64), between the insect and the ground voltage Vss} in series with the control node Ng (64)

314403.ptd

200407822 i. Description of invention (17) and p-type transistors T0b (64) to T5b (64) between the power supply voltage Vdd and the hue voltage transfer gate 7 7. • Same as the decoding circuit 7 shown in FIG. 3, the display signal bit D 〇 is input to each of the gates of the n-type transistors T 0a (6 4) to T 5 a (6 4). To D 5 ′ At the respective gates of p-type transistors τ 〇 b (6 4) to τ 5 b (6 4), reverse bits / D 〇 to / d 5 are input respectively. The tone voltage transfer gate 7 7 has a refractory transistor 78 a and a p-type transistor 1 connected in parallel between the tone voltage node n 6 4 and the meridian code output node Ndl. The gate of the N-type transistor 78a is connected to the control node Ng (64), and the gate of the search body 7 ^ b is connected to the control node / Ng (64). When the tone voltage V 6 4 is selected, that is, the display signal bits (D 0, T 2, D 4, D 5) = (1, 1, i, i, Bu m, N-type transistor 2, 8, to T 5a (64) and all P-type transistors T0b (64) to T5b (64) i = ί, the control node Ng (64) and the control node / Ng (64) will respectively result in the voltage Vdd and the ground voltage, forming a hue electrical conduction Hue + Mao VR / ^ Sunri limb 78 iodine P-type transistor 78b will add j electricity [V64 will be passed to the decode output node μι. 4 IMil it \ When non-selection tone voltage V64, that is From: at least one of two, D2, D3, D4, _ (1, 1, 1, 1, and p-type transistor TObt two crystals Toa (64) to T5a (64) to control the section \ Ns (r4 ^ At least one of T5b (i4) will be disconnected. • Voltage vss and power supply voltage Vdd =:: (⑷ will be transmitted by grounding and one voltage to the N-type electric gate of the gate 77. As a result, due to the formation of color Both the electric solar limb 78a and the p-type transistor 78b will

The system is disconnected from 1 200407822 V. Invention Description (18), so the decoding output node Ndl and the tone voltage node N64 (tone voltage V 6 4) will be cut off. Although they have the same configuration, they are set for the tone voltages v 丨 to v6 3 respectively, so corresponding to the tone voltage V] · (] ·: integer from 1 to 63) _ transistors T0a (j) to T5a (j ) And the P-type transistors T0b (j) to T5b (j), one of the gates will be input to select the corresponding hue voltage v] · The display signal bit °-D1 to D5 or its reverse bit / D0 Go to / D5. The tone voltage transfer gate may be connected to the tone voltage node. The tone voltage node is called between; and the point Ndl. 'Come out next' describes the configuration example of the current limiting elements 7 5 and 76. Referring to FIG. 8, The current limiting element 75 includes a p-type transistor 79b connected between Vdd and the control node / Ng (64), a p-type transistor 80b between the voltage Vdd and the ground voltage Vss, and: Power supply 81b. Connection of P-type transistor 80b and resistor element 81b. Rabbit-resistor-type transistor 79b is connected to each gate of 80b. Resistor element 8 ^ is connected to P resistor, channel resistance of transistor or impurity Diffusion current: According to Fig. 9, the current limiting element 76 has a _transistor 79a connected between the control node Ng (64) and a string _transistor between ground voltage ^ and ground voltage Vss 80a and ^ in the power supply, the connection node of the transistor core and the resistance element 兔 are connected to the gates of the electric resistance body 79a and 80a. The resistance ... u Similarly, it can be made of thin film: resistance two or疋 Impurity diffusion resistance etc. are formed.

iii! llflmm 23rd stomach 200407822 V. Description of the invention (19) Alternatively, a constant current circuit composed of a current mirror (cu r r n t m i r r 〇 r), etc., can also be used as the current limiting elements 7 5 and 7 6 in FIG. As described above, in the decoding circuit according to the third embodiment, since the number of transistors connected in series between the tone voltage node and the decoding output node is smaller, f, the resistance of the transmission path of the tone voltage can be further reduced. In addition, since the tone voltage transfer gate 7 7 is composed of a pair of N-type transistors and P-type transistors, the voltage does not drop at the tone voltage transfer gates 7 7. As a result, it is possible to suppress the influence of noise on the display voltage and reduce the write time of the display voltage to the pixels. In particular, compared with the decoding circuit described in Japanese Patent Application Laid-Open No. 2000-1-3¾ 3 4 shown in Fig. 9, the number of transistor configurations will not increase significantly, and the display voltage (tone voltage) can be suppressed. The voltage drops. In addition, the P-type and N-type transistor groups constituting the decoding circuits described in the first to third embodiments can be formed of .TFT elements in the same manner as the switching elements in the pixels 25. In this way, by forming a driving circuit group such as a decoding circuit on the same insulator substrate (glass substrate, resin substrate) as the pixel, miniaturization of the display device becomes possible and cost reduction can be achieved.

Fig. 10 shows a structure example of a P-type TFT and a TFT constituting a decoding circuit according to the present invention. Referring to FIG. 10, a P-type TFT is formed by using a semiconductor thin film 95 formed on an insulator substrate 90, and has source / drain regions 1 0 1, 1 2 and gates implanted with P-type impurities. Electrodes 1 0 4 and electrodes 1 0 5 and 1 6 which are electrically connected to the source / lower electrode regions 101 and 10 2 respectively. Semiconductor film

314403.pld Page 24 200407822 V. Description of the invention (20) 9 5 A gate insulating film 103 formed by stone dioxide and the like is provided between the gate electrode 10 and the gate electrode 104. The N-type TFT is formed using a semiconductor thin film 95 such as polycrystalline silicon, and has a source / drain region 1 5 1, 1 5 2, a gate electrode 1 5 4 that is implanted with N-type impurities, and a source / drain region. The electrode regions 1 51 and 1 2 are electrically connected electrodes 155 and 156, respectively, and the light-doped-drain (LDD) micro-doped non-electrode region 160 is used. Between the semiconductor thin film 95 and the gate electrode 154, a gate insulating film 153 similar to that of the PS TFT is provided. By setting the LDD field 1 60, the non-polar electric field will be relaxed, so the pressure resistance of N-type T F T will be improved. The electrodes 105, 106, 155, and 156 corresponding to the source and anode electrodes are generally formed by Ming et al., And the gate electrodes 104, 154 are formed by chromium or the like. The T F T element in the structural example shown in FIG. 10 can be manufactured by the same process as that of the TFT element constituting the pixel. Therefore, detailed description of the manufacturing method is omitted. All aspects of the embodiments described in the present invention are exemplary and not restrictive. The scope of the present invention is not the above description but the details of the scope of patent application. It has the same meaning as the scope of patent application and its Any changes within the scope are included. As explained above, in the present invention, on the respective transmission paths of the hue voltage in the decoding circuit that decodes the digital signal and generates a display voltage, the same field-effect type of the opposite conductive type is connected in parallel with each other. Crystal. In addition, each of the aforementioned field-effect transistors of the opposite conductivity type will receive signals of opposite polarity from each other by being driven by the gate (control electrode). Therefore, between these field-effect transistors of the opposite conductivity type,

314403.ptd Page 25 200407822 V. Description of the invention (21) Noises that are superimposed on the hue voltage due to parasitic capacitance will become opposite polarities to each other and will be offset. As a result, it is possible to suppress noise with respect to the display voltage and improve display accuracy. In addition, among the transmission paths of the tone voltage in the decoding circuit, the number of field-effect transistors in series_ is small, and by connecting field-effect transistors of opposite conductivity types in parallel, it is possible to reduce The resistance of its transmission path and the voltage across its transmission path decrease. As a result, it is possible to suppress the influence of noise on the display voltage and shorten the writing time of the display voltage to the pixels. In particular, the number of field effect transistors is not significantly increased, which is enough to suppress the voltage drop of the display voltage.

314403.ptd Page 26 200407822 Brief description of drawings [Simplified description of drawings] Fig. 1 is a block diagram illustrating the overall configuration of a liquid crystal display device 10 as a representative example of a display device according to an embodiment of the present invention. Fig. 2 is a circuit diagram of a pixel configuration example including an EL element. Fig. 3 is a circuit diagram showing the structure of the decoding circuit described in the first embodiment. Fig. 4 is a circuit diagram of a first configuration example of the decoding circuit described in the second embodiment. Fig. 5 is a circuit diagram of a second configuration example of the decoding circuit described in the second embodiment. Fig. 6 is a circuit diagram of a third configuration example of the decoding circuit described in the second embodiment. Fig. 7 is a circuit diagram showing the structure of the decoding circuit described in the third embodiment. Fig. 8 is a circuit diagram showing an example of the configuration of the resistor shown in Fig. 7. Fig. 9 is a circuit diagram showing an example of the configuration of the resistor shown in Fig. 7. Fig. 10 is a structural diagram showing a configuration example of a P-type TFT and an N-type TFT constituting the decoding circuit according to the present invention. 10 liquid crystal display device 20 liquid crystal array unit 25 pixels 26 switching elements 27-dimensional holding capacitor 28 liquid crystal display element 29 current driving transistor 30 gate driver 40 source horse driver 50 shift register

314403.ptd Page 27 200407822 Simple explanation of the formula 5 2, 5 4 Data asking circuit 70, 71, 71 #, 72 decoding circuit 色调 Tone voltage transfer gate 90 Insulator substrate • 101, 102, 151, 152 Drain region 1 0 4, 1 5 4 Gate electrodes D 0 to D 5 Display signal bits DL, DL 1, DL 2 Data line 60 tone voltage produces electrical failure 75, 76 current limit_ $ 路 8 0 Analog magnification ^ 9 5 Semiconductor thin_ 1 0 3, 1 5 3 Gate insulation film 105, 106, 155, / D0 to / D5 reverse bit electrodes E ^ (61) to DU (64), DU decoding unit G · GL1 gate, wire Hidden N64 tone voltage "N * 61a #, N61b #, N62a #, N62b #, N63a, N63b, N63a #, N63b #, N64a, N64b, N64a #, N64b # connection node M, Ndl decoding output node Nc common electrode node

Ng (64) / Ng (64) control node Np pixel node ... SIG green no signal T0a (j) to T5a (j), 78a, 79a, 8 0a N-type transistor (j: natural number tObU) to T5b (j ), 78b, 79b, 8 0b P-type transistors (j: Since = several Vg V64 hue voltage ^

314403.ptd Page 28

Claims (1)

200407822 VI. Patent application scope 1 · A display device that performs hue display based on digital signals of N bits (N: an integer of 2 or more), including: pixels that display brightness according to the applied display voltage, and 2 _ The voltage node generates a hierarchical 2_tone voltage tone voltage generating circuit, and selects one of the 2_tone voltages according to the aforementioned digital signal, and outputs the selected tone voltage as a display voltage to the output node for decoding. The decoding circuit includes a 2 _ decoding unit corresponding to the 2 _ tone voltage set; each of the decoding units has the N bits corresponding to the digital signal, and is connected in series to the output node and The N first field-effect transistors of the first conductivity type corresponding to the aforementioned voltage nodes correspond to the aforementioned N bits of the aforementioned digital signals, respectively, and are connected in series to the aforementioned output node and the corresponding aforementioned voltage node N second field-effect transistors of the second conductivity type; the first conductivity type and the second conductivity type The conductive types are opposite to each other. Among the N first field-effect transistors and the N second field-effect transistors, each corresponding to the same bit of the digital signal is connected to each control electrode. It accepts each of the aforementioned bits and their opposite bits. 2. The display device according to item 1 of the scope of patent application, wherein: in each of the foregoing decoding units, at least one of the (N-1) first connection nodes among the aforementioned N first field effect transistors is The 1 connection node is connected to at least one of the aforementioned N first field-effect transistors in the aforementioned decoding unit. 314403.ptd Page 29 200407822 • Sixth, the scope of patent application · (N-1) The first connection node corresponding to at least one of the first connection nodes is electrically connected; through at least one of the aforementioned first connection nodes Each of the first field-effect transistors in the first field-effect transistor in parallel with each other connected to the output node in parallel with each other corresponds to the same bit or a reverse bit of the same bit Each control electrode is received with the same polarity. 3. For the display device in the second item of the scope of patent application, wherein: in each of the foregoing decoding units, the plurality of first connection nodes are corresponding to the corresponding first of the at least one other foregoing decoding unit. 1 Connect the nodes for electrical connection. 4. The display device according to item 2 of the scope of patent application, wherein: in each of the foregoing decoding units, at least one of the (N-1) second connection nodes among the aforementioned N second field effect transistors is The 2 connection nodes are electrically connected to at least one second connection node corresponding to the (N-1) second connection node between the aforementioned fixed second field-effect transistors in at least one other aforementioned decoding unit. Connection; each of the same bit corresponding to the aforementioned digital signal in the aforementioned second field-effect transistor in parallel with each other through the aforementioned at least one second connection node's electrical connection with each other in parallel to the aforementioned output node, The same bit or its inverse bit is received by each control electrode under the same polarity. .5. The display device according to item 4 of the scope of patent application, wherein: in each of the foregoing decoding units, a plurality of each of the foregoing first connection node and second connection section 314403.ptd Page 30 200407822 6. The scope of the patent application point is that the first connection node and the second connection node corresponding to at least one of the other aforementioned decoding units are electrically connected respectively. 6. The display device according to item 1 of the scope of patent application, wherein each of the aforementioned first field-effect transistors and each of the aforementioned second field-effect transistors are composed of thin-film transistors. 7. The display device according to item 6 of the scope of patent application, wherein: the aforementioned pixel is a display element having a brightness according to the pixel node voltage, and is connected between a node that is transmitted with a voltage responded by the aforementioned display voltage and the aforementioned pixel node A switching element composed of a thin film transistor that reacts to a predetermined scanning period and is turned on; the switching element, each of the first field-effect transistor and each of the second field-effect transistor are formed in On the same insulator substrate. 8. The display device according to item 6 of the scope of patent application, wherein: the aforementioned pixels have a display element that displays brightness according to the supplied passing current, a node connected to the node that is transmitted with a voltage responded by the aforementioned display voltage, and the aforementioned pixel The nodes respond to a predetermined scanning period and are turned on. A switching element composed of a thin film transistor, a voltage maintaining element that maintains the pixel node voltage, and a current that is supplied to the pixel element according to the pixel node voltage, A current driving element composed of a thin film transistor, and the switching element, the current driving element, each of the first field-effect transistor and each of the second field-effect transistor are formed on the same insulator substrate. 9 · A display device based on digital signals of N bits (N: an integer of 2 or more) 3] 4403.ptd Page 31 200407822 6. Applying patents to perform hue display, including: displaying brightness pixels according to the applied display voltage, and generating 2 _ hue voltages for each 2 _ voltage node to generate a hue voltage The generating circuit selects one of the 2_tone voltages according to the digital signal, and outputs the selected tone voltage as a display voltage to a decoding node of an output node; wherein the decoding circuit includes a corresponding circuit corresponding to the 2 嗰2_decoding unit provided by the hue voltage; each of the aforementioned decoding units has the aforementioned N bits corresponding to the aforementioned digital signal, respectively, and is connected in series to the first control node and the first voltage which are electrically connected to the first voltage. The N first field-effect transistors of the first conductivity type between 2 voltages respectively correspond to the aforementioned N bits of the digital signal, and are connected in series to the second control node electrically connected to the aforementioned second voltage and the aforementioned N second field-effect transistors of the second conductivity type between the first voltage are connected between the foregoing output node and the corresponding voltage node, and The first conductive type-the third field-effect transistor having the control electrode connected to the second control node is connected between the output node and the corresponding voltage node, and has the first control node. The fourth field-effect transistor of the aforementioned second conductivity type of the connected control electrode; ^ The first conductivity type and the second conductivity type are mutually opposite conductivity types, and the N first field-effect transistors and the aforementioned Among the N second field-effect transistors, one corresponding to the same bit of the aforementioned digital signal, respectively, receives one of the aforementioned same bit and its inverse bit at each control electrode. 314403.ptd Page 32 200407822 VI. Application for patent scope 10. For the display device with scope of patent application No. 9, in which each of the aforementioned decoding elements has a first connection between the aforementioned first voltage and the aforementioned first control node. 1 Current limiting element, a second current limiting element connected between the second voltage and the second control node.如 The display device according to item 9 of the scope of patent application, wherein: each of the aforementioned first field-effect transistor, each of the aforementioned second-field transistor, the aforementioned third-field transistor, and the aforementioned fourth-field transistor The transistors are all composed of thin film transistors. 12. The display device according to item 11 of the scope of patent application, wherein the aforementioned pixels are display elements having a brightness according to the pixel node voltage, connected to a node that is transmitted with a voltage responded to according to the aforementioned display voltage, and the aforementioned pixel node In between, a switching element composed of a thin-film transistor that reacts to a predetermined scanning period and is turned on; and the switching element, each of the first field-effect transistor, each of the second field-effect transistor, The third field-effect transistor and the fourth field-effect transistor are formed on the same insulator substrate. 1 3. The display device according to item 11 of the scope of patent application, wherein the aforementioned pixels are display elements having a brightness according to a current flow, connected to a node that is transmitted with a voltage responded by the aforementioned display voltage, and the aforementioned pixel node In response to a predetermined scanning period, the switching element is composed of a thin film transistor, a voltage maintaining element that maintains the aforementioned pixel node voltage, and a current based on the aforementioned pixel node voltage is supplied to the aforementioned pixel element. An electric driving device composed of a thin film transistor, 314403.ptd Page 33 200407822 6. Scope of Patent Application-The aforementioned switching element, the aforementioned current driving element, each of the aforementioned first field effect transistor, each of the aforementioned second field effect transistor, and the aforementioned third field effect transistor It is formed on the same insulator substrate as the aforementioned fourth field effect transistor. 314403.pld Page 34