JPH1164825A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To rationalize mounting by reducing the scale of a horizontal driving circuit provided in a display device. SOLUTION: This display device is composed of a pixel array part 1 a vertical driving circuit 2 and a horizontal driving circuit 3. The pixel array part 1 has the rows and columns of mutually crossing scanning lines X and signal lines Y and pixels PXL arranged at the intersectional parts of both the lines. The vertical driving circuit 2 is connected to the respective scanning lines X and selects the pixels PXL for one row successively. The horizontal driving circuit 3 is connected to the respective signal lines Y, generates a signal voltage made into multigradations based on digital image data composed of multibits and writes the signal voltage in the selected pixels PXL for one row. The horizontal driving circuit 3 is provided with a multigradation circuit 34 serially connecting three stages of voltage modulating parts 35, 36 and 37. The fore stage voltage modulating part 35 performs primary gradation corresponding to bit data on the side of high-order digits. The middle stage voltage modulating part 36 performs secondary gradation corresponding to the bit data on the side of middle-order digits. The rear stage voltage modulating part 37 performs tertiary gradation corresponding to bit data on the side of low-order digits.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a display device.
More specifically, the present invention relates to a display device integration technology capable of expressing gradation based on digital image data.

[0002]

2. Description of the Related Art An example of a conventional display device will be briefly described with reference to FIG. The display device is a panel 1 that constitutes a screen.
10 and peripheral vertical drive circuit 120, horizontal drive circuit 13
0 and a timing generation circuit 140. The panel 110 is composed of, for example, an active matrix type liquid crystal display (LCD) using an amorphous silicon thin film transistor as a switching element. The panel is not limited to this, but may be a plasma display (PD).
P) and electroluminescent display (EL)
Can be used. The peripheral vertical drive circuit 120, horizontal drive circuit 130, and timing generation circuit 140 are composed of external LSIs. In a conventional display device, a panel and a peripheral circuit are separate bodies, and both are electrically connected by TAB or the like.

The panel 110 has scanning lines X and signal lines Y intersecting each other. Pixels PXL are formed at intersections of the row-shaped scanning lines X and the column-shaped signal lines Y. The pixel PXL includes a pixel electrode and a counter electrode COM facing the pixel electrode, and an electro-optical material such as a liquid crystal is held between the two electrodes. Each pixel PXL is driven by a thin film transistor Tr having amorphous silicon as an active layer. The drain electrode of the thin film transistor Tr is connected to the corresponding pixel PXL, the source electrode is connected to the corresponding signal line Y, and the gate electrode is connected to the corresponding scanning line X. The vertical drive circuit 120 is a vertical shift register circuit 1
21 and an output buffer circuit 122. The vertical shift register circuit 121 is connected to each scanning line X via an output buffer circuit 122, and sequentially selects one row of pixels PXL. The horizontal drive circuit 130 is an LSI in which a horizontal shift register circuit 131, a line memory circuit 132, a level conversion circuit 133, and a digital / analog conversion circuit 134 are integrated. This horizontal drive circuit 130 is connected to each signal line Y
And generates a signal voltage of multi-gradation based on digital image data of a multi-bit configuration, and writes the signal voltage to the selected one row of pixels PXL. The signal voltage is generated by modulating a reference voltage based on digital image data. The timing generation circuit 140 controls the synchronization between the vertical drive circuit 120 and the horizontal drive circuit 130.

FIG. 12 shows a specific configuration example of the horizontal drive circuit 130. The horizontal drive circuit includes a horizontal shift register circuit 131, an input line Z, a sampling switch SW,
It comprises a level conversion circuit 133, a line memory circuit 132, a digital / analog conversion circuit 134 and the like.
The horizontal shift register circuit 131 operates according to the timing signal supplied from the timing generation circuit 140 shown in FIG. 11, and controls opening and closing of a set of six sampling switches SW. Thereby, the digital image data D0 to D5 in the 6-bit parallel configuration supplied from the outside via the input line Z are sampled. The sampled digital image data is collectively stored in the line memory circuit 132 via the level conversion circuit 133 for one line. Batch latching of digital image data to the line memory circuit 132 is controlled by a timing signal supplied from the timing generation circuit 140 shown in FIG. The digital-to-analog conversion circuit 134 includes a decoder circuit and an analog switch. The digital-to-analog conversion circuit 134 decodes the digital image data stored in the line memory circuit 132 and generates a signal voltage assigned to each pixel PXL. The generated signal voltage is output to the corresponding signal line Y. The conventional digital-to-analog conversion circuit 134 selects one of the reference voltages V1 to V64 of 64 gradations supplied from the outside on the basis of the result of decoding the digital image data of the 6-bit parallel configuration, and the corresponding signal line Y To supply. In this conventional example, since 6-bit parallel digital image data is used, the reference voltage requires 2 ⁶ = 64 gradation levels. When digital image data of an 8-bit parallel configuration is used,
The gradation level of the reference voltage is 2 ⁸ = 256. Note that the arrangement of the level conversion circuit 133 and the line memory circuit 132 can be switched as shown in FIG.

FIG. 13 shows a specific configuration example of the digital-to-analog conversion circuit 134 shown in FIG. 12, in which only a portion corresponding to one signal line Y is shown. As shown in the figure, the digital-to-analog conversion circuit 134 includes a series connection of reference voltage selection circuits 135-1 to 135-256. When the digital image data has an 8-bit parallel configuration including D0 to D7, the reference voltage selection circuit 135
-1 to 135-256 require 2 ⁸ = 256, and if these are integrated into one chip, a large-scale IC (LSI) will result. Each reference voltage selection circuit includes, for example, a decoder circuit, an inverter, and a transistor. The specific configuration is, for example, SAITO, K .; KI
TAMURA, etc, NEC "A 6-bit Di
digital Data Driver for Col
or TFT-LCDs ", pp257-260, SI
D 95 digest, 1995.
In this conventional example, a reference voltage is used to generate a signal voltage. The reference voltage is toned by resistance division. In this method, for example, when writing digital image data of a 6-bit parallel configuration to one signal line,
For resistance division, 2 ⁶ = 64 resistance elements are required. Further, a ROM decoder is used to select a gradation level corresponding to digital image data. This is a transistor matrix array of 64 gradations × 6 bits. If C-MOS switches are arranged in each lattice of the matrix, the number of all transistors is 64 × 6 × 2 = 768, and high integration of the reference voltage selection circuit is essential. Further, if the gradation is further increased using digital image data having an 8-bit parallel configuration, the scale of the ROM decoder becomes enormous.

[0006]

In the conventional example shown in FIG. 11, the panel 110 is an active matrix LCD using thin film transistors using amorphous silicon as an active layer. Amorphous silicon thin film transistors have relatively poor operating characteristics and can be used as switching elements for driving pixels, but are insufficient for configuring peripheral circuit portions. Therefore, in the conventional display device, the panel 110
The vertical drive circuit 120 and the horizontal drive circuit 130 are formed separately from the LSI, and are connected to the panel 110.

On the other hand, in recent years, an active matrix type LCD using a thin film transistor having polycrystalline silicon as an active layer as a switching element has been developed.
Since a polycrystalline silicon thin film transistor has better operation characteristics than an amorphous silicon thin film transistor, a peripheral circuit in addition to a switching element for driving a pixel can be formed on the same insulating substrate. However, in the conventional display device configuration shown in FIG. 11, the scale of the horizontal drive circuit is enormous, which hinders the incorporation or integration into the panel. Specifically, when the horizontal drive circuit is built in the panel, its occupied area increases, and the size of the entire panel increases. The occupied area of the pixel array portion (screen) in the entire panel becomes relatively small, and the commercial value is significantly impaired.

In the conventional reference voltage selection method, as the number of bits of digital image data increases, the number of gradation levels of the reference voltage input from the outside increases, and the number of wirings increases accordingly. Therefore, even if the horizontal drive circuit is built in the panel, a wiring operation for inputting the reference voltage is still required, and the yield is deteriorated. Furthermore, as the panel area increases, the parasitic capacitance inside the digital-to-analog conversion circuit increases, causing a signal transmission delay inside the panel.
For this reason, high-speed response is impaired, and it becomes difficult to drive at high frequency.

In incorporating a horizontal drive circuit into a panel,
It is essential to reduce the circuit scale. In this regard,
The configuration of an improved horizontal drive circuit is disclosed in, for example,
No. 9392. This display device converts a panel provided with a plurality of parallel signal lines and input digital image data into any of a plurality of levels of signal voltages, and sends the signal voltages obtained by this conversion to each signal line. A horizontal drive circuit. Here, it is possible to generate a halftone signal voltage that does not correspond to any of a plurality of levels of reference voltages given in advance. Specifically, in order to generate a halftone signal voltage, a pair of adjacent reference voltages are averaged for each field. That is,
A desired signal voltage is generated through a pre-stage process of selecting a reference voltage and a post-stage process of averaging the selected reference voltage. In other words, sparse gradation is performed in the first step, and dense gradation is performed in the second step. In this manner, by dividing the gradation into two stages, the number of decoders required for this can be reduced. When digital image data of an 8-bit parallel configuration is used, the number of decoders required without stepwise gradation is 2 ⁸ = 256 per signal line as described above. When this is divided into two stages to perform coarse gradation and dense gradation, for example, 2 ⁴ +2 ⁴
= 16 + 16 = 32 decoders. However, 32 decoders per signal line are still required. Still, in order to integrate or incorporate the horizontal drive circuit into the panel, the circuit scale must be reduced, which is a problem to be solved.

[0010]

Means for Solving the Problems In order to solve the above-mentioned problems of the prior art, the following measures have been taken. That is, the display device according to the present invention includes, as a basic configuration, a row of scanning lines and a column of signal lines that intersect each other, a pixel disposed at the intersection of the two, a vertical driving circuit, and a horizontal driving circuit. Have. The vertical drive circuit is connected to each scanning line and sequentially selects one row of pixels. The horizontal drive circuit is connected to each signal line,
A multi-gradation signal voltage is generated based on multi-bit digital image data, and the signal voltage is written to the selected one row of pixels. As a characteristic feature, the horizontal drive circuit includes at least a preceding-stage voltage modulation unit that performs primary gradation according to bit data of an upper digit included in a multi-bit configuration, and a middle-order digit modulation unit also included in a multi-bit configuration. A voltage modulator in the middle stage that performs secondary gradation according to the bit data on the side;
There is also provided a multi-gradation circuit in which a voltage modulating section at the subsequent stage for performing tertiary gradation in accordance with lower-order bit data included in the multi-bit configuration is connected in series.

Preferably, in the multi-gradation circuit, at least one of the voltage modulating units in each stage is of a resistance division type for extracting a voltage corresponding to the bit data from a plurality of resistance-divided voltages. Alternatively, the multi-gradation circuit is of a gate voltage modulation type in which at least one of the voltage modulation units in each stage performs gradation by using an analog gate element whose impedance changes according to the gate voltage. Alternatively, in the multi-gradation circuit, at least one of the voltage modulation units in each stage is
It is a gate pulse modulation type that performs gradation by using an analog gate element that opens and closes according to the duty ratio of the gate pulse. Alternatively, the multi-gradation circuit is of a voltage selection type in which at least one of the voltage modulation units of each stage selects a voltage corresponding to the bit data from a plurality of levels of voltages input in advance to perform gradation. is there.

Preferably, the pixel has a thin film transistor formed on an insulating substrate and connected to the scanning line and the signal line, and a pixel electrode to which a signal voltage is written via the thin film transistor. In this case, the vertical drive circuit and the horizontal drive circuit are also constituted by thin film transistors integrated on the same insulating substrate.

According to another aspect of the present invention, a display device according to the present invention includes, as a basic configuration, a row of scanning lines and a column of signal lines that intersect each other, and a pixel disposed at an intersection of the two. A vertical drive circuit connected to each scanning line and sequentially selecting one row of pixels, and a multi-gradation signal voltage generated based on multi-bit digital image data connected to each signal line And a horizontal drive circuit for writing the signal voltage to the selected one row of pixels. The horizontal drive circuit includes at least a preceding-stage voltage modulation unit that performs primary gradation according to upper-order bit data included in the multi-bit configuration, and a lower-order bit data that is also included in the multi-bit configuration. And a multi-gray scale circuit in which a voltage modulating section at the subsequent stage for performing secondary gray scale and outputting a signal voltage is connected in series. The voltage modulator in the preceding stage includes a pair of analog switch elements that output a pair of reference voltages selected according to bit data. As a characteristic feature, the voltage modulator at the subsequent stage includes a plurality of resistance elements connected in series between the pair of analog switch elements, and constitutes a voltage dividing circuit including the pair of analog elements as a resistance component. . The voltage modulator at the subsequent stage takes out the divided voltage from the voltage dividing circuit according to the bit data and outputs a signal voltage. Preferably, the resistance value of each resistance element is set to be twice or more the resistance value when the analog switch element is in a conductive state. Preferably, the plurality of resistance elements have the same resistance value as each other, and the number of resistance elements smaller by one than the number of gradations of the secondary gradation is connected in series between the pair of analog switch elements. I have.

According to the present invention, the voltage modulation section is connected in series at least in three stages of front, middle, and rear to constitute a multi-gradation circuit. This makes it possible to apply, to each signal line, a signal voltage that has been multi-graded based on multi-bit digital image data. When performing multi-gradation based on 8-bit digital image data, the number of decoders required per signal line is 2 ⁸ = 256 unless the voltage modulation section is stepped at all. When multi-gradation is performed in two stages before and after, the number of decoders becomes 2 ⁴ + per signal line.
2 ⁴ = 32. On the other hand, when multi-gradation is performed in three stages of before, middle, and later according to the present invention, the number of decoders can be reduced to 2 ² +2 ³ +2 ³ = 20 per signal line. This facilitates the incorporation of the multi-gradation circuit in the panel. In addition, as the number of decoders is reduced, the number of reference voltages input from the outside can be reduced. The signal voltage falling between the adjacent reference voltages can be internally generated by the multi-gradation circuit. According to another aspect of the present invention, the first-stage voltage modulator includes a pair of analog elements that output a pair of reference voltages selected according to bit data, and the second-stage voltage modulator includes a pair of analog switches. It has a plurality of resistive elements connected in series between the elements, constructs a voltage divider circuit that includes a pair of analog elements as a resistance component, and extracts a voltage from the voltage divider circuit according to the bit data to signal Output voltage. By substituting a part of the resistance element with an analog switch element, the area occupied by the resistance element can be reduced. Further, it is not necessary to make the resistance of the analog switch element a resistance value that is negligibly small with respect to the resistance element group.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is an overall block diagram showing a display device according to the present invention. As shown in the figure, the present display device is roughly divided into a pixel array section 1, a vertical drive circuit 2, a horizontal drive circuit 3, and a timing generation circuit 4. At least a pixel array unit 1, a vertical drive circuit 2, and a horizontal drive circuit 3.
Can be integratedly formed on the same insulating substrate. However, the present invention is not limited to this, and only the pixel array unit 1 may be formed on a panel, and the remaining vertical drive circuit 2 and horizontal drive circuit 3 may be supplied by an external LSI.

The pixel array section 1 constitutes a screen of the present display device, in which scanning lines X and signal lines Y intersecting each other are arranged. Pixels PXL are formed at intersections of the row-shaped scanning lines X and the column-shaped signal lines Y. The pixel PXL includes at least a liquid crystal capacitor LC and a thin film transistor Tr.
The liquid crystal capacitor LC is composed of a pixel electrode and a counter electrode CO facing the pixel electrode.
M, and a liquid crystal is held between both electrodes as an electro-optical material. Note that the present invention is not limited to this, and other electro-optical materials can be used instead of the liquid crystal. In an actual panel structure, the pixel electrode and the thin film transistor Tr are integrally formed on one insulating substrate,
The counter electrode COM is formed entirely on the other insulating substrate. Liquid crystal is held between the two substrates. The liquid crystal capacitance LC is driven by the thin film transistor Tr. The thin film transistor Tr is, for example, a field effect transistor using polycrystalline silicon as an active layer. The drain electrode of the thin film transistor Tr is connected to the corresponding pixel electrode of the liquid crystal capacitor LC, the source electrode is connected to the corresponding signal line Y, and the gate electrode is connected to the corresponding scanning line X. The vertical drive circuit 2 includes a vertical shift register circuit 21 and an output buffer circuit 22. The vertical shift register circuit 21 operates according to the timing signal output from the timing generation circuit 4, and sequentially selects one row of pixels PXL via the output buffer circuit 22. Specifically, the vertical drive circuit 2
Sequentially outputs a selection pulse to each scanning line X, and keeps the thin film transistors Tr conductive for each row. Thus, the liquid crystal capacitance LC is connected to the corresponding signal line Y.

The horizontal drive circuit 3 comprises a horizontal shift register circuit 31, a line memory circuit 32, a level conversion circuit 33, and a multi-gradation circuit 34. Horizontal shift register circuit 3
1 operates in response to a timing signal supplied from the timing generation circuit 4 and sequentially samples digital image data supplied from the outside. The line memory circuit 32 also operates according to the timing signal supplied from the timing generation circuit 4, and collectively stores the sampled digital image data for one row. The stored digital image data is supplied to the multiple gradation circuit 34 via the level conversion circuit 33. The multi-gradation circuit 34 receives a reference voltage from the outside and is connected to the signal line Y. The multi-gradation circuit 34 generates a multi-gradation signal voltage based on multi-bit digital image data, and selects the selected multi-gradation signal. One row of pixels PXL
Write the signal voltage to. Specifically, a signal voltage is written to the corresponding liquid crystal capacitor LC via the thin film transistor Tr that has been turned on by the vertical drive circuit 2. As described above, the pixel PXL is formed on the insulating substrate. Each pixel PXL has a thin film transistor Tr connected to the scanning line X and the signal line Y, and a pixel electrode to which a signal voltage is written via the thin film transistor Tr. The thin film transistor Tr uses polycrystalline silicon as an active layer.
The vertical drive circuit 2 and the horizontal drive circuit 3 are also formed of thin film transistors integrated on the same insulating substrate as the pixels PXL. That is, this display device is of a built-in drive circuit type in which the peripheral vertical drive circuit 2 and the horizontal drive circuit 3 in addition to the pixel array section 1 are integrated on the same insulating substrate.

As a characteristic feature, the multi-gradation circuit 34 has a voltage modulation section corresponding to each signal line Y. In the present invention, the voltage modulation section is divided into at least three stages, and a front-stage voltage modulation section 35, a middle-stage voltage modulation section 36, and a rear-stage voltage modulation section 37 are connected in series. The pre-stage voltage modulator 35 performs primary gradation in accordance with the higher-order bit data included in the multi-bit configuration of the digital image data. The middle-stage voltage modulator 36 performs secondary gradation in accordance with the middle-order bit data included in the multi-bit configuration. The latter-stage voltage modulator 37 performs tertiary gradation according to the lower-order bit data included in the multi-bit configuration. The signal voltage generated through the primary to tertiary gradation is output to the corresponding signal line Y.

FIG. 2 shows a specific configuration example of the multi-gradation circuit 34 shown in FIG. 1, and shows only a portion corresponding to one signal line. As shown in the figure, this multi-gradation circuit has, for example, 8-bit digital image data D0 to D0.
A signal voltage gray-scaled to 256 levels based on D7 is supplied to the signal line. The former-stage voltage modulator 35 is configured to control the upper digit 2
Primary gradation is performed according to the bit data D0 and D1.
That is, it outputs a 4-level primary gradation signal A1A2 according to the 2-bit data D0 and D1. In this example, the preceding-stage voltage modulator 35 is of a voltage selection type that selects a voltage corresponding to the bit data D0D1 from a plurality of levels of preceding-stage reference voltages V0 to V4 input in advance and performs gradation. Therefore, in this specification, the pre-stage voltage modulator 35 having such a configuration is referred to as a voltage selection circuit. The middle voltage modulating section 36 performs secondary gradation in accordance with the middle digit side 3-bit data D2D3D4. That is, the 3-bit data D2D3D
4 to output an 8-level secondary gradation signal B1B2. In the present embodiment, the middle-stage voltage modulator 36 is of a gate voltage modulation type that performs gradation by using an analog gate element whose impedance changes according to the gate voltage. Therefore, in this specification, the middle-stage voltage modulator 36 is referred to as a gate voltage modulator. This gate voltage modulation circuit 36 is a primary gradation signal A1 supplied from the preceding voltage selection circuit 35.
A2 is accepted as a gate voltage for modulation. At the same time, the gate voltage modulation circuit 36 appropriately selects the middle-stage reference voltages V5 to V13 supplied from outside according to the value of the middle-order bit data D2D3D4. The selected middle stage reference voltage is modulated by the gate voltage to output the secondary gradation signal B1B2,
The voltage is supplied to the latter-stage voltage modulator 37. The latter-stage voltage modulator 37 performs tertiary gradation according to the lower-order 3-bit data D5D6D7. That is, an tertiary gradation signal C of 8 levels is output based on the 3-bit data D5D6D7. This tertiary gradation signal C is supplied to a signal line as a final signal voltage. In the present example, the post-stage voltage modulation section 37 is of a resistance division type that extracts a voltage division corresponding to the bit data D5D6D7 from the resistance-divided eight-level voltage. Therefore, in the present specification, the post-stage voltage modulation unit 37 is referred to as a resistance division modulation circuit. Specifically, the secondary gradation signal B1B2 is supplied to both ends of a plurality of resistors connected in series. The divided voltage of the secondary gradation signal B1B2 is converted to lower 3-bit data D5D6D.
7 is appropriately selected based on the value of 7.

FIG. 3 schematically shows a gradation signal output from the voltage modulation section of each stage shown in FIG. The pre-stage voltage modulator (voltage selection circuit) 35 is at a high level (Hig).
h), a pair of levels adjacent to each other is selected based on the upper two-bit data D0D1 from the pre-stage reference voltages V0 to V4 leveled from the low level (Low) to the primary gradation signal A1A2. Output. For example, D
When 0D1 = 11, a pair of V0V1 is selected and output to the middle-stage voltage modulator 36 as the primary gradation signal A1A2. The pre-stage voltage modulating section 35 sets V0 according to the value of D0D1.
One is selected from each pair of V1, V1V2, V2V3, and V3V4 and output. That is, roughly four levels of gradation are performed in the preceding stage. The middle voltage modulating section (gate voltage modulating circuit) 36 has a middle reference voltage V5V6, V6V7, V7V based on the value of the middle bit data D2D3D4.
8, V8V9, V9V10, V10V11, V11V1
2, one of which is selected from the pair of V12 and V13, and is output to the subsequent voltage modulation section C as the secondary gradation signal B1B2. For example, when D2D3D4 = 111, a pair of V5V6 is selected as the secondary gradation signal B1B2. On this occasion,
The gate voltage modulation circuit 36 modulates the secondary gradation signal B1B2 using the primary gradation signal A1A2 as a gate voltage, and outputs the result to the subsequent voltage modulation unit 37.
At this stage, gradation of 4 levels × 8 levels = 32 levels has been performed. The post-stage voltage modulation section (resistance division modulation circuit) 37 performs lower-order bit data D5 by a resistance division method.
Tertiary gradation of the secondary gradation signal B1B2 is performed based on D6D7. In this example, the secondary gradation signal B1B2
Is divided into eight levels by resistance division, one of the eight levels is selected according to the value of the lower bit data D5D6D7, and is output as a final tertiary gradation signal C (signal voltage). Finally, 4 × 8 × 8 = 256 levels of gradation can be achieved.

FIG. 4 shows a specific configuration of the multi-gradation circuit shown in FIG. For reference, the configuration of the conventional multi-gradation circuit shown in FIG. 13 is shown again. As shown in the figure, the conventional multi-gradation circuit has 256 reference voltage selection circuits 135-1 to 135-256 connected in series, and has 8-bit digital image data D0D1D2D.
One of the reference voltage selection circuits is turned on in accordance with 3D4D5D6D7, and the corresponding reference voltage is output to one signal line Y as an analog signal voltage.

On the other hand, the multi-gradation circuit of the present invention shown in (B) has four gate voltage selection circuits 35-
1 to 35-4, eight gate voltage modulation circuits 36-1 to 36-8 located at the middle stage, and eight resistance division modulation circuits 37-1 to 37-8 located at the subsequent stage. I have.
That is, the multi-gradation circuit according to the present invention is attached to one signal line,
A total of 20 decoders can be configured with four stages at the front stage, eight at the middle stage, and eight at the rear stage, so that the circuit size can be significantly reduced as compared with the related art. Upper bit data D0D1
When = 11, the first gate voltage selection circuit 35-1 is turned on, and the corresponding primary gradation signal is sent to the middle stage.
If D0D1 = 00, the fourth gate voltage selection circuit 35-
4 is turned on. Medium-order 3-bit data D2D3D4
If = 111, the first gate voltage modulation circuit 36-1 is turned on, and the corresponding secondary gradation signal is sent to the subsequent stage. If D2D3D4 = 000, the eighth gate voltage modulation circuit 36-8 is turned on. If the lower 3-bit data D5D6D7 = 111, the first resistance division modulation circuit 3
7-1 is turned on, and the corresponding tertiary gradation signal is output to the signal line Y as an analog signal voltage. D5D6
If D7 = 000, the eighth resistance division modulation circuit 37-8 is turned on.

FIG. 5 is a circuit diagram showing a more specific configuration of the multi-gradation circuit shown in FIG. In this figure, to facilitate understanding, the first gate voltage selection circuit 35
-1 and the first gate voltage modulation circuit 36-1 and the first resistance division modulation circuit 37-1 only, and these circuits are 8-bit digital image data D0D1D2D3D.
4D5D6D7 = 11111111 indicates a case where all the elements are turned on. The gate voltage selection circuit 35-1 in the preceding stage includes a decoder circuit DEC1 and a pair of analog gate elements TG1 and TG2. Here, a CMOS transmission gate element is used as the analog gate element (analog switch). The decoder circuit DEC1 outputs a selection signal X according to D0D1 = 11.
1, x1 is output, and TG1 and TG2 are opened to select a pair of preceding-stage reference voltages V0 and V1. The pair of V0 and V1 is as shown in FIG. Note that X1 and x1 are in opposite phase relationship with each other. The pair V0, V1 of the previous-stage reference voltage that has passed through TG1, TG2 is supplied to the middle-stage gate voltage modulation circuit 36-1 as the primary gradation signal A1A2. Decoder circuit DE belonging to middle-stage gate voltage modulation circuit 36-1
C2 is a selection signal X2, x according to D2D3D4 = 111.
2 and outputs the analog gate elements TG3, TG4, TG
5, make TG6 conductive. When TG3 and TG4 are turned on, primary gradation signals A1 and A2 are applied to the gates of TG5 and TG6, respectively. TG5, T
When G6 is turned on, a pair of middle stage reference voltages V5, V5
6 is selected. The levels of the pair of V5 and V6 are as shown in FIG. V5 is modulated by A1 at TG5, and the result is sent as a secondary gradation signal B1 to the subsequent resistance division modulation circuit 37-1. Similarly, V6 is modulated by A2 by TG6, and the result is sent to the subsequent resistance division modulation circuit 37-1 as a secondary gradation signal B2. A1,
A2 has a role of modulating V5 and V6. That is, TG
5, the on-resistance of TG6 is controlled by A1 and A2, respectively. TG5 and TG6 receive V5 and V6, respectively, and output B1 and B2. The outputs from TG5 and TG6 are determined by the ratio of the resistance of these analog switches. The resistance between the drain and source of TG5 is represented by R
Assuming that the resistance between the drain and the source of the TG 6 is R6, the output voltage VOUT of the secondary gradation signal B1B2 is given by the following equation. VOUT = (V5-V6) /
(R5 + R6) × R5 + V6 = (R5 × V5 + R6 × V
6) / (R5 + R6). Here, the values of R5 and R6 are TG
5, TG6, the pre-stage reference voltages V0, V
1 is controlled. Subsequent resistance division modulation circuit 37-1
The decoder circuit DEC3 belonging to D5D6D7 = 111
Select signals X3 and x3 in response to, open the analog gate element TG7, and output the tertiary gradation signal C as the final signal voltage. The resistance division modulation circuit 37-1 includes resistors R1 to R9 connected in series. Secondary gradation signals B1 and B2 are applied to both ends of the series connection.
The output voltage of the secondary gradation signal B1B2 is resistance-divided by R1 to R9, and a desired voltage division is selected by TG7. In this example, since D5D6D7 = 111, the highest-level partial voltage is extracted from one end of R1 and supplied to the signal line Y via TG7.

FIG. 6 shows the primary gradation signal A1 shown in FIG.
FIG. 4 is a schematic diagram showing specific waveforms of A2, a secondary gradation signal B1B2, and a tertiary gradation signal C. As shown in the figure, when driving a pixel array using liquid crystal as an electro-optical material, an alternating signal is used as the signal voltage. For example, the polarities of the primary gradation signals A1 and A2 are inverted every horizontal period (1H) or one field period (1F) around the signal voltage. Similarly, the secondary gradation signals B1 and B2 are also converted to AC with the signal voltage at the center. As mentioned above,
The secondary gradation signals B1 and B2 are primary gradation signals A1 and A2.
Is amplitude-modulated by an analog gate element using the gate voltage as a gate voltage. The output voltage of the secondary gradation signal B1B2 is divided into a desired value by resistance division, and a final tertiary gradation signal C is obtained. The tertiary gradation signal C is converted into an alternating current centering on the signal voltage, and its amplitude is finally modulated based on the values of the 8-bit digital image data D0 to D7.

FIG. 7 is a block diagram showing another embodiment of the multi-gradation circuit according to the present invention. Parts corresponding to those in the embodiment shown in FIG. 2 are denoted by corresponding reference numerals to facilitate understanding. The difference is that the pre-stage voltage modulator 35 of the previous embodiment is a gate voltage selection circuit, whereas the present embodiment is a gate pulse selection circuit. That is, the pre-stage voltage modulator 35 selects one of the four types of gate pulses φ0 to φ3 supplied from the outside according to the value of the upper two-bit data D0D1. The selected gate pulse is output to the middle-stage voltage modulator 36 as the primary gradation signal A. The middle voltage modulator 36 of this embodiment is basically the same as the middle voltage modulator of the previous embodiment, but employs a gate pulse modulation method instead of a gate voltage modulation method. That is, the middle-stage voltage modulation section 36 outputs the primary gradation signal A
Is performed by using an analog gate element that opens and closes in accordance with the duty ratio of the gate pulse supplied as. The secondary gradation signal B1B2 output from the middle voltage modulator 36 is supplied to the second voltage modulator 37. this is,
This is a resistance division modulation circuit as in the previous embodiment.

FIG. 8 shows the waveform of each gradation signal output from each stage voltage modulator shown in FIG. The gate voltage selection circuit included in the pre-stage voltage modulator 35 selects one of four types of gate pulses φ0 to φ3 having different duty ratios to generate the primary gradation signal A. For example, D0
When D1 = 11, φ0 is selected as A. The gate pulse modulating circuit constituting the middle voltage modulating unit 36 is D2D3D
A pair is selected from the reference voltages V5 to V13 according to the value of 4,
It is assumed that the signal is a secondary gradation signal B1B2. At this time, the selected pair of reference voltages is subjected to gate pulse modulation by the primary gradation signal A supplied from the preceding-stage voltage modulator 35.

FIG. 9 shows a specific configuration of the multi-gradation circuit shown in FIG. Parts corresponding to those of the previous embodiment shown in FIG. 5 are denoted by corresponding reference numerals to facilitate understanding. The decoder circuit DEC1 belonging to the preceding gate pulse selection circuit 35-1 outputs the selection signals X1 and x1 according to D0D1 = 11, and opens TG1 to select φ0. The decoder circuit DEC2 belonging to the gate pulse modulation circuit 36-1 in the middle stage outputs the selection signals X2 and x2 according to D2D3D4 = 111, opens TG3, and accepts the primary gradation signal A composed of φ0 as a gate pulse. Further, the decoder circuit DEC2 opens TG5 and TG6 to receive the pair of reference voltages V5 and V6. V5 and V6 undergo gate pulse modulation by A at TG5 and TG6, respectively, and the results are output as secondary gradation signals B1 and B2 to the subsequent resistance division modulation circuit 37-1.

FIG. 10 is a waveform chart for explaining the operation of the multi-gradation circuit shown in FIG. As shown, the gate pulse φ0 selected by the gate pulse selection circuit 35-1 at the preceding stage is a rectangular wave having an amplitude of VDD and a period of T. The duty ratio is set to 1: 1. The polarity of the pair of reference voltages V5 and V6 selected by the gate pulse modulation circuit 36-1 at the middle stage is inverted every 1H or 1F with the signal voltage as the center. The gate pulse φ0 selected in the previous stage is directly input to the middle stage as the primary gradation signal A. The pair of reference voltages V5 and V6 selected in the middle stage are gate pulse-modulated by the primary gradation signal A, and the secondary gradation signal B
1, B2 are obtained. The output voltage of the secondary gradation signal B1B2 is divided by the subsequent resistance division modulation circuit 37-1.
A tertiary gradation signal C having a desired amplitude level is obtained. The tertiary gradation signal C has been smoothed to some extent, and is sent to the corresponding signal line Y as it is as a signal voltage.
The amplitude of the signal voltage can be finally set by the values of the 8-bit digital image data D0 to D7.

As described above, one feature of the present invention is an integrated drive circuit using a TFT. The reason for implementing a thin film transistor, that is, an integrated driving circuit using a TFT will be described below. Conventionally, the gradation control method of signal output is as follows:
Output control was performed by an operational amplifier circuit. However, variations in the MOSTrs constituting the operational amplifier dominate the reproducibility and uniformity of the gradation output. FIG. 14 shows a multi-tone circuit using an amplifier circuit used in an IC. The operating principle of this circuit is that the input digital data a to d are connected to a resistor a via a CMOS buffer.
A current flows from 1 to d1. The added current is received on the input side of the amplifier, and the increase in the charge is detected. Then, Vout is output at the final output in a form proportional to the signal voltage.

However, as shown in FIG. 15, the mirror circuit used in this circuit must have the same Tr characteristics in order to maintain the constant current I1 / 2. This is because the output voltage at point e where this is output fluctuates. Finally, the output signal output at Vout is:
It is not stable due to Tr variations, and it becomes impossible to perform fine gradation signal control of an output signal with respect to an input signal. Therefore, it is difficult to use a TFT for the amplifier circuit. Therefore, in the present invention, a multi-tone signal output circuit without an amplifier is required as described above. The amplifier circuits shown in FIGS. 14 and 15 are generally used for gradation control. In particular, prior to this, a resistance connection is made, and by selecting this resistance connection, gradation is obtained. Here, the problem is the above-mentioned I1 / 2 portion, and it is necessary for the left I1 / 2 and the right I1 / 2 to similarly supply current. If the transistors are not formed uniformly, this balance will be broken and the linearity of the input signal and the output signal will be lost.

It is difficult to realize this in a TFT. In particular, variation in offset current due to Vth of the transistor becomes a problem. This is preferably within 10%, which is achieved by current TFTs.
Difficult with devices. In a TFT, a variation of ± 40% is common. In order to avoid this, in a TFT-integrated drive circuit used in a multi-tone circuit, the TFT is
It is desirable to use it as a signal selection switch. The present invention positively employs this, so that even if a TFT having a large variation is used, the variation in the gradation signal can be reduced.

FIG. 16 is a schematic block diagram showing another embodiment of the display device according to the present invention, and shows only main parts. Note that parts corresponding to those in the previous embodiment shown in FIG. 2 are denoted by corresponding reference numerals to facilitate understanding. The multi-gradation circuit 34 shown in FIG. 16 is incorporated in the horizontal drive circuit 3 of the display device shown in FIG.
Only a portion corresponding to one signal line is shown. As shown in the figure, the multi-gradation circuit 34 supplies a signal voltage that has been gradation-converted to 64 levels based on, for example, 6-bit digital image data D0 to D5. The multi-gradation circuit 34 includes a front-stage voltage modulator 35 and a rear-stage voltage modulator 3
7 in series. The pre-stage voltage modulator 35 performs primary gradation in accordance with the upper digit side 3-bit data D0, D1, D2. That is, it outputs an 8-level primary gradation signal A1A2 according to the 3-bit data D0, D1, D2. In this example, the pre-stage voltage modulator 35 is of a voltage selection type that selects a voltage corresponding to the bit data D0D1D2 from a plurality of levels of reference voltages V0 to V8 input in advance and performs gradation. Therefore, the pre-stage voltage modulator 35 having such a configuration will be referred to as a reference voltage selection circuit. The rear-stage voltage modulation unit 37 outputs lower-order 3-bit data D3D4.
Secondary gradation is performed according to D5. That is, an 8-level secondary gradation signal C is output based on the 3-bit data D3D4D5. This secondary gradation signal C is supplied to a signal line as a final signal voltage. In this example, the voltage modulation unit 3
Reference numeral 7 denotes a resistance division type that extracts a voltage division corresponding to the bit data D3D4D5 from the resistance-divided eight-level voltage. Here, the post-stage voltage modulation unit 37 is referred to as a resistance division modulation circuit. Specifically, a primary gradation signal A1A2 is supplied to both ends of a plurality of resistance elements connected in series. The primary gradation signal A1A2 is composed of a pair of high and low reference voltages selected by the reference voltage selection circuit 35 at the preceding stage. The divided voltage of this primary gradation signal A1A2 is
It is appropriately selected based on the value of the bit data D3D4D5.

FIG. 17 shows the multi-gradation circuit 3 shown in FIG.
4 shows a specific configuration. For reference, the configuration of a conventional multiple gradation circuit is shown in FIG. As shown
This conventional multi-gradation circuit includes a reference voltage selection circuit 135-1.
To 135-64 in series, and any one of the reference voltage selection circuits is turned on according to the 6-bit digital image data D0D1D2D3D4D5,
The corresponding reference voltage is output to one signal line Y as an analog signal voltage. In the case of 6-bit data, since there are 64 gradations, the conventional multi-gradation circuit requires a reference voltage of 64 levels. Correspondingly, 64 reference voltage selection circuits are required. Each reference voltage selection circuit is composed of a combination of a decoder circuit and an analog switch. In the case of 64 gradations, 64 decoder circuits are required for one signal line Y. In this conventional example, the chip size increases as the occupied area of the digital / analog circuit constituting the reference voltage selection circuit increases. In addition, as the number of levels of the reference voltage increases, the number of wirings for external input / output increases, and the yield decreases during connection work with the outside. or,
As the chip area increases, the parasitic capacitance inside the digital-to-analog conversion circuit increases, and internal signal delay occurs. For this reason, high-speed response is impaired and driving at high frequencies becomes difficult.

On the other hand, the multi-gradation circuit of the present invention shown in (B) has eight reference voltage selection circuits 35-
1 to 35-8, and eight resistance division modulation circuits 37-1 to 37-8 located at the subsequent stage. In other words, the multi-gradation circuit according to the present invention can be composed of a total of 16 decoders, one for the signal line and eight for the former stage and eight for the latter stage. Can be achieved. When the upper bit data D0D1D2 = 111, the first reference voltage selection circuit 35-1 is turned on, and the corresponding primary gradation signal is sent to the subsequent stage. D0D1D2 = 00
If 0, the eighth reference voltage selection circuit 35-8 is turned on. On the other hand, for the subsequent stage, the lower three-bit data D3
If D4D5 = 111, the first resistance division modulation circuit 37-
1 is turned on, and the corresponding secondary gradation signal is output to the signal line Y as an analog signal voltage. If the lower 3-bit data D3D4D5 = 000, the eighth resistance division modulation circuit 37-8 is turned on. As described above, in the present embodiment, the reference voltage selection circuit at the preceding stage is constituted by a decoder including an analog switch for selecting a reference voltage. The subsequent resistance division modulation circuit is constituted by a decoder including a voltage dividing resistor. This constitutes a digital multi-gradation circuit that generates multi-gradation analog signal voltages. In the present embodiment, in a display device having a drive circuit of a digital data input method, by connecting a reference voltage selection circuit and a resistance division modulation circuit in series, more gradations than the number of levels of a reference voltage prepared in advance are provided. It can be realized.
A reference voltage is selected according to the input digital image signal, and the selected reference voltage is divided to obtain an analog signal voltage. The final analog signal voltage is located between the selected pair of high and low reference voltages. That is, the analog signal voltage is lower than the high-level reference voltage and has an intermediate voltage level higher than the low-level reference voltage.

FIG. 18 is a circuit diagram showing a more specific configuration of the multi-gradation circuit shown in FIG. In this figure, the first reference voltage selection circuit 35 is provided for easy understanding.
-1 and the first resistance division modulation circuit 37-1 only, and these circuits are 6-bit digital image data D
0D1D2D3D4D5 = 111111 indicates a case where all the elements are turned on. The reference voltage selection circuit 35-1 at the preceding stage includes a decoder circuit DEC1 and a pair of analog switch elements TG1 and TG2. here,
A CMOS transmission gate element is used as the analog switch element. Decoder circuit DEC
1 is a selection signal X1, x1 according to D0D1D2 = 111.
TG1 and TG2 are opened to open a pair of reference voltages V
Select H and VL. VH is on the high level side and VL is on the low level side. When D0D1D2 = 111, the reference voltage V0 shown in FIG. 16 is actually selected as VH, and the reference voltage V1 is selected as VL. Note that X1 and x1 have phases opposite to each other. TG1, T
The pair of reference voltages VH and VL that have passed through G2 are supplied as primary gradation signals A1A2 to the subsequent-stage resistive division modulation circuit 37-1.

The decoder circuit DEC3 belonging to the subsequent stage resistance division modulation circuit 37-1 outputs the selection signals X3 and x3 in accordance with D3D4D5 = 111, and
G7 is opened to output the secondary gradation signal C as a final signal voltage. The resistance division modulation circuit 37-1 includes seven resistance elements RS connected in series. The primary gradation signal A1 is connected to both ends of the series connection via a pair of analog switch elements TG1 and TG2 on the side of the reference voltage selection circuit 35-1.
A2 is applied. The output voltage of the reference voltage selection circuit 35-1 is resistance-divided by seven resistance elements RS, and a desired voltage division is selected by TG7. In this example, D3D4D5 =
Since it is 111, the highest level of partial pressure is extracted and supplied to the signal line Y via TG7.

As described above, the reference voltage selection circuit 35-1 at the preceding stage includes a pair of analog switches TG1 and TG2 for outputting a pair of high and low reference voltages VH and VL selected according to the upper three-bit data D0D1D2. ing. The latter-stage resistive division modulation circuit 37-1 includes seven resistive elements RS connected in series between a pair of analog switches TG1 and TG2, and a pair of analog switch elements TG.
1 and TG2 as a resistance component. The resistance division modulation circuit 37-1 extracts the divided voltage from the voltage dividing circuit in accordance with the lower three-bit data D3D4D5, and outputs an analog signal voltage to a signal line. Preferably,
The resistance value of each resistance element RS is the analog switch element TG
1 and TG2 are set to be at least twice the resistance values R1 and R2 when in the conductive state. Further, the plurality of resistance elements RS have the same resistance value (also represented by RS), and are connected to a pair of analog switches by seven resistance elements RS which is one less than the number of gradations 8 of the secondary gradation. Element TG1, TG
2 are connected in series. On the other hand, in the previous resistance division modulation circuit shown in FIG. 5, nine resistance elements R1 to R9, which is one more than the number of gradations of 8, are connected in series to form a voltage dividing circuit. In this case, the conduction resistance of the pair of analog switch elements needs to be as close to 0 as possible. On the other hand, in the present embodiment, the voltage dividing circuit is configured in consideration of the conduction resistance of the analog switch elements TG1 and TG2 in advance, and the number of series resistance elements can be one less than the number of gradations of eight. Also, the conduction resistances R1, R2 of the analog switch elements TG1, TG2
Since it is not necessary to suppress 2 to 0 as much as possible, the burden on circuit design can be reduced. In FIG. 18, nodes for extracting any one of the eight partial pressures are represented by eight black circles. As shown, the highest partial pressure is taken from the connection point (node) between TG1 and the first RS. The lowest partial pressure is T
It is extracted from the connection point (node) between G2 and the lowest RS. In the illustrated example, the lower three-bit data D3D4D5
Since = 111, the top node among the eight nodes connected to the TG 7 is selected.

The drain of the analog switch element TG1
The source-to-source resistance is R1, and the analog switch element TG2
Let R2 be the resistance between the drain and the source of the pair, and let RS be one resistance of the plurality of resistance elements RS connected in series to the pair of analog switch elements TG1 and TG2.
8 is represented by the following equation. That is, assuming that the high-level reference voltage is VH and the low-level reference voltage is VL, VOUT1 to VOUT8 are obtained by dividing the potential difference (VH-VL) between them by eight. In this case, n = 8 in the equation.

VOUT1 = (VH-VL) * R1 / (R1 + RS * n + R2) VOUT2 = (VH-VL) * (R1 + RS * 1) / (R1 + RS * n + R2) VOUT3 = (VH-VL) * (R1 + RS * 2) / (R1 + RS * n + R2) VOUT4 = (VH-VL) * (R1 + RS * 3) / (R1 + RS * n + R2) VOUT5 = (VH-VL) * (R1 + RS * 4) / (R1 + RS * n + R2) VOUT6 = (VH-VL) ) * (R1 + RS * 5) / (R1 + RS * n + R2) VOUT7 = (VH-VL) * (R1 + RS * 6) / (R1 + RS * n + R2) VOUT8 = (VH-VL) * (R1 + RS * 7) / (R1 + RS * n + R2) )

FIG. 19 is a graph showing the linearity of the signal voltage output from the multi-gradation circuit shown in FIG. As illustrated, the multi-gradation circuit of the present embodiment outputs a signal voltage of 64 gradations according to 6-bit digital data. The reference voltage selection circuit at the preceding stage uses (V) as a pair of VH and VL.
0 = 10.5V, V1 = 10.0V), (V1 = 10.
0V, V2 = 9.5V), (V2 = 9.5V, V3 =
9.0V), (V3 = 9.0V, V4 = 8.5V),
(V4 = 8.5V, V5 = 8.0V), (V5 = 8.0V)
V, V6 = 7.5V), (V6 = 7.5V, V7 = 7.
0V) or (V7 = 7.0V, V8 = 6.5V) is selected in accordance with the value of the upper 3-bit data. By substituting the selected pair of high and low reference voltages into VH and VL in the above equation, a divided voltage of eight gradations can be obtained. One of the eight levels of voltage division is selected in accordance with the value of the lower three-bit data. As described above, the resistance division modulation circuit also includes a pair of analog switch elements as resistors, and eight divided voltages are generated between a pair of high and low reference voltages VH and VL. As a result, there are eight types of reference voltage pairs, and eight
Since there are different types, a signal voltage of 64 gradations can be generated by multiplying these. On the other hand, in the conventional method, a signal voltage is generated by a set of 64 resistive voltage dividers and a decoder. Compared to this conventional example, the present embodiment requires a circuit size of 1/4. Also, by replacing a part of the resistance element with an analog switch element, the area of the resistance element can be reduced. At the same time, there is no need to make the resistance of the analog switch element negligibly smaller than that of the resistive element group for voltage division. Therefore, the size of the transistor of the analog switch element itself can be reduced.

The resistances R1 and R1 of the pair of analog switch elements
It is desirable that R2 be set to 1/2 or less of RS of the resistance element. By doing so, the linearity of the signal voltage with respect to the gradation is maintained. As shown in FIG.
In the range of V to 10.5 V, the signal voltage keeps a substantially linear gradation. In order to maintain the linearity of the signal voltage with respect to the gray scale, it is necessary to appropriately set the resistances R1 and R2 of the analog switch elements which have a dominant influence on the voltage division close to the reference voltages VH and VL. R1 and R2 need to be relatively small relative to the RS, and preferably less than or equal to 1/2 of the RS.

FIG. 20 shows the dependence of the signal voltage on the resistance of the analog switch element. Even if the resistances R1 and R2 of the analog switch element fluctuate ± 50% with respect to the center value, the variation width of the signal voltage is very small, 48 mV. FIG. 20 shows that the resistance value R1 of the analog switching element TG1 is varied by ± 50% with respect to the center value, and the resistance value R2 of the analog switching element TG2 is varied by ± 50% with respect to the center value. This is a view of the signal voltage in the case of the above. As is clear from the graph, since the fluctuating voltage is suppressed to a small value, a signal voltage almost faithful to the gradation selection can be applied to each pixel of the display.
Note that the resistance values of the analog switch elements TG1 and TG2,
The resistance values of the plurality of resistance elements and the values of the reference voltages VH and VL are
It is necessary to optimize as appropriate according to the transmittance of the liquid crystal and the applied voltage characteristics.

[0043]

As described above, according to one aspect of the present invention, a multi-gradation circuit is formed by connecting at least the front, middle, and rear three-stage voltage modulating units in series, and converts digital data to digital data. Accordingly, multi-gradation of the signal voltage is achieved. For example, when multi-gradation is performed based on 8-bit digital image data, and when no step is performed, the multi-gradation circuit requires 2 ⁸ = 256 decoders per signal line. is there.
When multi-gradation is performed in two stages before and after, 2 ⁴ +2 ⁴ = 3
Two decoders are required. In the present invention, 3
2 ² +2 ³ +2
³ = 20 decoders are sufficient. As described above, the number of decoders can be reduced as compared with the related art, the size of the multi-gradation circuit can be reduced, and the incorporation into the panel can be facilitated. In addition, the number of levels of the reference voltage supplied from the outside can be reduced as the number of stages of the multi-gradation circuit increases, and the circuit scale and the wiring area can be reduced. According to another aspect of the present invention, the first-stage voltage modulator includes a pair of analog elements that output a pair of reference voltages selected according to bit data, and the second-stage voltage modulator includes a pair of analog devices. Equipped with a plurality of resistive elements connected in series between the analog switch elements, configures a voltage divider circuit that includes a pair of analog elements as resistance components, and extracts the voltage divided from the voltage divider circuit according to the bit data To output a signal voltage. By substituting a part of the resistance element with an analog switch element, the area occupied by the resistance element can be reduced. Further, it is not necessary to make the resistance of the analog switch element a resistance value that is negligibly small with respect to the resistance element group. Therefore, the transistor size of the analog switch element itself can be reduced.
In addition, even if a transistor formed on a large-area insulating substrate has a variation in operation characteristics, stable gradation expression can be secured.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a display device according to the present invention.

FIG. 2 is a block diagram showing a multi-gradation circuit included in a horizontal drive circuit of the display device shown in FIG.

FIG. 3 is a schematic diagram for explaining the operation of the multi-grayscale circuit shown in FIG. 2;

FIG. 4 is a block diagram illustrating a specific configuration of a multi-gradation circuit.

FIG. 5 is a circuit diagram showing a more specific configuration of the multi-gradation circuit shown in FIG.

FIG. 6 is a waveform chart for explaining the operation of the multi-grayscale circuit shown in FIG. 5;

FIG. 7 is a block diagram showing a multi-gradation circuit according to another embodiment.

FIG. 8 is a schematic diagram for explaining the operation of the multi-gradation circuit shown in FIG. 7;

FIG. 9 is a circuit diagram showing a specific configuration of the multi-gradation circuit shown in FIG. 7;

FIG. 10 is a waveform chart for explaining the operation of the multi-grayscale circuit shown in FIG. 9;

FIG. 11 is a block diagram illustrating an example of a conventional display device.

12 is a circuit diagram showing a configuration example of a horizontal drive circuit included in the conventional display device shown in FIG.

13 is a block diagram illustrating a configuration example of a digital-to-analog conversion circuit included in the horizontal drive circuit illustrated in FIG.

FIG. 14 is a circuit diagram showing an example of a conventional multiple gradation circuit.

FIG. 15 is a circuit diagram illustrating an example of an amplifier included in the multiple gradation circuit illustrated in FIG. 14;

FIG. 16 is a block diagram showing another embodiment of the multi-gradation circuit included in the horizontal drive circuit of the display device shown in FIG.

FIG. 17 is a block diagram showing a specific configuration of the multi-grayscale circuit shown in FIG. 16;

18 is a circuit diagram showing a more specific configuration of the multi-grayscale circuit shown in FIG.

FIG. 19 is a graph showing the linearity of a signal voltage output from the multi-gradation circuit shown in FIG.

20 is a graph showing the linearity of a signal voltage output from the multiple gradation circuit shown in FIG.

[Explanation of symbols]

1 ... pixel array section, 2 ... vertical drive circuit, 3 ...
.Horizontal drive circuit, 4... Timing generation circuit, 21.
..Vertical shift register circuits, 22 ... output buffer circuits, 31 ... horizontal shift register circuits, 32 ...
Line memory circuit, 33 ... level conversion circuit, 34
..Multi-gradation circuit, 35... Preceding voltage modulating section, 36.
..Middle-stage voltage modulators, 37 ... second-stage voltage modulators

Claims (10)

[Claims] 1. A row of scanning lines and a column of signal lines crossing each other, pixels arranged at the intersection of the two, and a vertical drive circuit connected to each scanning line and sequentially selecting one row of pixels. ,
A horizontal drive circuit that is connected to each signal line, generates a multi-grayscale signal voltage based on multi-bit digital image data, and writes the signal voltage to a selected row of pixels. A display device, wherein the horizontal drive circuit includes at least a preceding-stage voltage modulation unit that performs primary gradation according to upper-order bit data included in a multi-bit configuration; A middle-stage voltage modulation unit that performs secondary gradation according to bit data on the significant digit side, and a voltage modulation unit at the subsequent stage that performs tertiary gradation according to bit data on the low-order digit also included in the multi-bit configuration A multi-gradation circuit in which are connected in series. 2. The multi-gradation circuit according to claim 1, wherein at least one of the voltage modulating units of each stage is of a resistance division type for extracting a voltage corresponding to the bit data from a plurality of voltage levels divided by resistance. The display device according to claim 1, wherein: 3. The multi-gradation circuit according to claim 1, wherein at least one of the voltage modulation sections of each stage is of a gate voltage modulation type that performs gradation using an analog gate element whose impedance changes according to a gate voltage. The display device according to claim 1, wherein: 4. The multi-gradation circuit according to claim 1, wherein at least one of the voltage modulating units of each stage performs gradation by using an analog gate element that opens and closes in accordance with the duty ratio of the gate pulse. The display device according to claim 1, wherein the display device is a mold. 5. The multi-gradation circuit, wherein at least one of the voltage modulating units of each stage performs gradation by selecting a voltage corresponding to the bit data from a plurality of levels of voltages input in advance. The display device according to claim 1, wherein the display device is a voltage selection type. 6. The pixel includes a thin film transistor formed on an insulating substrate and connected to the scanning line and the signal line, and a pixel electrode to which a signal voltage is written via the thin film transistor. 2. The display device according to claim 1, wherein the drive circuit is also formed by a thin film transistor integrated on the same insulating substrate. 7. A row of scanning lines and columns of signal lines that intersect each other, pixels arranged at the intersection of the scanning lines, and a vertical drive circuit connected to each scanning line and sequentially selecting one row of pixels. ,
A horizontal drive circuit that is connected to each signal line, generates a multi-grayscale signal voltage based on multi-bit digital image data, and writes the signal voltage to a selected row of pixels. A display device, wherein the horizontal drive circuit includes at least a preceding-stage voltage modulation unit that performs primary gradation according to upper-order bit data included in a multi-bit configuration, and a lower-order voltage modulation unit also included in a multi-bit configuration. It has a multi-gradation circuit in which a second-stage voltage modulation unit that performs a second gradation in accordance with the digit-side bit data and outputs a signal voltage is connected in series. And a pair of analog switch elements for outputting a pair of reference voltages selected according to the following. The voltage modulation unit at the subsequent stage includes a plurality of resistance elements connected in series between the pair of analog switch elements. Yes, the one Display device, characterized in that the analog switch device constitutes a voltage divider circuit including a resistance component, and outputs a signal voltage removed the partial pressure from the voltage dividing circuit in accordance with the bit data of the. 8. The display device according to claim 7, wherein the resistance value of each resistance element is set to be at least twice the resistance value when the analog switch element is in a conductive state. 9. A plurality of resistive elements have the same resistance value, and a number of resistive elements one less than the number of gradations of secondary gradation are connected in series between the pair of analog switch elements. The display device according to claim 7, wherein: 10. The pixel includes a thin film transistor formed on an insulating substrate and connected to the scan line and the signal line, and a pixel electrode to which a signal voltage is written via the thin film transistor. 8. The display device according to claim 7, wherein the drive circuit is also formed of a thin film transistor integrated on the same insulating substrate.