JP2006173779A - Digital/analog conversion circuit and display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a digital/analog conversion circuit in which the scale of circuit is reduced, and to provide a display in which the size is reduced by employing that digital/analog conversion circuit. <P>SOLUTION: In a switch circuit, one voltage out of 64 reference voltages Vref being supplied from a reference voltage output circuit is selected depending on a 6 bit signals (b0-b5) and delivered to an output line DAO as an analog signal. 64 signal paths leading to the output line DAO from each input line of the reference voltage V0-V64 are classified into 32 sets of signal path group each comprising two signal paths wherein the two signal paths in the same set share five out of six transistors connected in series. Consequently, the number of transistors used is decreased by 160 as compared with a case where the transistors are not shared. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a digital-to-analog converter circuit and a display device using the same, and more particularly, to a digital-to-analog converter circuit that selects one of a plurality of reference voltages according to a digital signal and outputs it as an analog signal. The present invention relates to a display device that drives pixels accordingly.

  Usually, a digital-analog conversion circuit is mounted on a horizontal drive circuit of a display device. The digital-analog conversion circuit is used to convert a pixel signal input as a digital signal into an analog signal necessary for driving the pixel.

  There are various types of digital-analog conversion circuits used for driving pixels depending on the type of pixel and the driving method. For example, in a liquid crystal display device, an EL (electroluminescence) display device, and the like, a reference voltage selection type digital-analog conversion circuit that outputs a reference voltage selected from a plurality of reference voltages according to a pixel signal as an analog signal is used. .

FIG. 11 is a diagram illustrating an example of a main configuration of the reference voltage selection type digital-analog conversion circuit disclosed in Patent Document 1. In FIG.
The digital-analog converter circuit shown in FIG. 11 selects one of 64 reference voltages (V0 to V64) generated by a reference voltage generation circuit (not shown) according to 6-bit pixels (b0 to b5). Output.

  As shown in FIG. 11, there are six MOS transistors between 64 input lines for inputting 64 reference voltages (V0 to V64) and an output line DAO for outputting analog signals. The series circuit comprised by is connected.

  Each MOS transistor constituting the series circuit corresponds to each bit of the 6-bit pixel signal, and is turned on or off according to the value of the corresponding bit. That is, a corresponding 1-bit signal in a 6-bit pixel signal is input to the gate of each MOS transistor, and the MOS transistor is turned on or off according to the gate signal.

In each series circuit, the conductivity types of the six MOS transistors are determined so as to be turned on only when a pixel signal having a specific value is input.
For example, as shown in FIG. 11, in the series circuit connected between the input line of the reference voltage V1 and the output line DAO, the MOS transistor corresponding to the least significant bit b0 corresponds to the n-type MOS transistor and the other bits. The MOS transistor that performs this is a p-type MOS transistor. Assuming that a signal with a bit value “0” corresponds to a low level and a signal with a bit value “1” corresponds to a high level, this series circuit is turned on only when a pixel signal of “000001” is input. When the pixel signal of another value is input, it is turned off.

The 64 transistor series circuits correspond to 64 values that a 6-bit pixel signal can take, and each transistor series circuit is turned on when a corresponding pixel signal is input, Turns off when a pixel signal of value is input. As a result, one reference voltage corresponding to the 6-bit pixel signals (b0 to b5) is selected from the 64 reference voltages (V0 to V64) and output to the output line DAO.
JP 2000-242209 A JP 2001-282168 A JP 2003-29687 A

  In parts of portable electronic devices (hereinafter referred to as portable devices) typified by cellular phones, the display device occupies a particularly large area and is a main factor that defines the size of the device. In recent years, there is a tendency to enlarge the screen of the display device in order to improve the visibility of the display. However, from the viewpoint of portability, there is a restriction that the overall size of the device cannot be increased too much.

  On the other hand, in a display device mounted on a mobile device, from the viewpoint of reducing the number of parts, a display unit that configures a screen and a peripheral circuit that performs driving and control thereof are integrally formed on a common substrate. is there. For example, in the case of a liquid crystal display device, a switching element of each pixel is formed using a polysilicon TFT (thin film transistor) on a glass substrate, and a peripheral circuit composed of the polysilicon TFT is mounted on the same glass substrate. There is.

In a display device in which a display unit and a peripheral circuit are integrated, the peripheral circuit is usually arranged in a peripheral region of the display unit (hereinafter, this region is referred to as a frame). However, as described above, since there is a demand to increase the screen without enlarging the size of the device, it is inevitably required to narrow the frame of the display device.
The digital-analog conversion circuit described above is a circuit that occupies a large area among the peripheral circuits arranged in the frame. To narrow the frame of the display device, it is a problem to reduce the circuit scale. It has become.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a digital-analog conversion circuit whose circuit scale is reduced and a display device which is miniaturized by using the digital-analog conversion circuit. There is.

The digital-analog conversion circuit according to the first aspect of the present invention outputs a reference voltage output circuit that outputs 2 ⁿ (n represents an arbitrary integer greater than 1) reference voltage and the reference voltage output circuit. 2 ⁿ input lines for inputting the 2 ⁿ reference voltages and one output line, and any one of the 2 ⁿ input lines according to an input n-bit signal. And a switch circuit for connecting the selected input line to the output line. The switch circuit is configured between the 2 ⁿ input lines and the output line, and has 2 ⁿ signal paths in which any one of the switch circuits is turned on according to the n-bit signal. Each signal path has n switches connected in series with each other and controlled to be turned on and off in accordance with the n-bit signal. At least some of the 2 ⁿ signal paths share some of the n switches.

  A display device according to a second aspect of the present invention includes a pixel portion having a plurality of pixels arranged in a matrix, the digital-analog conversion circuit according to the first aspect, and an analog output from the digital-analog conversion circuit. And a driving circuit for driving each pixel of the pixel portion based on the signal. Preferably, the digital-analog conversion circuit is formed on a common substrate with the pixel portion.

According to the present invention, since a part of the n switches is shared in at least a part of the 2 ⁿ signal paths, the number of switches is reduced as compared with a case where the switches are not shared.

  One or a plurality of switches shared by a plurality of signal paths may be connected between an intersection of the plurality of signal paths and the output line.

Further, the 2 ⁿ signal paths have at least one 2 ^k signal path pairs (k is an arbitrary integer from 1 to n) sharing a part of the n switches. Each signal path may have k intersections with other signal paths belonging to the same set.

  Each of the switches may include either a first conductivity type transistor or a second conductivity type transistor, or may include a parallel circuit of the first conductivity type transistor and the second conductivity type transistor.

  According to the present invention, by sharing a switch in a switch circuit that selects and outputs one of a plurality of reference voltages, the number of switches used can be reduced and the circuit scale can be reduced. Thereby, the size of the display device can be reduced.

  Hereinafter, two embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
FIG. 1 is a diagram illustrating an example of a configuration of a digital-analog conversion circuit according to the first embodiment of the present invention.
The digital-analog conversion circuit shown in FIG. 1 includes a switch circuit 9, a buffer circuit 10, and a reference voltage output circuit 11.
The switch circuit 9 is an embodiment of the switch circuit of the present invention.
The reference voltage output circuit 11 is an embodiment of the reference voltage output circuit of the present invention.

  The reference voltage output circuit 11 is a circuit that outputs 64 reference voltages (V0,..., V63). For example, as shown in FIG. 1, 64 resistors (R0,..., R63) connected in series are connected. Have. A reference voltage VR is applied to the resistor series circuit, and a voltage obtained by dividing the reference voltage VR into 64 levels is output as the reference voltages V0 to V63.

  The switch circuit 9 has 64 input lines (hereinafter referred to as input lines V0 to V63) for inputting reference voltages V0 to V63 and one output line DAO, and a 6-bit signal (b0,...). , B5), any one of 64 input lines V0 to V63 is selected and connected to the output line DAO.

  The switch circuit 9 has 64 signal paths configured between the 64 input lines V0 to V63 and the output line DAO. Of the 64 signal paths, one of them becomes conductive according to a 6-bit signal (b0,..., B5), and the other becomes non-conductive.

  Each signal path has six switches connected in series with each other. The six switches are controlled to be turned on and off in accordance with a 6-bit signal (b0,..., B5).

At least some of the 64 signal paths share some of the six switches. One or more switches shared by the plurality of signal paths are connected between the intersection of the plurality of signal paths and the output line DAO.
For example, a signal path that conducts when a 6-bit signal is “001101” and a signal path that conducts when a 6-bit signal is “001110” both have the upper 4 bits of the input signal set to “0011”. Therefore, these two signal paths can share four switches corresponding to the upper 4 bits. In this case, the four switches are connected in series between the intersection of the two signal paths and the output line DAO. The remaining two switches of each signal path are connected in series between this intersection and the reference voltage input line.

  The buffer circuit 10 receives a voltage output to the output line DAO of the switch circuit 9 and generates an output voltage Vout corresponding to the input voltage. Since the buffer circuit 10 functions as an impedance conversion circuit having a high input impedance and a low output impedance, even when the output impedance of the switch circuit 9 is high, the output voltage Vout corresponding to the voltage generated on the output line DAO is low impedance. Can be output.

  Next, a configuration example of the switch circuit 9 will be described.

FIG. 2 is a diagram illustrating a first configuration example of the switch circuit 9.
2 includes an input line V0,..., V63, an output line DAO, 64 transistors Q0-0,..., Q63-0, and 32 transistors Q1-1, Q3-1, Q5-1, Q7-1, ..., Q61-1, Q63-1, 32 transistors Q1-2, Q3-2, Q5-2, Q7-2, ..., Q61-2, Q63-2, 32 transistors Q1-3, Q3-3, Q5-3, Q7-3,..., Q61-3, Q63-3, and 32 transistors Q1-4, Q3-4, Q5-4, Q7-4 , ..., Q61-4, Q63-4 and 32 transistors Q1-5, Q3-5, Q5-5, Q7-5, ..., Q61-5, Q63-5.

The transistor Qj-k (j is an integer from 0 to 63, k is an integer from 0 to 5, and the same shall apply hereinafter) is an n-type or p-type MOS transistor. The conductivity type is defined as follows.
When the kth bit (where the 0th bit is the least significant bit) when the numerical value j is expressed in binary is “1”, the conductivity type of the transistor Qj-k is n-type, and the kth bit is In the case of “0”, the conductivity type of the transistor Qj-k is p-type.
For example, in the case of the transistor Q3-1, j = 3 = '0000011' and k = 1. Since the first bit of “000011” is “1”, the conductivity type of the transistor Q3-1 is n-type.

Transistor Qq-0 (q represents an odd number from 1 to 63; the same shall apply hereinafter) is connected between input line Vq and node Aq. For example, the transistor Q61-0 is connected between the input line V61 and the node A61.
Transistor Q (q-1) -0 is connected between input line V (q-1) and node Aq. For example, the transistor Q62-0 is connected between the input line V62 and the node A63.

  Transistors Qq-1, Qq-2, Qq-3, Qq-4, and Qq-5 are connected in series between node Aq and output line DAO. For example, transistors Q3-1, Q3-2, Q3-3, Q3-4, and Q3-5 are connected in series between node A3 and output line DAO.

  The k-th bit signal bk is input to the gate of the transistor Qj-k. For example, the second bit signal b2 is input to the transistor Q3-2.

The 6-bit signal (b0,..., B5) is set to a high level or a low level according to the bit value. That is, it is set to a high level when the bit value is “1” and to a low level when the bit value is “0”.
When the conductivity type of the transistor Qj-k is n-type, the transistor Qj-k is turned on when the bit signal bk is at a high level and turned off when the bit signal bk is at a low level. On the other hand, when the conductivity type is p-type, the transistor Qj-k is turned on when the bit signal bk is at a low level and turned off when the bit signal bk is at a high level.
The bit signal bk at the high level is set to a voltage higher than a voltage (V63 + Vthn) obtained by adding the threshold voltage Vthn of the n-type MOS transistor to the maximum value (V63) of the reference voltage. Further, the bit signal bk at the low level is set to a voltage lower than the voltage (V0−Vthp) obtained by subtracting the threshold voltage Vthp of the p-type MOS transistor from the minimum value (V0) of the reference voltage.

Hereinafter, the signal path from the input line Vj to the output line DAO is referred to as “RTj”. For example, the signal path RT2 includes six transistors Q2-0, Q3-1, Q3-2, Q3-3, Q3-4, and Q3-5 connected in series, and inputs via these transistors. A reference voltage is transmitted from the line V2 to the output line DAO.
The switch circuit 9 shown in FIG. 2 has 64 signal paths (R0 to R63). Each signal path is composed of six transistors connected in series.

These 64 signal paths are grouped into 32 signal path groups each composed of 2 signal paths. In detail,
(R0, R1), (R2, R3), ..., (R60, R61), (R62, R63);
In other words, the 64 signal paths R0 to R63 are grouped into 32 signal path groups.

  Each signal path has one intersection with another signal path belonging to the same set. Five transistors are connected in series between this intersection and the output line DAO. For example, five transistors Q 3-1, Q 3-2, Q 3-3, Q 3-4, and Q 3-5 are connected in series between the node A 3 that is the intersection of the signal paths R 2 and R 3 and the output line DAO. Yes. The five transistors are shared by signal paths R2 and R3.

Each of the 64 signal paths R0 to R63 corresponds to each of 64 (= 2 ⁶ ) values that the 6-bit signal (b0,..., B5) can take. When the 6-bit signal (b0,..., B5) is set to a certain value, one signal path corresponding to this value is turned on and the rest is turned off.
For example, when a 6-bit signal (b0,..., B5) is set to a value of “110011”, the transistors Q51-0, Q51-1, Q51-2, Q51-3, and Q51− constituting the signal path R51 are set. 4, Q51-5 becomes conductive, and the input line V51 and the output line DAO are connected. As a result, the reference voltage V51 is output from the output line DAO.

As described above, the switch circuit 9 shown in FIG. 2 can perform a selection operation in which one of 64 reference voltages is selected and output in accordance with a 6-bit signal, similarly to the conventional circuit shown in FIG. In addition, since the transistors are shared in the 32 signal path groups, the number of transistors used can be greatly reduced compared to the conventional circuit shown in FIG. In other words, 384 (= 6 × 2 ⁶ ) transistors are used in the conventional circuit shown in FIG. 11, whereas 224 (= 6 × 2 ⁶ −5 × 2 ⁵ ) are used in the switch circuit 9 shown in FIG. ), And the number of transistors used can be reduced by 160.
Therefore, by configuring the digital-analog conversion circuit using the switch circuit 9 shown in FIG. 2, the circuit scale can be greatly reduced as compared with the conventional case.

  In addition, since the number of transistors included in the circuit can be reduced, current consumption caused by leakage current or the like is reduced, so that power consumption can be reduced. Furthermore, the production rate can be improved because the defect occurrence rate at the time of manufacture decreases due to the decrease in the number of circuit elements.

  Next, a second configuration example of the switch circuit 9 will be described with reference to FIG.

3 includes an input line V0,..., V63, an output line DAO, 64 transistors Q0-0,..., Q63-0, and 32 transistors Q1-1, Q3-1, Q5-1, Q7-1, ..., Q61-1, Q63-1, 16 transistors Q3-2, Q7-2, Q11-2, Q15-2, ..., Q59-2, Q63-2, 16 transistors Q3-3, Q7-3, Q11-3, Q15-3,..., Q59-3, Q63-3, and 16 transistors Q3-4, Q7-4, Q11-4, Q15-4 ,..., Q59-4, Q63-4 and 16 transistors Q3-5, Q7-5, Q11-5, Q15-5,..., Q59-5, Q63-5.
The transistor Qj-k is an n-type or p-type MOS transistor, and its conductivity type is defined in the same manner as described above.
The 64 transistors Q0-0 to Q63-0 have the same connection relationship as the circuit shown in FIG.
Similarly to the circuit shown in FIG. 2, the k-th bit signal bk is input to the gate of the transistor Qj-k.

The transistor Qr-1 (r represents any one of 16 integers {3, 7, 11, 15, 19,..., 63}) is connected between the node Ar and the node Br. The For example, transistor Q7-1 is connected between node A7 and node B7.
Transistor Q (r-2) -1 is connected between node A (r-2) and node Br. For example, transistor Q5-1 is connected between node A5 and node B7.

  Transistors Qr-2, Qr-3, Qr-4, and Qr-5 are connected in series between node Br and output line DAO. For example, transistors Q3-2, Q3-3, Q3-4, and Q3-5 are connected in series between node B3 and output line DAO.

The switch circuit 9 shown in FIG. 3 has 64 signal paths each composed of six transistors, similarly to the circuit shown in FIG.
These 64 signal paths are grouped into 16 signal path groups each composed of 4 signal paths. In detail,
(R0, R1, R2, R3), ..., (R60, R61, R62, R63);
In other words, the 64 signal paths R0 to R63 are grouped into 16 signal path groups.

Each signal path has two intersections with other signal paths belonging to the same set. Four transistors are connected in series between the intersection closest to the output line DAO and the output line DAO. These four transistors are shared by four signal paths.
From this intersection point, the signal path branches into two, and at the next intersection point, each signal path further splits into two, and is divided into four signal paths. These four signal paths are connected to four input lines. One transistor is connected between two adjacent intersections and between the intersection farthest from the output line DAO and the input line.

  Also in the switch circuit 9 shown in FIG. 3, as in the circuit shown in FIG. 2, one of the 64 signal paths R0 to R63 becomes conductive in response to the 6-bit signal (b0,..., B5). The rest becomes non-conductive.

As described above, the switch circuit 9 shown in FIG. 3 can perform the same selection operation as the conventional circuit shown in FIG. 11 and shares the transistors in the 16 signal path groups. The number of transistors used can be further reduced as compared with the circuit shown in FIG. That is, the switch circuit 9 shown in FIG. 3 requires only 160 (= 6 × 2 ⁶ −5 × 2 ⁵ −4 × 2 ⁴ ) transistors, and further reduces 64 transistors compared to the circuit shown in FIG. be able to.
Therefore, by configuring the digital-analog conversion circuit using the switch circuit 9 shown in FIG. 3, the circuit scale can be further reduced as compared with the prior art.

  Next, a third configuration example of the switch circuit 9 will be described with reference to FIG.

4 includes an input line V0,..., V63, an output line DAO, 64 transistors Q0-0,..., Q63-0, and 32 transistors Q1-1, Q3-1. Q5-1, Q7-1, ..., Q61-1, Q63-1, 16 transistors Q3-2, Q7-2, Q11-2, Q15-2, ..., Q59-2, Q63-2, Eight transistors Q7-3, Q15-3, Q23-3,..., Q55-3, Q63-3, four transistors Q15-4, Q31-4, Q47-4, Q63-4, and two Transistors Q31-5 and Q63-5.
The transistor Qj-k is an n-type or p-type MOS transistor, and its conductivity type is defined in the same manner as described above.
The 64 transistors Q0-0 to Q63-0 have the same connection relationship as the circuit shown in FIG. 32 transistors Q1-1, Q3-1, Q5-1, Q7-1,..., Q61-1, Q63-1 have the same connection relationship as the circuit shown in FIG.
Similarly to the circuit shown in FIG. 2, the k-th bit signal bk is input to the gate of the transistor Qj-k.

The transistor Qs-2 (s represents any one of eight integers {7, 15, 23, 31, 39, 47, 55, 63}) is connected between the node Bs and the node Cs. Connected. For example, the transistor Q7-2 is connected between the node B7 and the node C7.
Transistor Q (s-4) -2 is connected between node B (s-4) and node Cs. For example, transistor Q3-2 is connected between node B3 and node C7.

Transistor Qt-3 (t represents any one of four integers {15, 31, 47, 63}) is connected between node Ct and node Dt. For example, the transistor Q15-3 is connected between the node C15 and the node D15.
The transistor Q (t-8) -3 is connected between the node C (t-8) and the node Dt. For example, the transistor Q7-3 is connected between the node C7 and the node D15.

The transistor Qu-4 (u represents 31 or 63) is connected between the node Du and the node Eu. For example, the transistor Q31-4 is connected between the node D31 and the node E31.
Transistor Q (u-16) -4 is connected between node D (u-16) and node Eu. For example, the transistor Q15-4 is connected between the node D15 and the node E31.

Transistor Q31-5 is connected between node E31 and output line DAO.
Transistor Q63-5 is connected between node E63 and output line DAO.

The switch circuit 9 shown in FIG. 4 has 64 signal paths each composed of six transistors, similarly to the circuit shown in FIG.
These 64 signal paths are grouped into two signal path groups each composed of 32 signal paths. In detail,
(R0, R1, ..., R31), (R32, R33, ..., R63);
In other words, the 64 signal paths R0 to R63 are grouped into two signal path groups.

Each signal path has five intersections with other signal paths belonging to the same set. One transistor is connected between the intersection closest to the output line DAO and the output line DAO, and this transistor is shared by 32 signal paths.
From this intersection, the signal path branches into two, and at the next intersection, each signal path further branches into two. By repeating this, 32 signal paths are divided through 5 intersections. These 32 signal paths are connected to 32 input lines. One transistor is connected between two adjacent intersections and between the intersection farthest from the output line and the input line.

  Also in the switch circuit 9 shown in FIG. 4, as in the circuit shown in FIG. 2, one of the 64 signal paths R0 to R63 becomes conductive in response to the 6-bit signal (b0,..., B5). The rest becomes non-conductive.

As described above, the switch circuit 9 shown in FIG. 4 can perform the same selection operation as the conventional circuit shown in FIG. 11 and shares the transistors in the 32 signal path groups. The number of transistors used can be further reduced as compared with the circuit shown in FIG. That is, in the switch circuit 9 shown in FIG. 4, 126 transistors (= 6 × 2 ⁶ −5 × 2 ⁵ −4 × 2 ⁴ −3 × 2 ³ −2 × 2 ² −1 × 2 ¹ ) are sufficient, Compared with the circuit shown in FIG. 3, the number of transistors used can be further reduced by 34.
Therefore, by configuring the digital-analog conversion circuit using the switch circuit 9 shown in FIG. 4, the circuit scale can be further reduced as compared with the prior art.

  Next, a fourth configuration example of the switch circuit 9 will be described with reference to FIG.

  In the circuit shown in FIG. 2 described above, five switches controlled by the upper 5-bit signal among the 6-bit signals (b0,..., B5) are shared by the two signal paths. In the circuit shown in FIG. 5, five switches controlled by the lower 5-bit signal are shared by two signal paths.

5 includes an input line V0,..., V63, an output line DAO, 64 transistors Q0-5,..., Q63-5, and 32 transistors Q32-0,. 0, 32 transistors Q32-1,..., Q63-1, 32 transistors Q32-2,..., Q63-2, 32 transistors Q32-3,. Transistors Q32-4,..., Q63-4.
The transistor Qj-k is an n-type or p-type MOS transistor, and its conductivity type is defined in the same manner as described above.
Similarly to the circuit shown in FIG. 2, the k-th bit signal bk is input to the gate of the transistor Qj-k.

The transistor Qv-5 (v is an integer from 32 to 63; the same applies hereinafter) is connected between the input line Vv and the node Fv. For example, the transistor Q62-5 is connected between the input line V62 and the node F62.
The transistor Q (v-32) -5 is connected between the input line V (v-32) and the node Fv. For example, the transistor Q1-5 is connected between the input line V1 and the node F33.

  Transistors Qv-5, Qv-4, Qv-3, Qv-2, and Qv-1 are connected in series between node Fv and output line DAO. For example, the transistors Q33-4, Q33-3, Q32-2, Q31-1, and Q33-0 are connected in series between the node F33 and the output line DAO.

The switch circuit 9 shown in FIG. 5 has 64 signal paths each composed of six transistors, similarly to the circuit shown in FIG.
These 64 signal paths are grouped into 32 signal path groups each composed of 2 signal paths. In detail,
(R0, R32), (R2, R33), ..., (R30, R62), (R31, R63);
In other words, the 64 signal paths R0 to R63 are grouped into 32 signal path groups.

  Each signal path has one intersection with another signal path belonging to the same set. Five transistors are connected in series between this intersection and the output line DAO. For example, five transistors Q62-4, Q62-3, Q62-2, Q62-1, and Q62-0 are connected in series between the node F62, which is the intersection of the signal paths R30 and R62, and the output line DAO. Yes. The five transistors are shared by signal paths R30 and R62.

  Also in the switch circuit 9 shown in FIG. 5, as in the circuit shown in FIG. 2, one of the 64 signal paths R0 to R63 becomes conductive in response to the 6-bit signal (b0,..., B5). The rest becomes non-conductive.

As described above, the switch circuit 9 shown in FIG. 5 can execute the reference voltage selection operation similar to the circuit shown in FIG. 2, and the number of transistors used is 224, which is the same as the circuit shown in FIG.
Therefore, by configuring the digital-analog conversion circuit using the switch circuit 9 shown in FIG. 5, the circuit scale can be greatly reduced as compared with the conventional circuit.

  Next, a fifth configuration example of the switch circuit 9 will be described with reference to FIG.

  The switch circuit 9 shown in FIG. 6 is obtained by replacing the switch by one MOS transistor used in the circuit shown in FIG. 2 with a CMOS switch constituted by a parallel circuit of an n-type MOS transistor and a p-type MOS transistor. is there.

  The switch circuit 9 shown in FIG. 6 has the same configuration as the circuit shown in FIG. 2, and further includes 64 transistors Qx0-0,..., Qx63-0 and 32 transistors Qx1-1, Qx3-1, Qx5. -1, Qx7-1, ..., Qx61-1, Qx63-1, and 32 transistors Qx1-2, Qx3-2, Qx5-2, Qx7-2, ..., Qx61-2, Qx63-2, 32 Qx1-3, Qx3-3, Qx5-3, Qx7-3,..., Qx61-3, Qx63-3, 32 transistors Qx1-4, Qx3-4, Qx5-4, Qx7-4, ..., Qx61-4, Qx63-4, and 32 transistors Qx1-5, Qx3-5, Qx5-5, Qx7-5, ..., Qx61-5, Qx63-5.

The transistor Qxj-k is a MOS transistor having a conductivity type opposite in polarity to the transistor Qj-k. For example, the transistor Q0-0 is a p-type MOS transistor, whereas the transistor Qx0-0 is an n-type transistor.
The transistor Qxj-k is connected in parallel with the transistor Qj-k, and a signal xbk having a level complementary to the k-th bit signal bk is input to the gate of the transistor Qxj-k. When the signal bk is set to the high level, the signal xbk is set to the low level, and when the signal bk is set to the low level, the signal xbk is set to the high level.

  Since the switch circuit 9 shown in FIG. 6 uses a CMOS switch for each switch, the on-resistance of each switch can be reduced as compared with the circuit shown in FIG. Therefore, the signal delay is reduced as compared with the circuit shown in FIG. 2, and the operation can be speeded up.

<Second Embodiment>
Next, a second embodiment of the present invention will be described.

FIG. 7 is a diagram showing an example of the configuration of a display device according to the second embodiment of the present invention.
The display device shown in FIG. 7 includes a pixel unit 2, horizontal drive circuits 3A and 3B, a vertical drive circuit 4, a data processing unit 5, and a timing generator 6.
The pixel unit 2 is an embodiment of the pixel unit of the present invention.

  The pixel unit 2 includes a plurality of pixels including an electro-optical element such as a liquid crystal cell. The switching elements and electrodes of TFTs constituting these pixels are arranged in a matrix on a substrate 1 made of glass, plastic or the like. For example, in the case of a liquid crystal display device, a pixel is configured by holding a liquid crystal layer between a substrate (not shown) disposed to face the substrate 1.

The horizontal drive circuits 3A and 3B latch pixel signals P_DAT sequentially input in synchronization with the horizontal timing signal HCK for each horizontal line, and pixels for one horizontal line of the pixel unit 1 based on the latched pixel signal. Drive.
For example, among all the pixels on one horizontal line, the even-numbered pixel from the end is driven by the horizontal drive circuit 3A, and the odd-numbered pixel is driven by the horizontal drive circuit 3B.

  The vertical drive circuit 4 outputs a drive signal for selecting a horizontal line to be driven by the pixel unit 2 in synchronization with the vertical timing signal VCK. The horizontal drive circuits 3A and 3B drive pixels on the horizontal line selected by the vertical drive circuit 4.

The data processing unit 5 performs parallel conversion on the serially input image data Din in synchronization with the system clock signal SCK to generate a pixel signal P_DAT.
The timing generator 6 generates various signals (horizontal timing signal HCK, vertical timing signal VCK, system clock signal SCK, etc.) that define the operation timing of each circuit in synchronization with the input clock signal MCK.

  The horizontal drive circuits 3A and 3B, the vertical drive circuit 4, the data processing unit 5, and the timing generator 6 are integrally formed on the same substrate 1 as the pixel unit 2, and the peripheral area of the pixel unit 2 as shown in FIG. (Frame). In the example of FIG. 7, the horizontal drive circuits 3 </ b> A and 3 </ b> B are respectively arranged at positions facing each other with the pixel unit 2 interposed therebetween.

FIG. 8 is a diagram showing an example of the configuration of the horizontal drive circuits 3A and 3B.
8 includes registers 6-1, 6-2, 6-3,..., First latch circuits 7-1, 7-2, 7-3,. , Switch circuits 9-1, 9-2, 9-3,..., Buffer circuits 10-1, 10-2, 10-3,. Circuit 11.
The reference voltage output circuit 11 is an embodiment of the reference voltage output circuit of the present invention.
The switch circuits 9-1, 9-2, 9-3,... Are an embodiment of the switch circuit of the present invention.
Buffer circuits 9-1, 9-2, 9-3,... Are an embodiment of the drive circuit of the present invention.

  Registers 6-1, 6-2, 6-3,... Constitute a shift register circuit that generates horizontal scanning pulses SP1, SP2, SP3,... For sampling the pixel signal of each pixel on one horizontal line. When the pulse signal HST is supplied from the timing generator 6 at the beginning of one horizontal scanning period, the registers 6-1, 6-2,... Are synchronized with the horizontal timing signal HCK and the signal XHCK of the opposite phase to this pulse. The signal is sequentially shifted to the subsequent stage. The pulse signals transferred to the registers 6-1, 6-2,... Are input to the latch circuits 7-1, 7-2, 7-3,.

The first latch circuits 7-1, 7-2, 7-3,... Horizontally output grayscale data (6 bits) for one color from the pixel signal P_DAT for one pixel that is serially input by 18 bits. It samples and holds in synchronization with the scanning pulses SP1, SP2, SP3. When one horizontal scanning pulse becomes active, the corresponding three first latch circuits operate to simultaneously sample the gradation data for three colors of one pixel.
The entire first latch circuits 7-1, 7-2, 7-3,... Hold pixel signals for driving even-numbered or odd-numbered pixels among pixels on one horizontal line.

  The second latch circuits 8-1, 8-2, 8-3,... Are synchronized with the data transfer signal Oe that becomes active after the end of one horizontal scanning period, The pixel signals held in 7-3,... Are input and held.

  The reference voltage output circuit 11 is a circuit that outputs 64 reference voltages, and has, for example, the same configuration as the same reference numeral in FIG.

The switch circuits 9-1, 9-2, 9-3,... Are based on 6-bit gradation data supplied from the second latch circuits 8-1, 8-2, 8-3,. One of the 64 reference voltages output from the output circuit 11 is selected and output.
The switch circuits 9-1, 9-2, 9-3,... Have the same configuration as the switch circuit 9 described in the previous embodiment.

  The buffer circuits 10-1, 10-2, 10-3,... Receive voltages output from the switch circuits 9-1, 9-2, 9-3,..., And output voltages corresponding to the input voltages. Vout is generated. Each pixel of the pixel unit 1 is driven by the voltage output from the buffer circuits 9-1, 9-2, 9-3,.

  Next, the operation of the display device shown in FIGS. 7 and 8 having the above-described configuration will be described with reference to timing charts of FIGS. 9 and 10.

  As shown in FIG. 9A, the 18-bit pixel signal P_DAT for one pixel is supplied to the horizontal timing signals HCK and XHCK (see FIG. 9B) in the signal bus for pixel signal transfer of the horizontal drive circuits 3A and 3B. , (C)) and sequentially input. On the other hand, when the pulse signal HST is generated at the beginning of one horizontal scanning period, the pulse signal sequentially shifts the registers 6-1, 6-2,. 9D, 9E, and 9F occur in order. The pixel signals P_DAT sequentially input to the signal bus are sampled in order to the first latch circuits 7-1, 7-2, 7-3,... According to the horizontal scanning pulses SP 1, SP 2, SP 3. Thus, at the end of one horizontal scanning period, the entire first latch circuits 7-1, 7-2, 7-3,..., Pixels on one horizontal line (pixels corresponding to even-numbered or odd-numbered pixels). ) Pixel signal is held.

  When one horizontal scanning period ends, the timing generator 6 sets the data transfer signal Oe (FIG. 9G) to active. As a result, the pixel signals held in the first latch circuits 7-1, 7-2, 7-3,... Are transferred all at once to the second latch circuits 8-1, 8-2, 8-3,. The From the switch circuits 9-1, 9-2, 9-3,..., 64-gradation voltages corresponding to new data transferred to the second latch circuits 8-1, 8-2, 8-3,. Are output from the buffer circuits 9-1, 9-2, 9-3,... To each pixel of the pixel unit 1.

The data latching operation in the first latch circuits 7-1, 7-2, 7-3,..., The first latch circuits 7-1, 7-2, 7-3,. The data transfer operation to −2, 8-3,... And the data write operation to each pixel are repeatedly executed in synchronization with the vertical timing signal VCK (FIG. 10A).
For example, in parallel with the operation of writing the pixel signal to the i-th line of the pixel unit 1 (FIG. 10C), the pixel signal of the next (i + 1) -th line is converted to the first latch circuits 7-1, 7-2, 7-3,... (FIG. 10E) is executed. When the pixel signal writing operation and the pixel signal capturing operation are completed and the data transfer signal Oe becomes active, the (i + 1) th line captured by the first latch circuits 7-1, 7-2, 7-3,. Are transferred to the second latch circuits 8-1, 8-2, 8-3,... (FIG. 10E). Then, in the next horizontal scanning period, in parallel with the operation of writing the pixel signal to the (i + 1) th line, the operation of taking in the pixel signal of the next (i + 2) th line is executed.

According to the display device according to the present embodiment, since the circuit scale of the digital-analog conversion circuit used in the horizontal drive circuit can be reduced, the width of the frame required at the periphery of the pixel unit 1 in order to arrange these circuits. Can be narrowed.
In addition, since the number of circuit elements can be reduced, power consumption can be reduced and production yield can be improved.

  As mentioned above, although embodiment of this invention was described in detail, this invention is not limited only to said form, A various modification | change is possible.

  In the above-described embodiment, a 6-bit digital-analog conversion circuit is taken as an example, but the present invention is not limited to this. That is, the bit length of the input signal can be arbitrarily set.

  In the above-described embodiment, an example in which a switch is shared by two, four, and thirty-two signal paths is given. However, the present invention is not limited to this, and a switch on the path can be shared by an arbitrary number of signal paths. Is possible.

  In the above-described embodiment, an example is described in which a MOS transistor is used as a switch. However, the present invention is not limited to this, and any switch element such as a bipolar transistor can be used.

It is a figure which shows an example of a structure of the digital analog conversion circuit which concerns on the 1st Embodiment of this invention. It is a figure which shows the 1st structural example of a switch circuit. It is a figure which shows the 2nd structural example of a switch circuit. It is a figure which shows the 3rd structural example of a switch circuit. It is a figure which shows the 4th structural example of a switch circuit. It is a figure which shows the 5th structural example of a switch circuit. It is a figure which shows an example of a structure of the display apparatus which concerns on the 2nd Embodiment of this invention. It is a figure which shows an example of a structure of a horizontal drive circuit. FIG. 9 is a first timing chart for explaining the operation of the horizontal drive circuit shown in FIG. 8. FIG. FIG. 9 is a second timing chart for explaining the operation of the horizontal drive circuit shown in FIG. 8. FIG. It is a figure which shows an example of the main structures of the conventional reference voltage selection type digital analog conversion circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Board | substrate, 2 ... Pixel part, 3A, 3B ... Horizontal drive circuit, 4 ... Vertical drive circuit, 5 ... Data processing part, 6 ... Timing generator, 6-1, 6-2 ... Register, 7-1-7- 6, 8-1 to 8-6 ... latch circuit, 9, 9-1 to 9-6 ... switch circuit, 10, 10-1 to 10-6 ... buffer circuit, 11 ... reference voltage output circuit, Qj-k, Qxj-k (j = 0 to 63, k = 0 to 5)... MOS transistor.

Claims (9)

A reference voltage output circuit that outputs 2 ⁿ (n represents an arbitrary integer greater than 1) reference voltage;
Has 2 ⁿ input lines and one output line for inputting the 2 ⁿ pieces of reference voltage output from the reference voltage output circuit, in response to a signal n bits input, the 2 ⁿ pieces A switch circuit that selects any one of the input lines and connects the selected input line to the output line,
The switch circuit is configured between the 2 ⁿ input lines and the output line, and has 2 ⁿ signal paths in which any one of the switch circuits is turned on according to the n-bit signal,
Each signal path includes n switches connected in series to each other and controlled to be turned on and off according to the n-bit signal.
At least some of the 2 ⁿ signal paths share some of the n switches;
Digital analog conversion circuit. One or more switches shared by the plurality of signal paths are connected between an intersection of the plurality of signal paths and the output line.
The digital-analog conversion circuit according to claim 1. The 2 ⁿ signal paths have at least one set of 2 ^k signal paths (k represents an arbitrary integer from 1 to n) sharing a part of the n switches,
Each signal path has k intersections with other signal paths belonging to the same set,
The digital-analog conversion circuit according to claim 1. Each of the switches includes either a first conductivity type transistor or a second conductivity type transistor.
The digital-analog conversion circuit according to claim 1. The first conductivity type transistor inputs a 1-bit signal among the n-bit signals, and turns on when the input signal has a first level, and turns off when the input signal has a second level.
The second conductivity type transistor inputs a 1-bit signal among the n-bit signals, and is turned off when the input signal has the first level, and turned on when the input signal has the second level. To
The digital-analog conversion circuit according to claim 4. Each of the switches includes a parallel circuit of a first conductivity type transistor and a second conductivity type transistor.
The digital-analog conversion circuit according to claim 1. Each bit signal constituting the n-bit signal has a first signal and a second signal having complementary levels,
Each of the switches receives a first parallel circuit in which a first conductivity type transistor that inputs the first signal and a second conductivity type transistor that inputs the second signal are connected in parallel, or inputs the second signal. Including any one of a second parallel circuit in which a first conductivity type transistor and a second conductivity type transistor that inputs the first signal are connected in parallel;
The first conductivity type transistor is turned on when an input signal has a first level, and turned off when it has a second level.
The second conductivity type transistor is turned off when the input signal has the first level, and turned on when the input signal has the second level.
The digital-analog conversion circuit according to claim 6. A pixel portion having a plurality of pixels arranged in a matrix;
A digital-analog conversion circuit that converts an input n-bit signal into an analog signal;
A drive circuit for driving each pixel of the pixel unit based on an analog signal output from the digital-analog conversion circuit,
The digital-analog converter circuit is
A reference voltage output circuit that outputs 2 ⁿ (n represents an arbitrary integer greater than 1) reference voltage;
Has 2 ⁿ input lines and one output line for inputting the 2 ⁿ pieces of reference voltage output from the reference voltage output circuit, in response to a signal n bits input, the 2 ⁿ pieces A switch circuit that selects the input line and connects the selected input line to the output line. The switch circuit includes the ²ⁿ input lines and the output line. And 2 ⁿ signal paths, one of which is in a conductive state according to the n-bit signal,
Each signal path includes n switches connected in series to each other and controlled to be turned on and off according to the n-bit signal.
At least some of the 2 ⁿ signal paths share some of the n switches;
Display device. The digital-analog conversion circuit is formed on a common substrate with the pixel portion.
The display device according to claim 8.

Images