JP2012083523A - Drive unit for display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To highly increase the operating speed of a drive unit for a display device while restraining wasteful consumption of power.SOLUTION: The drive unit for the display device comprises: a plurality of PMOS transistors 52 and NMOS transistors 54 between a decoder circuit 36 for switching the potential of a output signal line 60 to a target potential corresponding to display data and the display device to which the potential of the output signal line 60 is supplied as a data voltage, the PMOS transistors 52 being configured to connect the output signal line 60 to a power source until the potential of the output signal line 60 reaches a gate potential, the NMOS transistors 54 being configured to connect the output signal line 60 to a ground line until the potential of the output signal line 60 reaches the gate potential. Different gate potentials are supplied to the corresponding transistors. In a case where the potential of the output signal line 60 is lower than a target potential, the PMOS transistor 52 whose gate potential is equal to or below the target potential and closest to the target potential among the n types of potentials is actuated. In a case where the potential of the output signal line 60 is higher than the target potential, the NMOS transistor 54 whose gate potential is equal to or higher than the target potential and closest to the target potential among the n types of potentials is actuated.

Description

  The present invention relates to a display device drive device, and more particularly, to a display device drive device that drives a display device by supplying a voltage corresponding to display data to the display device.

  A plurality of data lines are provided along the X direction, a plurality of gate lines are provided along the Y direction, and display cells (pixels) are provided at intersections between the individual data lines and the individual gate lines. An active matrix display device (for example, TFT (Thin Film Transistor) -LCD (Liquid Crystal Display)) has a source driver for driving data lines and a gate driver for driving gate lines. Connected drive unit. In this type of driving device, display data for one line including pixels corresponding to the same gate line is sequentially input from a data source such as a graphic processor in each cycle of the horizontal synchronizing signal.

  The source driver of the driving device transfers the display data for one line sequentially input from the data source in each cycle of the horizontal synchronization signal by the shift register and holds it in the latch, and one line input in the previous cycle. A data voltage corresponding to the display data is generated by a level shifter, a decoder circuit, and an amplifier circuit, and the generated data voltage is supplied to each data line and written to each pixel for one line. The gate driver of the driving device supplies a gate signal to a single gate line and switches the gate line supplying the gate signal at each cycle of the horizontal synchronization signal. As a result, the display device is driven, and an image represented by the display data is displayed on the display device.

  In relation to the above, Patent Document 1 discloses that a voltage in which the level of a gradation voltage corresponding to display data is shifted is generated between a decoder circuit of a drain driver and an output amplifier circuit, and the generated voltage is stored in a precharge period. A configuration in which a precharge circuit for supplying a drain signal line is provided is disclosed.

  Patent Document 2 further includes a second decoder that selects and outputs a precharge voltage corresponding to image data from a plurality of precharge voltages, and supplies the precharge voltage output from the second decoder to the data line. Techniques to do this are disclosed.

Japanese Patent Laid-Open No. 2001-166741 JP 2009-139538 A

  By the way, with the increase in the operation speed of the display device, the drive device that drives the display device is also required to increase the operation speed. As shown in FIG. 6A as an example, the source driver of the above driving device has conventionally had the lowest operating speed of an amplifier circuit composed of an operational amplifier among the constituent elements of the source driver, and the output delay of the amplifier circuit is low. This was a major impediment to improving the operating speed of the source driver. On the other hand, as a result of recent technological improvements around the amplifier circuit, the output delay of the amplifier circuit is greatly increased, as shown in FIG. It has become smaller. However, along with this, the delay of the output of the decoder circuit located in the previous stage of the amplifier circuit instead of the delay of the output of the amplifier circuit has become a major impediment to the improvement of the operating speed of the source driver, However, the operating speed of the source driver is not sufficiently improved even though the output delay of the amplifier circuit is significantly reduced.

  On the other hand, the technique described in Patent Document 1 is effective in improving the operation speed of the source driver because the potential of the drain signal line (data line) on the output side of the decoder circuit is changed by the precharge circuit. It is done. However, in the technique described in Patent Document 1, the data line is not changed until the precharge period ends regardless of whether the potential of the data line (drain signal line) has reached the precharge potential (PC potential) or not. As shown in FIG. 11 of Patent Document 1, especially for the near-end pixel close to the source driver, even after the potential of the data line reaches the PC potential. A voltage is supplied to the data line for a relatively long period, and there is a problem that wasteful power consumption occurs. Further, as shown in FIG. 11 of Patent Document 1, the technique described in Patent Document 1 raises the potential of the data line once to a PC potential higher than the final potential, and then decreases it to the final potential. Thus, temporarily raising the potential of the data line to the PC potential also leads to an increase in useless power consumption.

  As is clear from the technique described in Patent Document 2, the precharge period ends regardless of whether or not the potential of the data line has reached the precharge potential, as is clear from FIGS. 3 and 6 of Patent Document 2. In the meantime, since the supply of the precharge voltage to the data line is continued, there is a problem that wasteful power consumption occurs as in the technique described in Patent Document 1.

  The present invention has been made in consideration of the above-described facts, and an object of the present invention is to obtain a display device driving device capable of realizing an increase in operating speed while suppressing wasteful power consumption.

  In order to achieve the above object, a drive device for a display device according to claim 1 comprises a potential switching section for switching the potential of the drive signal line to a target potential corresponding to display data, and the potential of the drive signal line is a voltage. First switching means for connecting the drive signal line to a power source until the potential of the drive signal line reaches a first reference potential higher than the potential. And between the potential switching unit and the display device, the drive signal line is connected to a ground line until the potential of the drive signal line reaches a second reference potential lower than the potential. When the potential of the switching means 2 and the drive signal line is lower than the target potential, a potential equal to or lower than the target potential and closest to the target potential among predetermined n types (n ≧ 1) of potentials. The first reference potential When the first switching means is operated and the potential of the drive signal line is higher than the target potential, the potential that is equal to or higher than the target potential and is closest to the target potential is selected from the n types of potentials as the second reference. Control means for operating the second switching means as a potential.

  According to the first aspect of the present invention, the drive signal line is provided between the potential switching unit that switches the potential of the drive signal line to the target potential corresponding to the display data and the display device to which the potential of the drive signal line is supplied as a voltage. The first switching means for connecting the drive signal line to the power supply and the potential of the drive signal line reach the second reference potential lower than the potential until the potential reaches the first reference potential higher than the potential. And a second switching means for connecting the drive signal line to the ground line. Then, when the potential of the drive signal line is lower than the target potential, the control means uses, as a first reference potential, a potential that is equal to or lower than the target potential and is closest to the target potential among predetermined n types (n ≧ 1) of potentials. When the first switching means is operated and the potential of the drive signal line is higher than the target potential, the second switching means is set to a second reference potential that is equal to or higher than the target potential among the n types of potentials. Is activated.

  Thus, according to the first aspect of the present invention, when the potential of the drive signal line is lower than the target potential, the potential of the drive signal line is equal to or lower than the target potential and is closest to the target potential among n types of potentials. Until the first reference potential is reached, the drive signal line is connected to the power source by the first switching means, so that the time until the potential of the drive signal line reaches the target potential is shortened. Further, when the potential of the drive signal line is higher than the target potential, the potential of the drive signal line is lowered to the second reference potential that is equal to or higher than the target potential and closest to the target potential among n types of potentials. In the meantime, the drive signal line is connected to the ground line by the second switching means, whereby the time until the potential of the drive signal line reaches the target potential is shortened. As a result, it is possible to increase the operating speed of the display device driving device according to the present invention.

  The first switching means is configured to connect the drive signal line to the power source until the potential of the drive signal line reaches the first reference potential, and when the potential of the drive signal line reaches the first reference potential. The connection between the drive signal line and the power source is interrupted. Also, the second switching means is configured to connect the drive signal line to the ground line until the potential of the drive signal line reaches the second reference potential, and the potential of the drive signal line reaches the second reference potential. Then, the connection between the drive signal line and the ground line is cut off. Therefore, wasteful power consumption can be suppressed as compared with a configuration in which a voltage is supplied to the drive signal line for a certain period regardless of whether the potential of the drive signal line has reached a certain potential.

  In the invention described in claim 1, for example, as described in claim 2, a plurality of first switching means are provided, and each of the first switching means has different potentials among n types of potentials. It may be configured to be supplied as one reference potential. In this configuration, when the potential of the drive signal line is lower than the target potential, the first switching means is operated with a potential that is equal to or lower than the target potential and is closest to the target potential among the n types of potentials as the first reference potential. More specifically, for example, when the potential of the drive signal line is lower than the target potential, the control unit supplies, as the first reference potential, a potential that is equal to or lower than the target potential and is closest to the target potential among the plurality of first switching means. This can be realized by configuring the first switching means to be operated.

  In the invention according to claim 2, for example, as described in claim 3, when the third switching means is provided between each of the first switching means and the power source, a plurality of first switching means are provided. Among the switching means, operating the first switching means that is supplied with a potential equal to or lower than the target potential and closest to the target potential as a first reference potential is more specifically described. For example, the control means includes a plurality of third switching means. Among these, it can be realized by turning on the third switching means provided between the specific first switching means to be operated and the power supply to operate the specific first switching means.

  In the invention according to any one of claims 1 to 3, for example, as described in claim 4, a plurality of second switching means are provided, and each of the second switching means has n types. Different potentials among the potentials may be supplied as the second reference potential. In this configuration, when the potential of the drive signal line is higher than the target potential, the second switching means is operated with the potential that is equal to or higher than the target potential and is closest to the target potential among the n types of potentials as the second reference potential. More specifically, for example, when the potential of the drive signal line is higher than the target potential, the control unit supplies, as the second reference potential, a potential that is equal to or higher than the target potential and is closest to the target potential among the plurality of second switching units. This can be realized by configuring the second switching means to be operated.

  In the invention according to claim 4, for example, as described in claim 5, when the fourth switching means is provided between each of the second switching means and the ground line, a plurality of second switching means is provided. Among the two switching means, operating the second switching means to which the potential equal to or higher than the target potential and closest to the target potential is operated is more specifically described. Realized by configuring the specific second switching means to operate by turning on the fourth switching means provided between the specific second switching means to be activated and the ground line. it can.

  Further, in the invention according to any one of claims 1, 4, and 5, as described in claim 6, for example, the first switching means has any one of n kinds of potentials. The potential may be selectively supplied as the first reference potential. In this configuration, when the potential of the drive signal line is lower than the target potential, the first switching means is operated with a potential that is equal to or lower than the target potential and is closest to the target potential among n types of potentials as the first reference potential. More specifically, for example, when the potential of the drive signal line is lower than the target potential, the control means uses a potential that is equal to or lower than the target potential and is closest to the target potential among the n types of potentials to the first switching potential. It is realizable by comprising so that it may be supplied as.

  In the invention according to any one of claims 1, 4 and 5, for example, as described in claim 7, the second switching means has any one of n kinds of potentials. The potential may be selectively supplied as the second reference potential. In this configuration, when the potential of the drive signal line is higher than the target potential, the second switching means is operated with the potential that is equal to or higher than the target potential and is closest to the target potential among the n types of potentials as the second reference potential. More specifically, for example, when the potential of the drive signal line is higher than the target potential, the control means uses a potential that is equal to or higher than the target potential and is closest to the target potential among the n types of potentials to the second switching potential. It is realizable by comprising so that it may be supplied as.

  Further, in the invention according to any one of claims 1 to 7, for example, as described in claim 8, the first switching means includes a PMOS transistor having a back gate connected to the ground line. The switching means can include an NMOS transistor having a back gate connected to a power source.

  In the invention according to any one of claims 1 to 7, for example, as described in claim 9, the first switching means includes a PMOS transistor having a back gate connected to the drive signal line. The second switching means may include an NMOS transistor whose back gate is connected to the drive signal line. As described in claim 8, the back gate of the PMOS transistor is normally connected to the ground line, and the back gate of the NMOS transistor is usually connected to the power source. Therefore, as described above, when the back gates of the PMOS transistor of the first switching means and the NMOS transistor of the second switching means are connected to the drive signal line, it is necessary to separate these transistors from the other transistors. The circuit area increases.

  However, if the back gate of the PMOS transistor is connected to the ground line and the back gate of the NMOS transistor is connected to the power supply, a potential difference occurs between the back gate and the drive signal line (back bias is applied), and the potential of the drive signal line is There is a possibility of turning off at a timing slightly earlier than reaching the reference potential. On the other hand, when the back gate is connected to the drive signal line as described above, the back bias is not applied. Therefore, each of the above transistors is turned on until the drive signal line potential reaches the first reference potential or the second reference potential. The drive signal line can be turned on, and the state in which the drive signal line is connected to the power supply or the ground line can be continued until the potential of the drive signal line reaches the first reference potential or the second reference potential.

  In the invention according to claim 8 or 9, for example, as described in claim 10, a potential higher than the first reference potential by a predetermined value is supplied to the gate of the PMOS transistor of the first switching means. The NMOS transistor of the second switching means may be configured such that a potential higher than the second reference potential by a predetermined value is supplied to the gate. In this case as well, as in the ninth aspect of the invention, each of the transistors can be turned on until the potential of the drive signal line reaches the first reference potential or the second reference potential. The state in which the drive signal line is connected to the power supply or the ground line can be continued until the timing when the first reference potential or the second reference potential is reached.

  In the invention according to any one of claims 1 to 10, when an amplifier circuit is further provided between the potential switching unit and the display device, for example, as described in claim 11, the first The switching means and the second switching means can be configured to connect a portion of the drive signal line between the potential switching unit and the amplifier circuit to a power supply or a ground line.

  As described above, the present invention provides a drive signal between the potential switching unit that switches the potential of the drive signal line to the target potential corresponding to the display data and the display device to which the potential of the drive signal line is supplied as a voltage. The first switching means for connecting the drive signal line to the power supply until the potential of the line reaches a higher first reference potential and the drive until the potential of the drive signal line reaches a lower second reference potential. Second switching means for connecting the signal line to the ground line, and when the potential of the drive signal line is lower than the target potential, the potential that is equal to or lower than the target potential and is closest to the target potential among the n types of potentials. When the first switching means is operated as one reference potential and the potential of the drive signal line is higher than the target potential, the potential that is equal to or higher than the target potential and is closest to the target potential among the n types of potentials is set as the second reference potential. 2 switch Since the actuate the grayed means, the operation speed can be realized while suppressing wasteful power consumption and has an excellent effect that.

It is a block diagram which shows schematic structure of the drive device of the display apparatus demonstrated by embodiment with a display apparatus. 1 is a circuit diagram showing a configuration of a potential change auxiliary circuit according to a first embodiment. FIG. (A) is a diagram showing an example of a reference potential supplied to each of n potential change auxiliary circuits, and (B) and (C) are diagrams showing examples of potential changes of drive signal lines. It is a circuit diagram which shows the structure of the electric potential change auxiliary circuit which concerns on 2nd Embodiment. It is a circuit diagram which shows the structure of the electric potential change auxiliary circuit which concerns on 3rd Embodiment. FIG. 10 is a diagram for explaining a factor that hinders an improvement in operation speed in a display device drive device (source driver).

  Hereinafter, an example of an embodiment of the present invention will be described in detail with reference to the drawings.

[First Embodiment]
FIG. 1 shows a display device 10 that is a display device, and a drive device 12 that includes a gate driver 14 and a source driver 16 connected to the display device 10. The driving device 12 is an example of a driving device for a display device according to the present invention.

The display device 10 may be any of various known display devices as long as it is an active matrix type display device. For example, when the display device 10 is a TFT-LCD, the display device 10 is not illustrated but is predetermined. A liquid crystal is sealed between a pair of transparent substrates opposed to each other with an interval of, an electrode is formed on the entire surface of the opposite surface of one transparent substrate, and on the opposite surface of the other transparent substrate, FIG. A plurality of data lines arranged at regular intervals along the X direction and extending along the Y direction in FIG. 1 respectively, and arranged at regular intervals along the Y direction in FIG. 2 and extending along the X direction in FIG. A plurality of gate lines are provided, and a thin film transistor (TFT) and an electrode are arranged at the intersection (pixel position) of each data line and each gate line, and each TFT has a source. The gate is on the electrode The gate line and the drain are connected to the data line, respectively. Hereinafter, a case where the display device 10 is a TFT-LCD will be described as an example.
A gate driver 14 and a source driver 16 are provided. Each gate line of the display device 10 is connected to the gate driver 14, and each data line of the display device 10 is connected to the source driver 16. The gate driver 14 is connected to a timing controller (not shown), and in accordance with a gate driver control signal input from the timing controller, a gate signal is applied to any one of the multiple gate lines of the display device 10. Supplying for a predetermined time and turning on the TFTs of pixels for one line connected to the gate line for a predetermined time are repeated while sequentially switching the gate line for supplying the gate signal at the timing synchronized with the horizontal synchronizing signal.

  On the other hand, the source driver 16 includes a first latch circuit group 22 having the same number of latch circuits 24 as the number of pixels for one line of the shift register 20 and the same number of latch circuits 28 as the number of pixels for one line. In addition, the second latch circuit group 26, a level shifter group 30 having the same number of level shifters 32 as the number of pixels for one line, and a decoder circuit group 34, 1 having the same number of decoder circuits 36 as the number of pixels for one line. A potential change auxiliary circuit group 40 having the same number of potential change auxiliary circuits 42 as the number of pixels for one line and an amplifier circuit group 46 having the same number of amplifier circuits 48 as the number of pixels for one line are sequentially connected. Configured.

  The source driver 16 includes a drive device of this type in which display data for one line composed of pixels corresponding to the same gate line of the display device 10 is supplied to a data source such as a graphic processor in each cycle of the horizontal synchronization signal. Are sequentially input in units of pixels. The shift register 20 sequentially transfers display data for one line that is sequentially input in units of pixels, and then outputs the display data to the first latch circuit group 22. As a result, each latch circuit 24 of the first latch circuit group 22 holds display data for one pixel different from the display data for one line.

  The second latch circuit group 26 is a level shifter for the display data held in the second latch circuit group 26 in parallel with the transfer of the display data by the shift register 20 and the holding of the display data to the first latch circuit group 22. The display data for one pixel held in each latch circuit 24 of the first latch circuit group 22 is used to perform signal processing by the circuits after the group 30. After being transferred and held in the latch circuit 28, it is output to the individual level shifters 32 of the level shifter group 30.

  Each level shifter 32 of the level shifter group 30 converts the voltage level of the display data input from the latch circuit 28 of the second latch circuit group 26 into a higher voltage level suitable for the operation of the subsequent decoder circuit 36, etc. The display data after the level conversion is output to each decoder circuit 36 of the decoder circuit group 34.

  The decoder circuit group 34 is provided with a gradation voltage generation unit 38 that generates a plurality of types of gradation voltages having different voltage levels. The plurality of types of gradation voltages generated by the gradation voltage generation unit 38 are Each is supplied to an individual decoder circuit 36. Each decoder circuit 36 selects a gradation voltage corresponding to display data for one pixel input from the previous level shifter 32 from a plurality of kinds of gradation voltages supplied from the gradation voltage generator 38. By changing the voltage level (potential) of the output signal line to the selected gradation voltage, the selected gradation voltage is output to the subsequent circuit. The individual potential change auxiliary circuits 42 of the potential change auxiliary circuit group 40 will be described later.

  Each amplifier circuit 48 of the amplifier circuit group 46 includes an operational amplifier (not shown) having an input terminal connected to the output signal line of the decoder circuit 36. The operational amplifier has a peripheral circuit connected to function as a voltage follower, and an output terminal connected to the data line. As a result, the voltage (data voltage) of the output signal line is amplified and supplied to the data line by the amplifier circuit 48 (the operational amplifier) without changing the voltage level.

  As a result, the data voltage supplied from each amplifier circuit 48 of the amplifier circuit group 46 to the data line is one line corresponding to the gate line to which the gate signal is supplied by the gate driver 14 among the lines of the display device 10. The light transmittance of the liquid crystal at the position of each pixel to which the data voltage is applied is changed according to the magnitude of the applied data voltage, so that an image for one line is displayed on the display device 10. Is displayed. Then, the gate line to which the gate signal is supplied by the gate driver 14 is sequentially switched, and the line to which the display data of the source driver 16 is input is sequentially switched, so that an image is displayed on the display device 10.

  Next, the potential change auxiliary circuit 42 provided in the potential change auxiliary circuit group 40 in the same number as the number of pixels for one line will be described with reference to FIG. FIG. 2 shows a single potential change auxiliary circuit 42 corresponding to a single pixel (data line). The potential change auxiliary circuit 42 includes n potential detection / changes (for example, n> 1). A circuit 50 is provided. The potential change auxiliary circuit group 40 is also provided with a switching control unit 44 including a reference potential supply unit 62 and a selection signal supply unit 64.

  Each potential detection / change circuit 50 includes a detection PMOS transistor 52 and an NMOS transistor 54, and a selection NMOS transistor 56 and a PMOS transistor 58. The detection PMOS transistor 52 has a drain connected to the output signal line 60, a source connected to the source of the selection NMOS transistor 56, a gate connected to the reference potential supply unit 62, and a back gate (also referred to as a substrate gate). ) Is connected to the ground line and maintained at the potential Vss. The detection NMOS transistor 54 has a drain connected to the output signal line 60, a source connected to the source of the selection PMOS transistor 58, a gate connected to the reference potential supply unit 62, and a back gate connected to the power supply. Thus, the potential VDD is maintained.

  The selection NMOS transistor 56 has a drain and a back gate connected to a power supply and maintained at the potential VDD, and a gate connected to the selection signal supply unit 64. The selection PMOS transistor 58 has a drain and a back gate connected to the ground line and maintained at the potential Vss, and a gate connected to the selection signal supply unit 64. Note that the number n of the potential detection / change circuits 50 provided in the single potential change auxiliary circuit 42 is, for example, an allowable circuit scale for the drive device 12 or an increase in operation speed for the drive device 12. It can be determined according to conditions such as degree.

  In addition, the reference potential supply unit 62 of the switching control unit 44 applies the minimum to the maximum value of the data voltage output from the decoder circuit 36 with respect to the detection PMOS transistor 52 and NMOS transistor 54 of the individual potential detection / change circuit 50. A voltage (potential) having a different voltage level within the value range and different for each potential detection / change circuit 50 among the n types of voltage levels is supplied to the gate as a reference potential Vref.

  As an example, FIG. 3A shows a reference supplied to the gates of the detection PMOS transistor 52 and the NMOS transistor 54 of each potential detection / change circuit 50 when the number n of potential detection / change circuits 50 is 3. An example of the potentials Vref1 to Vref3 is shown. In FIG. 3A, the potential Vmin is the data voltage output from the decoder circuit 36 when the minimum display data value Dmin is input, and the potential Vmax is the decoder when the maximum display data value Dmax is input. This is a data voltage output from the circuit 36. For example, as shown in FIG. 3A, the reference potential supply unit 62 sets the range (Vmin to Vmax) of the data voltage output from the decoder circuit 36 according to the number n of the potential detection / change circuits 50 ( = N + 1 = 4), the potential corresponding to the boundary of each range when equally divided into a plurality of ranges is applied to the detection PMOS transistor 52 and NMOS transistor 54 of each potential detection / change circuit 50 as a reference potential Vref. It can be configured to be supplied as

  The selection signal supply unit 64 of the potential detection / change circuit 50 receives display data after level conversion input to the decoder circuit 36 (instead of this, display data before level conversion may be input). ), Based on the input display data, the target potential in the change of the potential of the output signal line 60 by the decoder circuit 36 is recognized before the potential of the output signal line 60 is changed by the decoder circuit 36. The selection signal supply unit 64 holds the target potential of the output signal line 60 recognized in the previous cycle of the horizontal synchronization signal, and compares the recognized target potential with the target potential of the previous cycle, thereby It is determined whether the potential change direction of the output signal line 60 by the decoder circuit 36 in the cycle is an increase or decrease in potential.

  When the selection signal supply unit 64 determines that the change direction of the potential of the output signal line 60 is an increase in potential, the n types of potentials supplied to the n potential detection / change circuits 50 as the reference potential Vref. A potential that is lower than the recognized target potential and closest to the target potential is selected, and the selected potential is supplied to the gates of the detection PMOS transistor 52 and NMOS transistor 54 as the reference potential Vref. A selection signal for turning on the selection NMOS transistor 56 is supplied to the change circuit 50 to the gate of the selection NMOS transistor 56.

  When the selection signal supply unit 64 determines that the change direction of the potential of the output signal line 60 is a decrease in potential, the n types of potentials supplied to the n potential detection / change circuits 50 as the reference potential Vref. A potential that is equal to or higher than the recognized target potential and that is closest to the target potential is selected, and the selected potential is supplied to the gates of the detection PMOS transistor 52 and NMOS transistor 54 as the reference potential Vref. A selection signal for turning on the PMOS transistor 58 for selection is supplied to the gate of the PMOS transistor 58 for selection.

  In the first embodiment, the detection PMOS transistor 52 includes the first switching means according to the present invention (more specifically, the first switching means according to claims 2 and 11) and the eighth aspect. An NMOS transistor 54 for detection, which is an example of the PMOS transistor of the present invention, includes the second switching means according to the present invention (more specifically, the second switching means according to claims 4 and 11) and the NMOS transistor according to claim 8. The selection NMOS transistor 56 is an example of the third switching means according to claim 3, the selection PMOS transistor 58 is an example of the fourth switching means according to claim 5, and the switching control unit 44 is An example of the control means according to the present invention (more specifically, the control means according to claims 2 to 5), the decoder circuit 36 is the potential switching according to claim 1. An example of the amplification circuit 48 is an example of an amplifier circuit according to claim 11. The potential supplied to the gate of the detection PMOS transistor 52 is an example of a first reference potential, and the potential supplied to the gate of the detection NMOS transistor 54 is an example of a second reference potential.

  Next, the operation of this embodiment will be described. As described above, the decoder circuit 36 of the source driver 16 of the driving device 12 corresponds to one pixel input from the level shifter 32 in the previous stage from among the plurality of types of gradation voltages supplied from the gradation voltage generator 38. The gradation voltage corresponding to the display data is selected and the voltage level (potential) of the output signal line 60 is changed to the selected gradation voltage, but the speed at which the decoder circuit 36 changes the potential of the output signal line 60 (decoder circuit). The output speed of 36 is lower than the output speed of the other circuits of the source driver 16, which is a main impediment to improving the operating speed of the source driver 16. Therefore, the potential change auxiliary circuit group 40 is provided in the source driver 16 of the drive device 12 according to the present embodiment.

  When the selection signal supply unit 64 of the potential detection / change circuit 50 provided in the potential change auxiliary circuit group 40 determines that the potential change direction of the output signal line 60 is an increase in potential, n potential detection / change circuits are provided. 50 is selected from the n types of potentials supplied as the reference potential Vref to the reference potential Vref, and a potential that is equal to or lower than the recognized target potential and closest to the target potential is selected. A selection signal for turning on the selection NMOS transistor 56 is supplied to the gate of the selection NMOS transistor 56 to the potential detection / change circuit 50 supplied to the gate of the NMOS transistor 54.

  When the selection NMOS transistor 56 to which the selection signal is supplied to the gate is turned on, the detection PMOS transistor 52 connected to the selection NMOS transistor 56 is supplied with the potential of the output signal line 60 to the gate. Since the output signal line 60 is turned on until the reference potential Vref is reached, the output signal line 60 is supplied via the detection PMOS transistor 52 and the selection NMOS transistor 56 until the potential of the output signal line 60 reaches the reference potential Vref. Connected to.

  As an example, in FIG. 3B, the target potential VD of the output signal line 60 recognized by the selection signal supply unit 64 is higher than the target potential VD-1 of the previous period of the horizontal synchronizing signal, and the reference potential Vref3. The change in the potential of the output signal line 60 when the output voltage is higher than that is shown. As is clear from FIG. 3B, the output signal line 60 is connected to the power source during the period until the potential of the output signal line 60 reaches the reference potential Vref3. As is clear from the comparison of the slope of the change with the slope of the potential change when not provided in the potential change auxiliary circuit group 40 (the slope of the one-dot chain line shown in FIG. 3B), the output is output during the period. The potential of the signal line 60 changes at high speed.

  Further, when the potential of the output signal line 60 reaches the reference potential Vref3, the PMOS transistor 52 for detection is turned off, so that the connection between the output signal line 60 and the power source is released, and the slope of the potential change of the output signal line 60 is also increased. Although it becomes smaller as in the case where it is not provided in the potential change auxiliary circuit group 40, the output signal line 60 is changed from the potential VD-1 to the potential VD as indicated by "time reduction" in FIG. Since the total time required for the change is shortened, the operation speed of the source driver 16 can be improved. Since the detection PMOS transistor 52 is turned off when the potential of the output signal line 60 reaches the reference potential Vref3, the detection PMOS transistor 52 is useless compared to the case where the detection PMOS transistor 52 is turned on for a predetermined time. Power consumption can be suppressed.

  The selection signal supply unit 64 of the potential detection / change circuit 50 supplies the n potential detection / change circuits 50 as the reference potential Vref when determining that the change direction of the potential of the output signal line 60 is a decrease in potential. A potential that is equal to or higher than the recognized target potential and closest to the target potential is selected from the n types of potentials, and the selected potential is supplied as a reference potential Vref to the gates of the PMOS transistor 52 and the NMOS transistor 54 for detection. A selection signal for turning on the selection PMOS transistor 58 is supplied to the gate of the selection PMOS transistor 58 with respect to the potential detection / change circuit 50.

  When the selection PMOS transistor 58 to which the selection signal is supplied to the gate is turned on, the detection NMOS transistor 54 connected to the selection PMOS transistor 58 is supplied with the potential of the output signal line 60 to the gate. Since it is turned on until the reference potential Vref is reached, the output signal line 60 is grounded via the detection NMOS transistor 54 and the selection PMOS transistor 58 until the potential of the output signal line 60 reaches the reference potential Vref. Connected to the line.

  As an example, in FIG. 3C, the target potential VD of the output signal line 60 recognized by the selection signal supply unit 64 is lower than the target potential VD-1 of the previous period of the horizontal synchronizing signal, and the reference potential Vref1. The change in the potential of the output signal line 60 when the output signal line is lower than that is shown. As apparent from FIG. 3C, since the output signal line 60 is connected to the ground line during the period until the potential of the output signal line 60 reaches the reference potential Vref1, the output signal line 60 in this period is connected. As is apparent from the comparison of the slope of the potential change with the slope of the potential change when the potential change auxiliary circuit group 40 is not provided (the slope of the one-dot chain line shown in FIG. 3C), The potential of the output signal line 60 changes at high speed.

  When the potential of the output signal line 60 reaches the reference potential Vref1, the detection NMOS transistor 54 is turned off, so that the connection between the output signal line 60 and the ground line is released, and the slope of the potential change of the output signal line 60 As shown in FIG. 3C, “time reduction” is indicated, and the output signal line 60 is changed from the potential VD-1 to the potential VD. Since the total time required for the change to is shortened, the operation speed of the source driver 16 can be improved. Further, since the detection NMOS transistor 54 is turned off when the potential of the output signal line 60 reaches the reference potential Vref1, it is useless compared with the case where the detection NMOS transistor 54 is turned on for a predetermined time. Power consumption can be suppressed.

[Second Embodiment]
Next, a second embodiment of the present invention will be described. In addition, the same code | symbol is attached | subjected to the part same as 1st Embodiment, and description is abbreviate | omitted. FIG. 4 shows the potential change auxiliary circuit 42 and the switching control unit 44 of the potential change auxiliary circuit group 40 according to the second embodiment. As shown in FIG. 4, in the second embodiment, a single potential detection / change circuit 68 is provided in the potential change auxiliary circuit 42.

  In the potential detection / change circuit 68, the selection NMOS transistor 56 and the PMOS transistor 58 are omitted as compared with the potential detection / change circuit 50 described in the first embodiment, and the detection PMOS transistor 52 has a source. The power supply, the gate is connected to the potential selection circuit 70, and the detection NMOS transistor 54 has the source connected to the ground line and the gate connected to the potential selection circuit 72.

  The potential selection circuits 70 and 72 are supplied with n types of potentials (reference potentials Vref1 to Vrefn) from the reference potential supply unit 62 of the switching control unit 44, respectively. The potential selection circuits 70 and 72 include n switching elements that are turned on / off in response to a selection signal input from the selection signal supply unit 64 of the switching control unit 44, and are selected from the selection signal supply unit 64. In response to the signal, any one of n potentials supplied from the reference potential supply unit 62 is supplied as a reference potential Vref to the gate of the detection PMOS transistor 52 or the gate of the detection NMOS transistor 54. To do.

  In the second embodiment, the detection PMOS transistor 52 includes the first switching means according to the present invention (more specifically, the first switching means according to claim 6) and the PMOS according to claim 8. An example of the transistor, the NMOS transistor 54 for detection, includes the second switching means according to the present invention (more specifically, the second switching means according to claim 7) and the example of the NMOS transistor according to claim 8. The control unit 44 is an example of a control unit according to the present invention (more specifically, the control unit according to claims 6 and 7), the decoder circuit 36 is an example of the potential switching unit according to claim 1, and the amplifier circuit 48 is a claim. 11 is an example of an amplifier circuit described in FIG. The potential supplied to the gate of the detection PMOS transistor 52 is a first reference potential, more specifically, an example of “any one of n types of potentials” according to claim 6, The potential supplied to the gate of the NMOS transistor 54 is an example of a second reference potential, more specifically, “any one potential among n types of potentials” according to claim 7.

  Next, the operation of the second embodiment will be described. When the selection signal supply unit 64 of the potential detection / change circuit 50 determines that the potential change direction of the output signal line 60 is an increase in potential, the reference potential supply unit 62 supplies the potential selection circuits 70 and 72 with the potential n. A potential that is equal to or lower than the recognized target potential and closest to the target potential is selected from the types of potentials, and a selection signal for outputting the selected potential from the potential selection circuit 70 is supplied to the potential selection circuit 70. As a result, the potential selected above is supplied as the reference potential Vref to the gate of the detection PMOS transistor 52, and until the potential of the output signal line 60 reaches the reference potential Vref supplied to the gate. When the PMOS transistor 52 is turned on, the output signal line 60 is connected to the power supply via the detection PMOS transistor 52 until the potential of the output signal line 60 reaches the reference potential Vref.

  Accordingly, as in the first embodiment, the time required for the output signal line 60 to change from the potential VD-1 to the higher potential VD is shortened (see also FIG. 3B), and the operating speed of the source driver 16 is reduced. Improvement can be realized. The detection PMOS transistor 52 is turned off when the potential of the output signal line 60 reaches the reference potential Vref supplied to the gate, so that the detection PMOS transistor 52 is turned on for a predetermined time. Thus, wasteful power consumption can be suppressed.

  Further, when the selection signal supply unit 64 of the potential detection / change circuit 50 determines that the potential change direction of the output signal line 60 is a decrease in potential, the reference potential supply unit 62 supplies the potential selection circuits 70 and 72 with the potential decrease. A potential that is equal to or higher than the recognized target potential and closest to the target potential is selected from the n types of potentials, and a selection signal for outputting the selected potential from the potential selection circuit 72 is supplied to the potential selection circuit 72. As a result, the potential selected above is supplied as the reference potential Vref to the gate of the NMOS transistor 54 for detection, and until the potential of the output signal line 60 reaches the reference potential Vref supplied to the gate. When the NMOS transistor 54 is turned on, the output signal line 60 is connected to the power supply via the detection NMOS transistor 54 until the potential of the output signal line 60 reaches the reference potential Vref.

  Accordingly, as in the first embodiment, the time required for the output signal line 60 to change from the potential VD-1 to the lower potential VD is shortened (see also FIG. 3C), and the operating speed of the source driver 16 is reduced. Improvement can be realized. Since the detection NMOS transistor 54 is turned off when the potential of the output signal line 60 reaches the reference potential Vref supplied to the gate, the detection NMOS transistor 54 is turned on for a predetermined time. Thus, wasteful power consumption can be suppressed.

[Third Embodiment]
Next, a third embodiment of the present invention will be described. In addition, the same code | symbol is attached | subjected to the part same as 1st Embodiment, and description is abbreviate | omitted. FIG. 5 shows the potential change auxiliary circuit 42 and the switching control unit 44 of the potential change auxiliary circuit group 40 according to the third embodiment. As shown in FIG. 5, the potential detection / change circuit 76 according to the third embodiment is different from the potential detection / change circuit 50 described in the first embodiment in the detection PMOS transistor 52 and NMOS transistor 54. The only difference is that the back gate is connected to the output signal line 60.

  In the first embodiment, the detection PMOS transistor 52 is an example of a PMOS transistor according to claim 9, and the detection NMOS transistor 54 is an example of an NMOS transistor according to claim 9.

  When the back gate of the detection PMOS transistor 52 is connected to the ground line and the back gate of the detection NMOS transistor 54 is connected to the power source as in the potential detection / change circuit 50 described in the first embodiment, Since a potential difference occurs between the back gates of the detection PMOS transistor 52 and NMOS transistor 54 and the output signal line 60 (back bias is applied), the transistor that is turned on among the detection PMOS transistor 52 and NMOS transistor 54 outputs Off at a timing slightly earlier than the potential of the signal line 60 reaches the reference potential Vref supplied to the gate (the timing at which the difference between the potential of the output signal line 60 and the reference potential Vref is reduced to the threshold voltage Vt of the transistor) To do.

  On the other hand, when the back gates of the detection PMOS transistor 52 and the NMOS transistor 54 are connected to the output signal line 60 as in the potential detection / change circuit 76 according to the third embodiment, the detection PMOS transistor 52 Since the back bias is not applied to the NMOS transistor 54, the ON transistor of the detection PMOS transistor 52 and the NMOS transistor 54 is turned on until the potential of the output signal line 60 reaches the reference potential Vref supplied to the gate. Will turn on. As a result, the period during which the detection PMOS transistor 52 and NMOS transistor 54 are ON is lengthened, so that the time required for the output signal line 60 to change from the potential VD-1 to the potential VD is further shortened. The operation speed of 16 can be further improved.

  In the third embodiment, the configuration in which the back gates of the detection PMOS transistor 52 and the NMOS transistor 54 are connected to the output signal line 60 in the configuration described in the first embodiment has been described. The configuration is not limited, and the back gates of the detection PMOS transistor 52 and the NMOS transistor 54 may be connected to the output signal line 60 in the configuration described in the second embodiment.

  In the above description, the reference potential Vref, which is the target potential when changing the potential of the output signal line 60 by turning on the detection PMOS transistor 52 and NMOS transistor 54, is applied to the gates of the detection PMOS transistor 52 and NMOS transistor 54. Although the supply mode has been described, the present invention is not limited to this, and the gates of the detection PMOS transistor 52 and the NMOS transistor 54 have a potential higher than the reference potential by a predetermined value (for example, the threshold voltage Vt of the transistor). You may make it supply to. Also in this case, as in the case where the back gates of the detection PMOS transistor 52 and the NMOS transistor 54 are connected to the output signal line 60, the period during which the detection PMOS transistor 52 and the NMOS transistor 54 are on is made longer. be able to. In addition, the said aspect is an example of invention of Claim 10.

  Further, the potential change auxiliary circuit 42 is not limited to the configuration shown in FIGS. 2, 4, and 5; The configuration may be different. That is, for example, on the side where the output signal line 60 is connected to the power supply, as shown in FIGS. 2 and 5, a plurality of detection PMOS transistors 52 to which different potentials are supplied to the gates are provided. On the side where the output signal line 60 is connected to the ground line, as shown in FIG. 4, a single NMOS transistor 54 for detection in which the potential supplied to the gate is switched from a plurality of potentials by the potential selection circuit. Alternatively, the configuration on the side where the output signal line 60 is connected to the power supply and the configuration on the side where the output signal line 60 is connected to the ground line may be replaced with the above.

  Further, in the above description, the first switching means is constituted by the detection PMOS transistor 52 and the second switching means is constituted by the detection NMOS transistor 54. However, the present invention is limited to this. It is also possible to adopt a configuration using switching elements other than MOS transistors.

DESCRIPTION OF SYMBOLS 10 Display apparatus 12 Drive apparatus 16 Source driver 36 Decoder circuit 38 Gradation voltage generation part 42 Potential change auxiliary circuit 44 Switching control part 48 Amplifier circuit 50,68,76 Potential detection / change circuit 52 Detection PMOS transistor 54 For detection NMOS transistor 58 NMOS transistor 58 for selection PMOS transistor 60 for selection Output signal line 62 Reference potential supply unit 64 Selection signal supply unit 70, 72 Potential selection circuit

Claims (11)

Provided between a potential switching unit that switches the potential of the drive signal line to a target potential according to display data and a display device to which the potential of the drive signal line is supplied as a voltage. First switching means for connecting the drive signal line to a power source until a first reference potential higher than the potential is reached;
A second switch provided between the potential switching unit and the display device and connecting the drive signal line to a ground line until the potential of the drive signal line reaches a second reference potential lower than the potential; Switching means;
When the potential of the drive signal line is lower than the target potential, a potential that is equal to or lower than the target potential and is closest to the target potential among the n types (n ≧ 1) of predetermined potentials is set as the first reference potential. When the first switching means is operated and the potential of the drive signal line is higher than the target potential, the potential that is equal to or higher than the target potential and is closest to the target potential is selected from the n types of potentials as the second reference. Control means for actuating the second switching means as a potential;
A drive device for a display device, comprising: A plurality of the first switching means are provided, and each of the first switching means is supplied with a different potential among the n types of potentials as the first reference potential,
When the potential of the drive signal line is lower than the target potential, the control means has a potential that is equal to or lower than the target potential and closest to the target potential as the first reference potential among the plurality of first switching means. The display device driving apparatus according to claim 1, wherein the first switching means to be supplied is operated. Third switching means is provided between each of the first switching means and the power source,
The control means turns on the third switching means provided between the specific first switching means to be operated and the power source among the plurality of third switching means, thereby causing the specific first switching means to turn on. 3. A drive device for a display device according to claim 2, wherein the switching means is operated. A plurality of the second switching means are provided, and different potentials among the n kinds of potentials are supplied to the individual second switching means as the second reference potential,
When the potential of the drive signal line is higher than the target potential, the control means has a potential equal to or higher than the target potential and closest to the target potential among the plurality of second switching means as the second reference potential. 4. The display device driving device according to claim 1, wherein the second switching means to be supplied is operated. Fourth switching means is provided between each of the second switching means and the ground line,
The control means turns on the fourth switching means provided between the specific second switching means to be operated and the ground line among a plurality of the fourth switching means, and thereby the specific switching means. 5. The display device driving apparatus according to claim 4, wherein the second switching means is operated. The first switching means is selectively supplied with any one of the n kinds of potentials as the first reference potential,
When the potential of the drive signal line is lower than the target potential, the control means supplies the first switching means with a potential that is equal to or lower than the target potential and is closest to the target potential among the n types of potentials. 6. The method according to claim 1, wherein the first switching means is operated by supplying a reference potential that is equal to or lower than the target potential and that is closest to the target potential as the first reference potential. A drive device for a display device according to claim 1. The second switching means is selectively supplied with any one of the n kinds of potentials as the second reference potential,
When the potential of the drive signal line is higher than the target potential, the control means supplies the second switching means with a potential that is equal to or higher than the target potential and is closest to the target potential among the n types of potentials. 6. The method according to claim 1, wherein the second switching means is operated by supplying a potential that is equal to or higher than the target potential and closest to the target potential as the second reference potential. A drive device for a display device according to claim 1. The first switching means includes a PMOS transistor having a back gate connected to the ground line,
The display device driving device according to claim 1, wherein the second switching unit includes an NMOS transistor having a back gate connected to the power source. The first switching means includes a PMOS transistor having a back gate connected to the drive signal line,
8. The display device driving device according to claim 1, wherein the second switching unit includes an NMOS transistor having a back gate connected to the driving signal line. A potential higher than the first reference potential by a predetermined value is supplied to the gate of the PMOS transistor of the first switching means,
10. The display device driving device according to claim 8, wherein a potential higher than the second reference potential by a predetermined value is supplied to a gate of the NMOS transistor of the second switching means. An amplifying circuit provided between the potential switching unit and the display device;
The said 1st switching means and the said 2nd switching means connect the site | part between the said electric potential switch part and the said amplifier circuit among the said drive signal lines to the said power supply or the said ground line. The drive device for a display device according to any one of 10.

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