JPH11136130A - Decoder, digital/analog conversion circuit using the same and driving circuit for matrix type liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a decoder constituted by a simple layout with a minimum number of input wirings, a digital/analog conversion circuit using it and a driving circuit of a matrix type liquid crystal display device composed by constituting a horizontal driving circuit by using a digital/analog conversion circuit further. SOLUTION: In a 3-bit decoder, three pieces of MOS transistors Qn11, Qp11 and Qn12 ON/OFF operated corresponding to the logic of the respective bits of inut data X0, X1 and X2 are connected in series between a negative power supply Vss and na output node N11 through a MOS transistor Qn for obstructing a through current in a reset period, while a MOS transistor Qp12 for resetting the potential of the output node N11 to the power supply voltage of a positive power supply Vdd is provided and the logical stage of the output node N11 is latched in a latch circuit 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoder, a digital-to-analog conversion circuit using the same, and a drive circuit for a matrix type liquid crystal display device using the digital-to-analog conversion circuit to form a horizontal drive circuit.

[0002]

2. Description of the Related Art A decoder is generally configured as shown in FIG. FIG. 7 shows a 3-bit decoder as an example. Then, as shown in the logic table of FIG. 8, one of the 8 (= 2 ³ ) outputs Y0 to Y7 is designated based on the 3-bit input data X0 to X2.

Usually, when a decoder is constructed, as shown in FIG. 7, inverters 101 to 103 are provided for 3-bit input data X0 to X2, respectively, and each bit is input as two data of opposite logic. There is a need to. Therefore, in the case of a 3-bit decoder,
The input data to the decoder is 3 bits × 2. That is, the 3-bit decoder is controlled by 6 inputs.

In order to specify one of the eight outputs Y0 to Y7, a static circuit 8 is usually used.
NAND circuits (or AND circuits) 111 to 118
Is used. FIG. 9 illustrates an example of a configuration of a three-input NAND circuit. In the figure, three P-channel MOS transistors Qp101 to Qp103 are connected in parallel, and each gate electrode is connected to three input terminals 101 to 103, respectively. P channel MOS transistor Qp1
Source electrodes 01 to Qp103 which are commonly connected are connected to a positive power supply Vdd.

[0005] P-channel MOS transistor Qp101
Np MOS transistors Qn101 to Qn103 are connected in series between the commonly connected drain electrodes Qp103 to Qp103 and the negative power supply Vss, and each gate electrode is connected to three input terminals 101 to 103, respectively. Have been. Then, P-channel MOS transistor Qp1
The commonly connected drain electrodes 01 to Qp103 are connected to the output terminal 104.

[0006]

As described above, a conventional general decoder requires twice as many input wires as the number of input data bits, and is constructed using the above-described NAND circuit. Since the number of transistors required is twice as large as the number of bits of input data, the area occupied by these transistors increases, and the number of transistors increases as the number of bits of input data increases.

The decoder having the above-described configuration is used, for example, in a digital input matrix type liquid crystal display device to constitute a digital-to-analog conversion circuit in a horizontal drive circuit. However, considering a liquid crystal display device in which a driving system including the horizontal driving circuit is formed on the same substrate as a liquid crystal panel, configuring a digital-to-analog conversion circuit using the decoder having the above configuration requires a narrower pixel pitch. At present, it becomes difficult on the layout.

FIG. 10 shows an example of the configuration of a conventional digital-to-analog conversion circuit using the decoder having the above configuration. In the figure, the same parts as those in FIG. 7 are denoted by the same reference numerals, and the description thereof will not be repeated.

In FIG. 10, a reference voltage 1 for eight gradations is used.
The analog switches 131 to 138 are connected between each of the voltage lines 121 to 128 for giving the signal voltages .about.8 and one signal line 129 in a liquid crystal panel (not shown). In the liquid crystal panel, one column of pixels is connected to one signal line 129. Each of the analog switches 131 to 138 is configured by a C-MOS transistor,
ON / OFF control is performed by the outputs of the ND circuits 111 to 118 and the outputs of the inverters 141 to 148 for inverting the polarities of these outputs, that is, two decode outputs having opposite polarities.

A unit unit in the conventional digital-to-analog conversion circuit having the above configuration, for example, a NAND circuit 111,
FIG. 11 shows a specific circuit configuration of the inverter 141 and the analog switch 131. In the figure, since the circuit configuration of the NAND circuit 111 is the same as the circuit configuration shown in FIG. 9, the same parts are denoted by the same reference numerals, and the description thereof will not be repeated.

In FIG. 11, an inverter 141 is connected in series between a positive power supply Vdd and a negative power supply Vss, and has P-channel MOS transistors Qp111 and N having respective gate electrodes commonly connected to an output terminal of a NAND circuit 111.
CM composed of channel MOS transistor Qn111
It is composed of an OS inverter. The analog switch 131 is, as described above, a C-MO having a P-channel MOS transistor Qp121 and an N-channel MOS transistor Qn121 connected in parallel with each other.
It is composed of S transistors.

As described above, in a digital input matrix type liquid crystal display device, when a digital-analog conversion circuit is configured using a decoder including a NAND circuit,
For example, in the case of 3 bits, the input wiring is 6 times which is twice the number of bits.
This is necessary, and since reference voltages 1 to 8 for eight gradations are required, eight unit units corresponding to the reference voltages are required. FIG. 11 shows the configuration of a unit unit.
As is clear from FIG. 6, six NAND circuits, two inverters, and two C-MOS analog switches are used.
Therefore, a total of ten transistors are required.

In the case of 4 bits, 16 gradations are required, so that eight input wirings and 16 unit units are required. Eight NAND circuits and two inverters are required to constitute a unit unit. As a C-MOS analog switch, a total of 12 transistors are required. As described above, as the number of bits of input data increases, the number of input wirings and the number of transistors constituting a unit increase, and the area occupied by the transistors increases. On the same substrate as the liquid crystal panel.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and has as its object to provide a decoder which requires a minimum number of input wirings and can be configured with a simple layout and a digital / analog using the same. Conversion circuit,
Another object of the present invention is to provide a driving circuit for a matrix type liquid crystal display device in which a horizontal driving circuit is formed by using the digital-analog conversion circuit.

[0015]

A decoder according to the present invention is connected in series between a first power supply and an output node, and operates in accordance with the logic of each bit of input data of n bits (n is an integer of 2 or more). N switch means for performing on / off operation, latch means for latching a logic state of an output node,
A reset means connected between the output node and the second power supply and resetting the potential of the output node to the power supply voltage of the second power supply is provided.

In the decoder having the above configuration, first, the reset means resets the potential of the output node to the power supply voltage of the second power supply. Thus, the output node potential is refreshed. Thereafter, when data of a predetermined logic is input to each bit, the corresponding n switch means are turned on (conducting). Then, a short circuit occurs between the output node and the first power supply, and the potential of the output node becomes the power supply voltage of the first power supply. Then, the potential state (logic) of the output node is latched by the latch means.

By using this decoder as a unit unit and connecting 2 ⁿ unit units in parallel, a multi-bit decoder that selects one of 2 ⁿ outputs based on n-bit input data is constructed. Is done. Also, by using this multi-bit decoder, a digital-to-analog conversion circuit that selects one reference voltage corresponding to the input data from among the reference voltages having 2 ⁿ gray scales and outputs it as an analog signal is configured. Further, this digital-to-analog conversion circuit is used in a drive system of a matrix type liquid crystal display device.
It is used as a digital-to-analog conversion circuit in a horizontal drive circuit that receives digital signals.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a circuit diagram showing one embodiment of the present invention. In the present embodiment,
As an example, when applied to a 3-bit decoder, the input data X
The case where each logic of 0 to X2 is (101) is taken as an example.

In FIG. 1, 3-bit input data X
As three switch means corresponding to 0, X1, X2,
N channel MOS transistor Qn11, P channel M
An OS transistor Qp11 and an N-channel MOS transistor Qn12 are sequentially connected in series. These MOS transistors Qn11, Qp11, Q
The data lines 11, 12, 13 are connected to each gate electrode of n12.
, Three-bit input data X0, X1, and X2 are provided.

The source electrode of N-channel MOS transistor Qn11 is connected to negative power supply Vss, which is a first power supply, and the source electrode of N-channel MOS transistor Qn12 is connected to output node N11 via N-channel MOS transistor Qn13. I have. A P-channel MOS transistor Qp12 is connected as a reset means between the output node N11 and the positive power supply Vdd as the second power supply. P channel MOS transistor Qp1
2 and a reset pulse re via a reset line 14 to each gate electrode of the N-channel MOS transistor Qn13.
set is applied at an appropriate timing.

P channel MOS transistor Qp12
Is a low-level reset pulse re applied to its gate electrode.
When set is applied, the output node N11 is turned on (conducted) and resets the potential of the output node N11 to the power supply voltage Vdd. On the other hand, N channel MOS transistor Qn13 and N channel MOS transistor Qn11 and P channel MOS transistor Qp1 during the reset period by P channel MOS transistor Qp12.
It functions to block a through current flowing through 1 and N channel MOS transistor Qn12.

The output node N11 is further connected to a latch circuit 15 for latching the logic state of the node N11. The latch circuit 15 includes two C-MOS inverters 16 and 17 connected in parallel with opposite polarities. The C-MOS inverter 16 includes a P-channel MOS transistor Qp21 and an N-channel transistor Mp21 connected in series between a positive power supply Vdd and a negative power supply Vss.
OS transistor Qn21,
The gate electrodes of the OS transistors Qp21 and Qn21 are commonly connected to an output node N11.

Similarly, the C-MOS inverter 17 also includes a P-channel MOS transistor Qp22 and an N-channel MOS transistor Qp22 connected in series between a positive power supply Vdd and a negative power supply Vss.
S transistor Qn22.
The gate electrodes of the S transistors Qp22 and Qn22 are C
Output terminals of the MOS inverter 16 (Qp21, Qn21
, The drain common connection point, and the drain common connection point is connected to the input terminal (Qp2
1 and Qn21).

Next, the circuit operation of the above configuration will be described with reference to FIG.
This will be described with reference to the timing chart of FIG.

First, 3-bit input data X0, X1,
When each logic of X2 is, for example, in the state of (100), this decoder is in the non-selected state because it corresponds to (101). In a reset period A in which the reset pulse reset is at a low level, the output node N11
(Output voltage out) is reset (refreshed) to Vdd. Then, the input data X0, X1, X2
Is in the state of (101), the N-channel MO
S transistor Qn11, P channel MOS transistor Qp11 and N channel MOS transistor Qn1
2 are all turned on.

In reset period A, N-channel MOS transistor Qn11, P-channel MOS transistor Qp11 and N-channel MOS transistor Qp11
Even if all of n12 are turned on, N channel M
Since the low-level reset pulse reset is applied to the gate electrode of the OS transistor Qn13 and is in the off state, the positive power supply Vdd and the negative power supply Vss are short-circuited, and the N-channel MOS transistor Qn11, the P-channel MOS transistor Qp11 and N channel M
No through current flows through the OS transistor Qn12.

When the reset period A elapses, the low-level reset pulse reset disappears, and the P-channel MOS transistor Qp12 is turned off, while the N-channel MOS transistor Qn13 is turned on. Therefore, N channel MOS transistor Q
Since n11, P-channel MOS transistor Qp11 and N-channel MOS transistor Qn12 are all in the ON state, the potential of output node N11 transitions from Vdd (logic 1) to Vss (logic 0), and this decoder is in the selected state. . The logic state of the output node N11 is latched by the latch circuit 15 during a period B until the next reset period A.

As described above, in the decoder according to the present embodiment, the transistors Qn11, Qp11, Qn12 and the output node N1 corresponding to the number of bits of the input data are provided.
Transistor Qp1 that resets (refreshes) 1
2 and a latch circuit 15 for latching the logic state of the output node N11. Therefore, the number of input lines may be the number of data lines 11 to 13 corresponding to the number of bits, and one reset line 14. Even if the number of bits increases, only the number of transistors increases by the number of bits, so that a simple layout can be realized and a high yield can be achieved. Moreover, it is possible to suppress power consumption to a low level even though it is a dynamic circuit.

In the above-described embodiment, an N-channel MOS transistor Qn13 for preventing a through current in the reset period A is provided between the three transistors Qn11, Qp11, Qn12 and the output node N11. If the through current can be ignored, FIG.
As shown in FIG.
The OS transistor Qn13 becomes unnecessary. As a result, one transistor can be reduced.

In the above embodiment, the output node N1
As means for latching the logical state of one, two C-MOS inverters 16 and 17 connected in parallel with opposite polarities are used.
Although the latch circuit 15 is used, the present invention is not limited to this. For example, as shown in FIG.
The capacitor 18 may be connected between the output node N11 and the negative power supply Vss. In short, the capacitor 18 may have any configuration that can latch the logic state of the output node N11.

At this time, the two-stage cascade-connected C-MOS inverters 16 and 17 used as the latch circuit 15 by connecting the input terminal and the output terminal in common so that the input terminal and the output terminal are not connected. The waveform shaping circuit 1
It will function as 5 '. Note that the output node 11
Is stable and the waveform shaping is not required, the C-MOS inverters 16 and 17 become unnecessary, and the number of transistors can be further reduced.
However, when it is necessary to derive an output having a polarity opposite to the logic of the output node N11, it is necessary to leave the first-stage C-MOS inverter 16 as it is.

Further, the decoder according to the above-described embodiment or its modification is used as a unit unit, and eight unit units are connected in parallel, and the conductivity type (P-channel / N-channel) of three MOS transistors as switching elements is used. Is appropriately selected for each unit, as shown in the logic table of FIG. 8, a 3-bit 3-bit designating one of eight outputs Y0-Y7 based on 3-bit input data X0-X2. A decoder can be configured. When a 4-bit decoder is configured, for example, four switch elements may be provided, and 16 (= 2 ⁴ ) unit units may be connected in parallel.

As described above, a multi-bit decoder in which unit units are connected in parallel by the number corresponding to the number of bits of the input data is used, and a reference voltage having a gradation corresponding to the number of bits is used. 1 corresponding to the input data from
A digital-to-analog conversion circuit that selects one reference voltage and outputs it as an analog signal can be configured. FIG.
FIG. 1 shows an example of a circuit configuration of a digital-to-analog conversion circuit using, for example, the 3-bit decoder shown in FIG.

In FIG. 5, reference voltages 1 to 8 for eight gradations are set.
8 and one signal line 29
Between them, analog switches 31 to 38 are connected. Each of the analog switches 31 to 38 is a C-MOS
Each unit unit output is a potential of the output nodes N11-1 to N11-8 of each unit unit and its inverted output, that is, two of opposite polarities.
On / off control is performed by two decode outputs.

In the present embodiment, as an inverter for obtaining the inverted output, the first-stage C-MOS inverter 16 (see FIG. 1) of each of the latch circuits 15-1 to 15-8 provided for each unit unit. I also use it. That is, the input and output of the first-stage C-MOS inverter 16 of each of the latch circuits 15-1 to 15-8 are supplied to the analog switches 31 to 38 as two decoded outputs having opposite polarities.

Also, three MOs in each unit unit
As the conductivity type of the S transistor, input data X0 to X2
Corresponding to the eight combinations of logic of each bit of
In the order of bits 0, X1, and X2, P
Channel, N channel, P channel, P
P channel, N channel, P
Channel, N channel at reference voltage 4, N channel, P
Channel, P channel at reference voltage 5, P channel, N
N channel, P channel, N
Channel, P channel at reference voltage 7, N channel, N
N channels are set for all the channels and the reference voltage 8.

As described above, the decoder according to the present invention is used as a unit unit, and this unit unit is connected in parallel by the number corresponding to the number of bits of the input data to constitute a digital-analog conversion circuit. A number corresponding to the number, for example, three data lines 1 for 3 bits
Since a multi-bit decoder can be constituted by 1 to 13 and one reset line 14, a simple layout can be realized.

As for the number of transistors, when a 3-bit decoder is compared, in the unit unit according to the conventional example shown in FIG. 11, six NAND circuits, two inverters, and C-MOS analog switches are used. While a total of ten transistors are required, the unit unit according to this embodiment has three switches, one reset means, one through current blocking means, and one latch circuit 15 in the unit unit according to the present embodiment. 4 pieces, C-MO
A total of 11 transistors are required as S analog switches, and the conventional example is one less.

However, when the number of bits of the input data increases, the unit unit according to the conventional example using the NAND circuit increases the number of transistors of the NAND circuit by twice the number of bits. In the unit unit according to the embodiment, since the number of transistors of the switch means only increases by the number of bits, the effect of reducing the number of transistors increases as the number of bits of input data increases. In that case, the effect is extremely large.

The digital-to-analog conversion circuit according to the present embodiment described above is used, for example, as a digital-to-analog conversion circuit in a horizontal drive circuit in an active matrix type liquid crystal display device. FIG. 6 illustrates an example of a configuration of an active matrix liquid crystal display device.

In FIG. 6, a plurality of pixels 43 are two-dimensionally arranged at intersections of each of a plurality of rows of scanning lines (scanning electrodes) 41 and a plurality of columns of signal lines (signal electrodes) 42. Each of the pixels 43 is a switching element in which a gate electrode is connected to the scanning line 41 and a source electrode is connected to the signal line 42, for example, a thin film transistor (TFT).
A thin film transistor 44 and a liquid crystal cell 45 in which a pixel electrode is connected to a drain electrode of the TFT 44.

In each of the pixels 43, the liquid crystal cell 45 is provided with a counter electrode facing the pixel electrode. Although the counter electrode is schematically shown in FIG. 6, there is usually one dielectric layer provided commonly to all the pixel electrodes, and a constant voltage is applied to the counter electrode as a common voltage. .
Although not shown, an auxiliary capacitance is usually provided to increase the tolerance of the TFT 44 for leakage.

A horizontal drive circuit 46 for selecting and driving a plurality of pixels 43 in units of columns includes a horizontal shift register circuit 47 for sequentially outputting horizontal scanning pulses, a wiring section 48 for taking in digital image data, and a A digital data memory circuit 49 for sequentially storing the fetched digital image data, and a level conversion circuit 50 for performing level conversion of the data
And a digital-to-analog conversion circuit 51 for converting digital data to analog data.

On the other hand, a vertical drive circuit 52 for selecting and driving a plurality of pixels 43 on a row-by-row basis includes a vertical shift register circuit 53 for sequentially outputting vertical scanning pulses by performing vertical scanning; The scanning line 41 responds to the vertical scanning pulse sequentially output from the circuit 53.
And an output buffer circuit 54 for directly driving the output buffer circuit.

In the active matrix type liquid crystal display device having the above configuration, the horizontal shift register circuit 47 sequentially transfers the start signal supplied from the timing generation circuit 55, and outputs a horizontal scanning pulse sequentially from each register stage. Then, in response to the horizontal scanning pulse, data is taken in via the data wiring section 48 and stored in the digital data memory circuit 49. The data stored in the digital data memory circuit 49 is output collectively in response to the output enable signal, and is supplied to the digital / analog conversion circuit 51 via the level conversion circuit 50.

The digital-to-analog conversion circuit 51 provides, for each column, for example, 3-bit input data X0 to X2,
The input data X0 is selected from among the reference voltages 1 to 8 having eight gradations.
One reference voltage (analog voltage) corresponding to .about.X2 is selected and output. As the digital-to-analog conversion circuit 51, a digital-to-analog conversion circuit (see FIG. 5) configured using the above-described decoder according to the present invention is used.

Here, as the digital / analog conversion circuit 51 in the horizontal drive circuit 46 in the active matrix type liquid crystal display device, a digital / analog conversion circuit according to the present invention shown in FIG. The circuit operation in this case will be described again with reference to the timing chart of FIG.

First, the reset pulse reset is generated once in one horizontal period. As a result, the decoder including the analog switches 31 to 38 for selecting the reference voltages of all the signals is in a non-selected state, and each pixel 43 has a TFT 44
The signal line 42 (the signal line 29 in FIG. 5)
) To high impedance. The input data X0 to X2 are line-sequential pulses that are simultaneously sampled during the horizontal period. The timing at which the input data X0 to X2 is re-sampled is adjusted so as to be within the reset period A. Therefore, the data rewritten during the reset period A is input to all the decoders at the moment when the reset period A ends, and one of the decoders to be selected is selected.
One is selected.

As described above, the drive system of an active matrix type liquid crystal display device can be implemented by using a digital-to-analog conversion circuit having a feature that a simple layout can be realized because the number of transistors can be reduced and the number of input wires is small. With this configuration, when the driving system is formed on the same substrate as the liquid crystal panel, there is no problem in layout even if the pitch of pixels is reduced. In other words, it is possible to contribute to narrowing the pitch of the pixels, which is advantageous for increasing the definition of the pixels.

[0050]

As described above, according to the present invention,
n switch means for performing on / off operation according to the logic of each bit of the input data of n bits (n is an integer of 2 or more) are connected in series between the first power supply and the output node, and By providing reset means for resetting the potential to the power supply voltage of the second power supply and providing latch means for latching the logic state of the output node, the number of data lines corresponding to the number of bits is increased for the input wiring, Only one reset line is required. Even if the number of bits of input data increases, only the number of transistors increases by the number of bits.
A simple layout can be realized, a high yield can be achieved, and low power consumption can be suppressed even with a dynamic circuit.

Also, when the decoder according to the present invention is used as a unit unit, and the unit units are connected in parallel by the number corresponding to the number of bits of the input data to constitute a digital-to-analog conversion circuit, the input wiring has the number of bits. Only a corresponding number of data lines and one reset line are required, and even if the number of bits of input data increases, only the number of transistors increases by the number of bits. Thus, the power consumption can be reduced, and the power consumption can be reduced even though the circuit is a dynamic circuit.

Further, in the driving circuit of the matrix type liquid crystal display device, by configuring the digital / analog circuit in the horizontal driving circuit by using the digital / analog circuit according to the present invention, it can be configured with a small number of transistors.
Since the number of input wires is small, the digital-to-analog conversion circuit has the advantage of realizing a simple layout.Therefore, when the drive circuit is created on the same substrate as the liquid crystal panel, the pixel pitch has been reduced. Even if it is used, there is no problem in layout, and therefore, it can contribute to narrowing the pitch of pixels, which is advantageous for higher definition of pixels.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the circuit of FIG. 1;

FIG. 3 is a circuit diagram showing a modification of the embodiment.

FIG. 4 is a circuit diagram showing another modification of the present embodiment.

FIG. 5 is a circuit diagram illustrating an example of a configuration of a digital-to-analog conversion circuit according to the present invention.

FIG. 6 is a schematic configuration diagram showing one example of an active matrix type liquid crystal display device according to the present invention.

FIG. 7 is a block diagram showing a conventional example of a 3-bit decoder.

FIG. 8 is a diagram illustrating a logic table of a 3-bit decoder.

FIG. 9 is a circuit diagram illustrating an example of a configuration of a three-input NAND circuit.

FIG. 10 is a block diagram showing a conventional example of a digital-to-analog conversion circuit.

FIG. 11 is a circuit diagram illustrating an example of a configuration of a unit unit in a conventional digital-to-analog conversion circuit.

[Explanation of symbols]

11, 12, 13 ... data line, 14 ... reset line, 1
5, 15-1 to 15-8: latch circuit, 16, 17: CM
OS inverter, 18 capacitors, 21 to 28 voltage lines, 29, 42 signal lines, 31 to 38 C-MOS analog switches, 41 scanning lines, 43 pixels, 44 T
FT (thin film transistor), 45: liquid crystal cell, 46: horizontal drive circuit, 51: digital / analog conversion circuit, 52:
Vertical drive circuit, N11, N11-1 to N11-8 ... output node

 ──────────────────────────────────────────────────の Continuation of the front page (72) Inventor Masumitsu Ino 6-35 Kita Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation

Claims (11)

[Claims] An n number of switches connected in series between a first power supply and an output node and performing on / off operation according to the logic of each bit of n-bit (n is an integer of 2 or more) input data Means, latch means for latching a logic state of the output node, and reset means connected between the output node and a second power supply, for resetting the potential of the output node to the power supply voltage of the second power supply. A decoder characterized by the above-mentioned. 2. An apparatus according to claim 1, further comprising a blocking means connected between said n switching means and said output node for blocking a through current flowing through said n switching means during a reset period by said resetting means. The decoder according to claim 1, wherein: 3. The latch means includes a first inverter having an input terminal connected to the output node, an input terminal connected to an output terminal of the first inverter, and an output terminal connected to the output node. 2. The decoder according to claim 1, further comprising a second inverter. 4. The decoder according to claim 3, wherein two outputs of mutually opposite logic are derived from the output node and the output terminal of the second inverter. 5. The decoder according to claim 1, wherein said latch means comprises a capacitor connected between said output node and said first power supply. 6. The circuit according to claim 1, wherein a circuit having said n switch means, said latch means and said reset means is a unit unit, and 2 ⁿ unit units are connected in parallel. decoder. 7. The unit unit is connected between the n switch means and the output node, and has a blocking means for blocking a through current flowing through the n switch means during a reset period by the reset means. 7. The decoder according to claim 6, wherein: 8. A decoder for obtaining 2 ⁿ outputs based on n-bit (n is an integer of 2 or more) input data, and one of reference voltages having 2 ⁿ gradations based on the output of the decoder. A digital-to-analog conversion circuit comprising a selection circuit for selecting and outputting one of the two signals, wherein the decoder is connected in series between a first power supply and an output node, and is turned on / off according to the logic of each bit of input data. N switch means for performing an OFF operation; latch means for latching a logic state of the output node; connected between the output node and a second power supply; and a potential of the output node for a power supply voltage of the second power supply 2. A digital-to-analog conversion circuit comprising 2 ⁿ unit units having reset means for resetting the number of units. 9. A device, comprising: a blocking means connected between the n switching means and the output node, for blocking a through current flowing through the n switching means during a reset period by the resetting means. A digital-to-analog conversion circuit according to claim 8. 10. A horizontal drive circuit for selecting a plurality of pixels arranged two-dimensionally in a matrix on a column-by-column basis, based on n-bit (n is an integer of 2 or more) input data, outputs 2 ⁿ different outputs. And based on the output of this decoder, 2 ⁿ
In a matrix type liquid crystal display device configured using a digital-to-analog conversion circuit including a selection circuit for selecting and outputting one of gradation reference voltages, the decoder includes a first power supply and an output node. N switch means connected in series between them to perform on / off operation in accordance with the logic of each bit of input data, latch means for latching a logic state of the output node, the output node and a second power supply And 2 ⁿ unit units having reset means for resetting the potential of the output node to the power supply voltage of the second power supply are connected in parallel with each other. Drive circuit. 11. A device connected between the n switch means and the output node, and comprising a blocking means for blocking a through current flowing through the n switch means during a reset period by the reset means. A driving circuit for a matrix type liquid crystal display device according to claim 10.