KR100479455B1 - The layout of a decoder and the method thereof - Google Patents

Abstract

An arrangement and method of a decoder with m x n nodes is provided. The node includes a plurality of transistor nodes and a plurality of channel nodes. The method of manufacturing a transistor node includes forming a gate, a first source / drain region, and a second source / drain region. Channel nodes are manufactured by forming channels. The channel, the first source / drain region and the second source / drain region are simultaneously formed of the same material. In the present invention a smaller width decoder circuit is achieved without additional masks.

Description

LAYOUT OF A DECODER AND THE METHOD THEREOF

The present invention relates to the arrangement and method of the decoder, and more particularly to the arrangement and method of the decoder having a smaller number of masks and a smaller circuit width.

This application forms a part of this specification by citing here Taiwan Application No. 90101196, filed January 18, 2001.

LCD (Liquid Crystal Display) has a data driver and a scan driver. The color or image on the display device is converted by the following mechanism. First, one of the scan lines that needs to be scanned is determined by the scan driver. Next, all the pixels in one scan line are updated by inputting data signals from the data driver. Taking a color TFT LCD (thin film transistor LCD) as an example, each pixel includes three sub-pixels, and the gray scale of each sub pixel is a TFT (thin film transistor). Controlled by The three subpixels represent three colors of red, green, and blue, respectively. Thus, the color of each pixel is controlled by three TFTs.

1 shows the structure of a drive circuit for the color TFT LCD 100. When the resolution of the color LCD is achieved by 1280 pixels by 1024 lines, 3840 (1280x3) subpixels and TFTs are required for each scan line. First, the data driver 106 receives the digital image data D and converts the digital image data D into analog image data by the DAC 108 (Digital Analog Converter, D / A). Next, the scan driver 104 selects the scan line 114 (m), and the data of the subpixels on the scan line m is updated from the data driver 106 via the data line 112.

In the LCD, each sub pixel includes a liquid crystal which determines the transmittance of the sub pixel, and the transmittance is controlled by the voltage applied to the liquid crystal. If a voltage having the same polarity is continuously applied to the subpixel, the liquid crystal will be easily damaged. The transmittance of each subpixel is related to the value of the applied voltage, not to the polarity of the applied voltage. Thus, the problem of damage can be solved by polarity reversal.

FIG. 2 shows a circuit block diagram in accordance with the DAC 108 of FIG. 1. The DAC 108 includes a plurality of P-type DAC devices 202, a plurality of N-type DAC devices 204, a plurality of buffers 206, and switching elements 210, 212. The P-type DAC device 202 includes a plurality of PMOSs (P-type metal-oxide semiconductors), and the N-type DAC device 204 includes a plurality of NMOSs (N-type metal-oxide semiconductors). These P-type and N-type DAC devices are arranged alternately, and they are used to output different voltage levels. When the digital image data D of the scanning line is input to the DAC device 108, it is selected by the switching element 210 according to the digital data [D (n)] dot inversion method or column inversion method for each sub-pixel and is P. Input to the -type DAC device 202 or the N-type DAC device 204. When digital data D (n) is input to the P-type DAC device 202, the digital data D (n) will be converted into an analog signal Vp. When digital data D (n) is input to the N-type DAC device 204, the digital data D (n) will be converted into an analog signal Vn. Thereafter, the analog signals Vp and Vn are input to the buffer 206, and output signals Vp 'and Vn' are generated, respectively. Next, the switching element 212 outputs the output signals Vp 'and Vn' to one of the data lines according to the method used by the switching element 210. It is well known to those skilled in the art that analog signals Vp ', Vn' are voltages with different polarities.

FIG. 3 shows a circuit diagram of the N-type DAC device 204 of FIG. 2. Here, a three-bit input is shown, and three bits of digital data D (n) are provided. The N-type DAC device 204 includes a resistor row Rs, an output line OUT, and a decoder 302. The two ends of the resistor row Rs are connected to voltages Vc and Vd, respectively. The resistor row Rs consists of series connected R0 to R6. Thus, eight different voltages from V (0) to V (7) are provided.

The decoder 302 is composed of a plurality of transistor nodes 310 and a plurality of channel nodes 320 in an array arrangement. The gates of the transistors in each column of transistor node 310 are connected to each other to generate decoder inputs B (0) to B (5). Source / drain of the transistor Q in each row of the transistor node 310 and the channel node 302 are connected in series to form signal lines L (0) to L (7).

Reference is made simultaneously to FIGS. 4A and 4B. The figures show a circuit diagram of a transistor node 310 including a transistor Q and a circuit diagram of a channel node 320 including a connection line K, respectively. Decoder inputs B (0) to B (5) are used to receive digital data D (n). Digital data [D (n)] (b0 ', b0, b1', b1, b2 ', b2) are input to decoder inputs B (0) to B (5), respectively, where b0, b1 and b2 are b0. It is the inverted value of ', b1', b2 '. The input ends of the signal lines L (0) to L (7) are coupled with the output ends of the resistor rows Rs. All output terminals of the signal lines L (0) to L (7) are commonly connected to the output line OUT. The output line OUT is used to output an analog signal while digital data is processed by digital-to-analog conversion. The voltages V (0) to V (7) output from the resistor row Rs are input to the signal lines L (0) to L (7). The gate of the transistor on the signal line L (i) is controlled by the decoder input B. When the transistor on the signal line L (i) is turned on, the output line OUT outputs the voltage V (i). In the meantime, only the transistor on the output line OUT is conducted, and only the input terminal and the output terminal on the signal line L (i) are conducted, where 0 ≦ i ≦ 7. For example, when the digital data D (n) is 000, b0 ', b1' and b2 'are all 1, and only the transistor on the signal line L (0) is turned on. Therefore, the output line OUT outputs the analog signal Vn of the voltage V (0).

5 illustrates the layout of the decoder 302 of FIG. 3 according to a conventional method. The arrangement of each transistor node 310 for the decoder 302 includes a gate 530, a source region 532, and a drain region 534 corresponding to the transistor region. In addition to the gate 530, source region 532, and drain region 534, the placement of the channel node 320 further includes a doped region 526, where the doped region 526 is a channel node 320. A short circuit is formed between the source region 532 and the drain region 534 of the transistor so that the transistor is always conductive. The channel node 320 corresponds to the channel region. 6A to 6E show a method of manufacturing the signal line L (0) of FIG. The manufacturing process of the decoder 302 is as follows. As shown in Fig. 6A, a substrate is provided. Next, a doped layer 526 is formed in the channel region. Next, transistors are formed at all transistor nodes 310 and all channel nodes 320 of decoder 302, which correspond to FIGS. 6C-6E. In FIG. 6C, an oxide layer 628 is formed on the substrate. As shown in FIG. 6D, a plurality of gates 530 are formed on the oxide layer 638, and a source region 532 and a drain region 534 are formed in the substrate in FIG. 6E. These gates 530 are connected to the decoder input B and the transistors at the channel node 320 are shorted because there is a doping layer 526. In this way, the transistors are turned on and are not controlled by the decoder input B. Since the DAC 108 (n) includes a P-type DAC device 202 and an N-type DAC device 204, two additional masks are used for the P-type doped layer and the N-type doped layer. It is necessary to form independently.

7 illustrates the placement of the decoder 302 of FIG. 3 according to another conventional method. The decoder 302 is composed of a plurality of transistor nodes 310 and a plurality of channel nodes 320 in an array arrangement. The arrangement of each transistor node 310 for the decoder 302 includes a gate 730, a source region 732, and a drain region 734 corresponding to the transistor region. In addition to the gate 730, source region 732, and drain region 734, the placement of the channel node 320 further includes a short circuit device 736, the short circuit device 736 for the channel node 320. A short circuit is formed between the source region 732 and the drain region 734. The channel node 320 corresponds to the channel region. 8A to 8E show a method of manufacturing the signal line L (0) of FIG. The process of forming transistors in all transistor nodes and channel nodes of the decoder 302 is as follows. As shown in FIG. 8A, a substrate 824 is provided. An oxide layer 828 is then formed on the substrate 824 as shown in FIG. 8BB. Next, a plurality of gates 730 are formed on the oxide layer 828 as shown in FIG. 8C. In FIG. 8D, a source region 732 and a drain region 734 are formed in the substrate 824, and the arrangement of the transistors is completed. Referring to FIG. 8E, an insulating layer 838 is formed on the substrate 824, and a short circuit device 736 is formed in the channel region by forming a metal layer on the insulating layer 838. The first contact 740 and the second contact 742 of the short circuit device 736 pass through the insulating layer 838 and are connected to the source region 732 and the drain region 734, respectively. Thus, a short circuit is formed between the source 732 and the drain 734. Moreover, the gate 730 is connected to the decoder input B and the transistor is always conductive. Since the short circuit device 736 is connected to the source 732 and the drain 734 of the transistor in the channel region, the transistor is not controlled by any of the decoder inputs B.

Such a conventional method does not have the step of forming a doped layer using additional masks, namely P-type and N-type, but the circuit width of the DAC device is short circuit device 736 and source 732 and drain ( 734 is increased because the connection between them is completed by the contacts. In addition, if 10 data drivers are used in the panel, there are 384 DAC devices in the data driver, which makes the overall circuit width of the DAC device large. For DAC devices with 6 bits, the latter conventional method is difficult but can be implemented. The data driver will also be too long to use if the DAC device is 8 bits.

It is an object of the present invention to provide an arrangement and method of the decoder in which the decoder has a small circuit width and is manufactured using a small mask.

According to the object of the present invention, a decoder structure having m x n nodes is provided, the node comprising a plurality of transistor nodes and a plurality of channel nodes. The transistor node N (i1, j1) corresponds to the transistor region A (i1, j1), the channel node N (i2, j2) corresponds to the channel region A (i2, j2), i1, i2, j1, and j2 satisfy a relationship of 1≤i1, i2≤m, 1≤j1, j2≤n, i1 ≠ i2, j1 ≠ j2. The decoder structure includes a substrate, a first source / drain region, a second source / drain region, a channel, a first insulating layer, a gate, a second insulating layer, and a metal layer. The first source / drain region and the second source / drain region are located on the substrate in the transistor region A (i1, j1). The channel on the channel region A (i2, j2) is disposed in the substrate. The first insulating layer covers the first source / drain region, the second source / drain region, and the channel. The gate is disposed between the first source / drain region and the second source / drain region on the first insulating layer. The second insulating layer covers the gate. The metal layer is located above the gate and electrically connects the gates in the same column to form a decoder input.

When transistor node N (i1, j1) and channel node N (i2, j2) are on the same row and connected to each other, the first source / drain region of transistor region A (i1, j1) and The second source / drain region is connected to the channel of the channel region A (i2, j2).

When the transistor node N (i1, j1) is next to the transistor node N (i3, j3) on the same row, the first source / drain region or second of the transistor node N (i1, j1). The source / drain region is connected to the first source / drain region or the second source / drain region of the transistor node N (i3, j3).

 When the channel node [N (i2, j2)] is adjacent to the channel node [N (i4, j4) on the same row, the channel of the channel node [N (i2, j2)] becomes the channel node [N (i4, j4). )] Channel.

One terminal of the node on the same column is for receiving a signal, the other terminal of the node is connected to the data line, and the data line is used to output the signal, respectively. A metal layer is used to electrically connect the gates of the transistor nodes on the same column to form a Y decoder input that receives digital signal data.

According to another object of the present invention, a method of manufacturing the structure of a decoder is provided. The decoder comprises m signal lines, n decoder inputs, p transistor nodes and (m x n-p) channel nodes, where p is an integer less than m x n. First, a substrate is provided, and an insulating layer is formed on the substrate. Next, p gates are formed on the transistor region, p first source / drain regions and p second source / drain regions are formed on the transistor region, while (mxn-p) channels are channels. It is formed on the area to complete m signal lines. Thereafter, a second insulating layer is formed, and the decoder input is formed by patterning and selectively depositing a metal layer. The decoder input is electrically connected to the gate by a plurality of contacts.

The above and other advantages of the present invention will become more apparent by describing the preferred embodiments of the present invention in detail with reference to the accompanying drawings.

As shown in FIG. 9A, an arrangement of the decoder 302 of FIG. 3 in accordance with a preferred embodiment of the present invention is shown. The decoder 302 includes 8x6 nodes, each node including a plurality of transistor nodes 310 and a plurality of channel nodes 320 respectively corresponding to transistor regions and channel regions. The placement of each transistor node 310 includes a gate, a source and a drain. Channel node 320 includes a channel. Gates on the same column of the transistor node are connected to each other to form decoder inputs B (0) to B (5). The transistor node and the channel node on each row are connected in series, thus forming signal lines L (0) to L (7).

FIG. 9B shows a cross-sectional view of the signal line L (0) in FIG. 9A. The signal line L (0) includes a substrate 924, a first source / drain region 932, a second source / drain region 934, a channel region 936, a first insulating layer 928, and a gate 930. ), A second insulating layer 938, and a metal layer 940. The first source / drain region 932 and the second source / drain region 934 are the substrates 924 in the transistor regions A (0,1), A (0,3), and A (0,5). ) Is located within. Channel 936 is disposed within substrate 924 in channel regions A (0,0), A (0,2), A (0,4). The first source / drain region 932, the second source / drain region 934, and the channel 936 are covered with a first insulating layer 928. The gate 930 formed on the first insulating layer 928 is disposed between the first source / drain region 932 and the second source / drain region 934. Further, the gate 930 is covered with a second insulating layer 938, and the metal layer 940 formed on the second insulating layer 938 is electrically connected to the gate 930.

Adjacent transistor nodes N (0,1) on the same row and channel nodes N (0,0) are connected to each other. The first source / drain region 932 is connected to the channel of the channel region A (0, 0). The gates 930 of the transistors on the same column are electrically connected to each other by the metal layer 940, so that six decoder inputs are formed to receive the data signal D (n).

The transistor node 310 of the present invention is manufactured using a conventional process. The gate 930, the first source / drain region 932 and the second source / drain region 934 are sequentially formed. Fabrication of channel node 320 is completed by forming a channel. Without an additional mask, channel 936, first source / drain region 932 and second source / drain region 934 are formed simultaneously. 10A to 10E are cross-sectional views of manufacturing the signal line L (0) of the decoder 302 according to the preferred embodiment of the present invention. In FIG. 10A, a substrate 924 is provided. Next, as shown in FIGS. 10B and 10C, an insulating layer 928 is formed on the substrate 924, and a plurality of gates 930 are formed in the transistor regions A (0,1) and A (0,3). , A (0,5)]. Referring to FIG. 10D, the channel 936 is A (0,0), A (because the gate does not cover the channel regions A (0,0), A (0,2), A (0,4)). It is formed directly in the substrate 924 in 0,2) and A (0,4). Thus, signal lines L (0) to L (7) are formed. On the other hand, the channels of the channel regions A (0,0), A (0,2) and A (0,4) are transistor regions A (0,1), A (0,3) and A (0,0). 5)] and the first source / drain region 932 and the second source / drain region 934 are electrically connected. Next, referring to FIG. 10E, a metal layer 940 is formed on the substrate 924 and is patterned to form decoder inputs B (0) through B (5), which are formed from decoder inputs B (0) through. B (5)] is electrically connected to the gate 930 on the same column by the plurality of contacts 942.

Since the channel of the channel region and the source / drain region of the transistor region are formed simultaneously in the present invention, there is no need to add P-type and N-type channels as in the conventional method. Thus, two masks are reduced in the present invention. Moreover, the circuit width in the present invention is reduced without forming a short circuit by the metal layer. Thus, smaller circuitry decoder placement is achieved without additional masks.

Given the above description, many other features, modifications, and improvements will become apparent to those skilled in the art. Accordingly, such other features, modifications, and improvements are considered to be part of this invention, and the scope of the invention should be determined by the following claims.

1 is a diagram showing a driving circuit for a color TFT LCD.

FIG. 2 is a block diagram of a driving circuit of the DAC of FIG. 1.

3 is a conventional circuit diagram of the N-type DAC device of FIG.

4A is a circuit diagram of a transistor node.

4B is a circuit diagram of a channel node.

5 is a diagram showing a conventional arrangement of the decoder of FIG.

6A to 6E are cross-sectional views illustrating the manufacture of the signal line L (0) of FIG. 5.

FIG. 7 illustrates another conventional arrangement of the decoder of FIG. 3.

8A to 8E are cross-sectional views illustrating the manufacture of the signal line L (0) of FIG. 7.

9A is a diagram illustrating an arrangement of the decoder of FIG. 3 according to a preferred embodiment of the present invention.

FIG. 9B is a cross-sectional view of the signal line L (0) in FIG. 9A.

10A to 10E are cross-sectional views showing the manufacture of the signal line L (0) of the decoder according to the preferred embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

104; Scan driver 106; Data driver

108; DAC 202; P-type DAC device

204; N-type DAC device 302; Decoder

310; Transistor node 320; Channel node

526; Doped region 736; Short circuit device

930; Gate 932; First source / drain region

934; Second source / drain region 936; Channel area

940; Metal layer

Claims (9)

Each having a plurality of mxn nodes including a plurality of transistor nodes and a plurality of channel nodes, one of the transistor nodes N (i1, j1) corresponds to a transistor region A (i1, j1), and the channel One of the nodes N (i2, j2) corresponds to the channel region A (i2, j2), wherein 1≤i1, i2≤m, 1≤j1, j2≤n, i1 ≠ i2, j1 ≠ j2 As a decoder structure, Board, A first source / drain region and a second source / drain region formed in the substrate in the transistor region A (i1, j1), A channel formed in the substrate in the channel region A (i2, j2), A first insulating layer formed on the first source / drain region, the second source / drain region, and the channel, A gate formed on the first insulating layer between the first source / drain region and the second source / drain region, A second insulating layer formed on the gate, and A metal layer formed over the gate and electrically connected to the gate Including; The first source / drain region of the transistor region A (i1, j1) when the transistor node N (i1, j1) is next to the channel node N (i2, j2) on the same row One of the and second source / drain regions is connected with the channel of the channel region A (i2, j2), When the transistor node N (i1, j1) is next to the transistor node N (i3, j3) on the same row, the first source / drain of the transistor node N (i1, j1) One of a region and a second source / drain region is connected to one of the first source / drain region and the second source / drain region of the transistor node [N (i3, j3)],  When the channel node N (i2, j2) is next to the channel node N (i4, j4) on the same row, the channel of the channel node N (i2, j2) is the channel node. Connected to the channel of [N (i4, j4)], The metal layer electrically connects the gates of the transistor nodes on the same column to form a plurality of decoder inputs for receiving digital signal data. The method of claim 1, And the first insulating layer is an oxide layer. a decoder having mxn nodes comprising p transistor nodes and (mxn-p) channel nodes, the transistor nodes corresponding to a transistor region, the channel nodes corresponding to a channel region, p being an integer less than mxn As a method of manufacturing Providing a substrate, Forming an insulating layer on the substrate, Forming p gates on the transistor region, Forming p first sources / drains and p second sources / drains on the transistor region, and forming m signal lines by forming (m × n−p) channels on the channel region; Forming a second insulating layer, and Forming n decoder inputs electrically connected to the gates by a plurality of contacts on the second insulating layer How to include. The method of claim 3, And the first insulating layer is an oxide layer. A decoder structure having a plurality of transistor nodes and a plurality of channel nodes, one of the transistor nodes corresponding to a transistor region, and one of the channel nodes corresponding to a channel region, Board, A transistor disposed in the transistor region, the transistor comprising source and drain regions formed in the substrate and next to the gate; A metal layer disposed on the gate and insulated from the substrate, and A channel formed in the channel region in the substrate Including; When a first transistor node of the transistor nodes is connected to a first channel node of the channel nodes on the same row, one of the source / drain regions of the transistor region is connected with the channel of the channel region, When the first transistor node of the transistor nodes is connected to a second transistor node of the transistor nodes on the same row, one of the source / drain regions of the first transistor node is the source / drain of the second transistor node. Connected to one of the drain regions, When the first channel node is connected to a second channel node of the channel node on the same row, the channel of the first channel node is connected to the channel of the second channel node, And the metal layer electrically connects the gates of the transistor nodes on the same column by at least one contact to form a plurality of decoder inputs for receiving digital signal data. The method of claim 5, And a first insulating layer between the gate and the substrate to electrically insulate the gate and the substrate. The method of claim 5, And a second insulating layer between the metal layer and the substrate to insulate the metal layer and the substrate. The method of claim 5, And the channel region on the substrate does not include the gate of the transistor. The method of claim 5, And a metal layer in the channel region is electrically insulated from the channel region.