JPH02110974A - Semiconductor circuit - Google Patents
Semiconductor circuitInfo
- Publication number
- JPH02110974A JPH02110974A JP26429688A JP26429688A JPH02110974A JP H02110974 A JPH02110974 A JP H02110974A JP 26429688 A JP26429688 A JP 26429688A JP 26429688 A JP26429688 A JP 26429688A JP H02110974 A JPH02110974 A JP H02110974A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- semiconductor substrate
- mos transistor
- electrode plate
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78612—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、絶縁膜上に形成した半導体回路に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor circuit formed on an insulating film.
第３図は従来の絶縁膜上に形成した半導体回路を示す断
面図であり、図において、１は絶縁膜、２は絶縁膜１上
に形成したＭｏ３）−ランジスタの半導体基板、ｎはｎ
形半導体からなるソース・ドレイン領域、ＰはＰ形半導
体からなるチャネル領域、Ｇは半導体基板２上に薄い絶
縁膜を介して形成したゲート電極、Ａｆｔはソース・ド
レイン領域ｎに接続された配線、１ａは半導体回路上に
形成した絶縁膜である。FIG. 3 is a cross-sectional view showing a conventional semiconductor circuit formed on an insulating film. In the figure, 1 is an insulating film, 2 is a Mo3)-transistor semiconductor substrate formed on the insulating film 1, and n is an n
P is a channel region made of a P-type semiconductor, G is a gate electrode formed on the semiconductor substrate 2 via a thin insulating film, Aft is a wiring connected to the source/drain region n, 1a is an insulating film formed on the semiconductor circuit.
次に動作について説明する。絶縁膜１上に半導体基板２
により形成されたＭｏＳトランジスタも通常のＭＯＳト
ランジスタとその動作は同じであり、ゲート電極Ｇに印
加された電圧により、該ＭＯＳトランジスタのソースか
らドレイン領域に流れる電流を制御する。従って、通常
のバルクの半導体回路と同様に、このＭＯＳトランジス
タを複数個接続し、あるいは他の素子と接続することに
より、半導体回路として動作する。Next, the operation will be explained. Semiconductor substrate 2 on insulating film 1
The MoS transistor formed by the above operates in the same way as a normal MOS transistor, and the voltage applied to the gate electrode G controls the current flowing from the source to the drain region of the MOS transistor. Therefore, like a normal bulk semiconductor circuit, by connecting a plurality of these MOS transistors or connecting them to other elements, it operates as a semiconductor circuit.
従来の半導体回路は以上のように構成されているので、
Ｍｏ５）−ランジスタの半導体基板の電位が固定できず
、該ＭＯＳトランジスタの電流−電圧特性に第２図に示
すようにキンク現象という、電流の飽和特性を損なう現
象が生じ、特にアナログ回路の動作に悪影響を及ぼすと
いう課題があった。Conventional semiconductor circuits are configured as described above, so
Mo5) - The potential of the semiconductor substrate of the transistor cannot be fixed, and as shown in Figure 2, a kink phenomenon occurs in the current-voltage characteristics of the MOS transistor, a phenomenon that impairs the saturation characteristics of the current, which particularly affects the operation of analog circuits. There was the issue of negative effects.
尚、近似技術としてアイ−イーイーアイイーデイ−エム
８１ フォローティング サブストレイト エフエクツ
イン ニスオーニス ブイエルエスア、イエス（ＩＥ
ＥＥ ＩＥＤＭ８１ＦＬＯＡＴＩＮＧ ５ＵＢＳＴＲＡ
ＴＥ ＥＦＦＥＣＴＳ ＩＮ ＳＯ５ＶＬＳＩＳ）カあ
る。In addition, as an approximation technique, IEDM81 Following Substrate Effects
EE IEDM81FLOATING 5UBSTRA
TE EFFECTS IN SO5VLSIS).
この発明は上記のような課題を解消するためになされた
もので、キンク現象を抑制し、電流の飽和特性の良いＭ
ＯＳトランジスタを形成することによって、絶縁膜上に
特性の良いアナログ回路を形成することができる半導体
回路を得ることを目的とする。This invention was made in order to solve the above-mentioned problems, and it suppresses the kink phenomenon and provides an M with good current saturation characteristics.
An object of the present invention is to obtain a semiconductor circuit in which an analog circuit with good characteristics can be formed on an insulating film by forming an OS transistor.
（課題を解決するための手段〕
この発明に係る半導体回路は、絶縁膜内に電極板を備え
、該電極板と絶縁膜上に形成したＭｏＳトランジスタの
半導体基板をスルーホールによって電気的に接続したも
のである。(Means for Solving the Problems) A semiconductor circuit according to the present invention includes an electrode plate within an insulating film, and electrically connects the electrode plate to a semiconductor substrate of a MoS transistor formed on the insulating film through a through hole. It is something.
この発明における絶縁膜上のＭｏＳトランジスタの半導
体基板は、その電位がスルーホールと絶縁膜内に形成し
た電極板を介して固定電位に接続されて固定される。In the semiconductor substrate of the MoS transistor on the insulating film in this invention, the potential thereof is connected to a fixed potential through the through hole and the electrode plate formed in the insulating film, and is fixed.
以下、この発明の一実施例を図について説明する。第１
図において、１０は絶縁膜１内に形成した電極板、２０
は絶縁膜１上に形成したＭＯＳトランジスタの半導体基
板２と電極板１０を接続するスルーホール、３０は電極
板１０の電位をスルーホール２０とＰ形半導体基板４０
と配線ＡＪＺ、を介して固定電位に接続する端子である
。その他の符号は、第３図に示す従来例と同じである。An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 10 is an electrode plate formed within the insulating film 1;
30 is a through hole connecting the semiconductor substrate 2 of the MOS transistor formed on the insulating film 1 and the electrode plate 10; 30 is the through hole 20 connecting the potential of the electrode plate 10 to the P-type semiconductor substrate 40;
This is a terminal connected to a fixed potential via the wiring AJZ and the wiring AJZ. Other symbols are the same as those in the conventional example shown in FIG.
次に動作について説明する。基本的な動作は従来例に示
したものと同じであり、ゲート電極Ｇに印加する電圧に
よって、ソース領域からドレイン領域に流れる電流を制
御するＭｏＳトランジスタの半導体基板２によって回路
が構成されている。但し、この場合は、スルーホール２
０によって各ＭＯＳトランジスタの半導体基板２が絶縁
膜１内の電極板１０に接続され、該電極板１０はスルー
ホール２０．Ｐ形半導体基板４０を介して配線ＡＪ２．
で端子３０に接続されているため、該端子３０に固定電
位を与えることにより、絶縁膜１上の複数のＭＯＳ）ラ
ンジスタの半導体基板２の電位を一斉に固定することが
でとる。このため絶縁膜１上に形成したＭＯＳ）−ラン
ジスタの半導体基板２で生ずるキンク現象を抑制でき、
特性の良いアナログ回路を形成することができる。Next, the operation will be explained. The basic operation is the same as that shown in the conventional example, and the circuit is constituted by a semiconductor substrate 2 of a MoS transistor that controls the current flowing from the source region to the drain region by the voltage applied to the gate electrode G. However, in this case, through hole 2
0, the semiconductor substrate 2 of each MOS transistor is connected to an electrode plate 10 in the insulating film 1, and the electrode plate 10 is connected to the through hole 20. Wiring AJ2. via the P-type semiconductor substrate 40.
By applying a fixed potential to the terminal 30, the potentials of the semiconductor substrate 2 of the plurality of MOS transistors on the insulating film 1 can be fixed all at once. Therefore, the kink phenomenon that occurs in the semiconductor substrate 2 of the MOS transistor formed on the insulating film 1 can be suppressed.
Analog circuits with good characteristics can be formed.
なお、上記実施例では、絶縁膜１上に半導体回路を一段
設けたものを示したが、第４図に示すように該半導体回
路上に絶縁膜１ａ、１を形成し、その上に更に同様の構
成で半導体回路を形成し、全体でｎ段（ｎは整数であり
、この実施例ではｎ＝２、即ち２段の例を示している。In the above embodiment, one stage of the semiconductor circuit is provided on the insulating film 1, but as shown in FIG. A semiconductor circuit is formed with the following configuration, and has a total of n stages (n is an integer, and this embodiment shows an example of n=2, that is, two stages).
）の積層型半導体回路を構成した場合も、各段の間の絶
縁膜１内にそれぞれ電極板１０を形成し、その各電極板
１０とそれぞれの上に形成したＭｏＳトランジスタの半
導体基板２をスルーホール２０で接続し、端子３０から
固定電位を与えることによって、積層型半導体回路の各
段に形成したＭｏＳトランジスタの半導体基板２からキ
ンク現象を抑制することができ、特性の良いアナログ回
路を形成することができる。), the electrode plates 10 are formed in the insulating film 1 between each stage, and the semiconductor substrates 2 of the MoS transistors formed on each electrode plate 10 are passed through. By connecting through the hole 20 and applying a fixed potential from the terminal 30, it is possible to suppress the kink phenomenon from the semiconductor substrate 2 of the MoS transistors formed in each stage of the stacked semiconductor circuit, forming an analog circuit with good characteristics. be able to.
（発明の効果）
以上のように、この発明によれば絶縁膜上に形成したＭ
ＯＳトランジスタの半導体基板の電位を固定するように
構成したので、キンク現象を抑制することができ、特性
の良いアナログ回路が得られる効果がある。(Effects of the Invention) As described above, according to the present invention, M
Since the potential of the semiconductor substrate of the OS transistor is fixed, the kink phenomenon can be suppressed, and an analog circuit with good characteristics can be obtained.
第１図はこの発明の一実施例による半導体回路を示す断
面図、第２図はＭＯＳトランジスタの半導体基板の電流
−電圧特性にキンク現象が生じている場合の特性図、第
３図は従来の半導体回路を示す断面図、第４図はこの発
明を２段の積層型半導体回路とした場合の一実施例を示
す断面図である。
１．１ａは絶縁膜、２はＭＯＳトランジスタの半導体基
板、ｎはソース・ドレイン領域、Ｐはチャネル領域、Ｇ
はゲート電極、ＡｊＺ。
Ａｌ１．は配線、１０は電極板、２０はスルーホール、
３０は端子１．４０はＰ形半導体基板。
なお、図中、同一符号は同一、又は相当部分を示す。
特許出願人 三菱電機株式会社
第１
ｏｓFIG. 1 is a sectional view showing a semiconductor circuit according to an embodiment of the present invention, FIG. 2 is a characteristic diagram when a kink phenomenon occurs in the current-voltage characteristics of a semiconductor substrate of a MOS transistor, and FIG. 3 is a diagram showing a conventional semiconductor circuit. FIG. 4 is a cross-sectional view showing an embodiment of the present invention as a two-stage stacked semiconductor circuit. 1.1a is an insulating film, 2 is a semiconductor substrate of a MOS transistor, n is a source/drain region, P is a channel region, G
is the gate electrode, AjZ. Al1. is the wiring, 10 is the electrode plate, 20 is the through hole,
30 is a terminal 1.40 is a P-type semiconductor substrate. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Patent applicant: Mitsubishi Electric Corporation 1st OS
Claims (1)
ている半導体回路において、外部より固定電位を与える
端子を有する電極板と、前記電極板と前記ＭＯＳトラン
ジスタの半導体基板を電気的に接続するスルーホールと
が前記絶縁膜内に設けられていることを特徴とする半導
体回路。In a semiconductor circuit in which a semiconductor substrate of a MOS transistor is provided on an insulating film, an electrode plate having a terminal that applies a fixed potential from the outside, and a through hole that electrically connects the electrode plate and the semiconductor substrate of the MOS transistor. is provided in the insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26429688A JPH02110974A (en) | 1988-10-19 | 1988-10-19 | Semiconductor circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26429688A JPH02110974A (en) | 1988-10-19 | 1988-10-19 | Semiconductor circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02110974A true JPH02110974A (en) | 1990-04-24 |
Family
ID=17401201
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26429688A Pending JPH02110974A (en) | 1988-10-19 | 1988-10-19 | Semiconductor circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02110974A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011008895A1 (en) * | 2009-07-15 | 2011-01-20 | Io Semiconductor | Semiconductor-on-insulator with back side body connection |
| CN102576692A (en) * | 2009-07-15 | 2012-07-11 | Io半导体公司 | Semiconductor-on-insulator with back side heat dissipation |
| US8912646B2 (en) | 2009-07-15 | 2014-12-16 | Silanna Semiconductor U.S.A., Inc. | Integrated circuit assembly and method of making |
| US9034732B2 (en) | 2009-07-15 | 2015-05-19 | Silanna Semiconductor U.S.A., Inc. | Semiconductor-on-insulator with back side support layer |
| US9576937B2 (en) | 2012-12-21 | 2017-02-21 | Qualcomm Incorporated | Back-to-back stacked integrated circuit assembly |
| US9843235B2 (en) | 2013-12-27 | 2017-12-12 | Mabuchi Motor Co., Ltd. | Motor |
| US10217822B2 (en) | 2009-07-15 | 2019-02-26 | Qualcomm Incorporated | Semiconductor-on-insulator with back side heat dissipation |
-
1988
- 1988-10-19 JP JP26429688A patent/JPH02110974A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8921168B2 (en) | 2009-07-15 | 2014-12-30 | Silanna Semiconductor U.S.A., Inc. | Thin integrated circuit chip-on-board assembly and method of making |
| CN102576692A (en) * | 2009-07-15 | 2012-07-11 | Io半导体公司 | Semiconductor-on-insulator with back side heat dissipation |
| US8232597B2 (en) | 2009-07-15 | 2012-07-31 | Io Semiconductor, Inc. | Semiconductor-on-insulator with back side connection |
| US8357975B2 (en) | 2009-07-15 | 2013-01-22 | Io Semiconductor, Inc. | Semiconductor-on-insulator with back side connection |
| US8859347B2 (en) | 2009-07-15 | 2014-10-14 | Silanna Semiconductor U.S.A., Inc. | Semiconductor-on-insulator with back side body connection |
| US8912646B2 (en) | 2009-07-15 | 2014-12-16 | Silanna Semiconductor U.S.A., Inc. | Integrated circuit assembly and method of making |
| WO2011008895A1 (en) * | 2009-07-15 | 2011-01-20 | Io Semiconductor | Semiconductor-on-insulator with back side body connection |
| US9029201B2 (en) | 2009-07-15 | 2015-05-12 | Silanna Semiconductor U.S.A., Inc. | Semiconductor-on-insulator with back side heat dissipation |
| US9034732B2 (en) | 2009-07-15 | 2015-05-19 | Silanna Semiconductor U.S.A., Inc. | Semiconductor-on-insulator with back side support layer |
| US9748272B2 (en) | 2009-07-15 | 2017-08-29 | Qualcomm Incorporated | Semiconductor-on-insulator with back side strain inducing material |
| US10217822B2 (en) | 2009-07-15 | 2019-02-26 | Qualcomm Incorporated | Semiconductor-on-insulator with back side heat dissipation |
| US9576937B2 (en) | 2012-12-21 | 2017-02-21 | Qualcomm Incorporated | Back-to-back stacked integrated circuit assembly |
| US9843235B2 (en) | 2013-12-27 | 2017-12-12 | Mabuchi Motor Co., Ltd. | Motor |
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