JPS6124247A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a gate array type semiconductor device forming specified capacitor without deteriorating the general-purpose properties thereof by a methed wherein wirings are connected to utilize each MOS transistor of basic cell provided for constituting a logic circuit as a capacitor. CONSTITUTION:One lower wiring M1 supplied with power supply voltage VDD is connected to three sources of two P type MOS transistors or P type diffusion regions 3, 4, 5 as drains through lower contacts C1, C1, C1 while the other lower wiring M1 supplied with earth VSS is connected to three N type diffusion regions 6, 7, 8 of two N type MOS transistors through lower contacts C1, C1, C1. Besides, contact spaces 10, 20 of two gates 1, 2 are connected to the lower layer wiring M1 through contacts C1, C1 while the lower layer wiring M1 is further connected to an upper layer wiring M2 through upper layer contact C2. Through these procedures, a capacitor unit represented by a figure wherein a capacitor comprising four gate capacitors of each transistor T11, T12, T21, T22 parallel-connected is constituted between a terminal A and a semiconductor substrate may be provided.

Description

DETAILED DESCRIPTION OF THE INVENTION A) Industrial Application Field The present invention relates to a gate array type semiconductor device in which a plurality of basic cells each consisting of a specific number of P-type and N-type MOS transistors are arranged in rows and columns.

(Example) Conventional technology In the conventional gate array type semiconductor device, the
As shown in Japanese Patent No. 3905, basic cells having a logic function of a C-MO8 configuration are automatically wired to perform a desired logic operation. However, in such a gate array type semiconductor device, capacity cannot be realized in principle, and external connections have to depend on components. This means that the master chip, which is in the state immediately before the wiring and contact hole formation process, is made of a general-purpose chip.However, the problems that this mass (c) invention aims to solve are as follows: This was done in view of the disadvantages, and the purpose is to provide a gate array type semiconductor device that can form a desired capacitance without impairing its versatility.

2) Means for Solving the Problems The gate array type semiconductor device of the present invention
I31. A capacitor unit is constructed by combining a MOS transistor and an N-type MO8I transistor gate capacitance or a composite capacitance of gate capacitance and junction capacitance.

Function: In the semiconductor device of the present invention, a specific capacitor is not formed in advance, but each MOS transistor of a basic cell prepared to constitute a logic circuit is connected and wired to be used as a capacitor. Depending on the situation, the capacity can be increased.

(F) Embodiment FIG. 3 shows the planar form of a basic cell of a gate array type LSI when used as a master chip. In the same figure, (1), (2)
are two gate electrodes arranged in parallel with each other with an insulating film written over the semiconductor substrate, and a wide contact space (2) is provided in the middle of each gate electrode. (3), (4
), (5) are provided on the semiconductor substrate on one end side of both the gate electrodes (1), (2), and these gate electrodes (1),
This is a P-type diffusion region divided into three in (2). On the other hand (6
), (7), and (8) are both gate electrodes (1) and (2) above.
This is an N-type diffusion region provided on the semiconductor substrate on the other end side and divided into three by both gate electrodes (1) and (2).

That is, this basic cell includes two P-type MO3) transistors having a common source or drain and two N-type MOS transistors having a common source or drain.

Using such a basic cell, two-man power (l) as shown in Figure 4(b)
In order to realize a NAND circuit of N1)(lN2), lower layer wiring M12M19M1, upper layer wiring M2, lower layer contacts C1 . . . and upper layer contacts C2, C2 as shown in FIG.

When the basic cell as described above is configured as a capacitor unit, the circuit shown in FIG.
Wiring contacts as shown in Fig. 1 are made, and as shown in Fig. 2 (
In order to realize the circuit bl, wiring contacts as shown in the figure (bl) are made.

The first embodiment will be described in detail below based on FIG. 1 (al). In the capacitor unit shown in FIG. P-type diffusion regions (3), (4), (5) which are the sources or drains of the two P-type MOS transistors
) through lower layer contacts -C1, CI, CI, and the other lower layer wiring M1 is supplied with ground Vss,
This wiring M1 is connected to two lower layer contacts C1, C1, C1i to the three N-type diffusion regions (6), (7), and (8) of the pN-type MOS transistor. The contact space portions αα, 2 of the gates (11, +21) are connected to the lower layer wiring M1 through contacts C1, C1, and this lower layer wiring M1 is further coupled to the upper layer wiring M2 through an upper layer contact C2.

Therefore, according to the wiring contacts in Figure 1 (al), two P-type MOS transistors T
11. Both the source and drain of T12 are connected in parallel to the power supply Von, while the two N-type MOS transistors T21
, the sources and drains of T22 are both connected in parallel to Vss, that is, the four transistors T11
, T12, T21, and T22, the generation of current in the channel portion under the gate of each transistor 1'l1, T12, T21, and T22 is prevented by making the potential difference between the source and drain of each transistor 1'l1, T12, T21, and T22 zero. In a state where the potential of the channel part of the lever is stabilized, each transistor T11, T12, T21, T22 (7) A capacitor in which four gate capacitors are connected in parallel is configured between the terminal and the semiconductor substrate. .

Next, the second embodiment will be described in detail based on FIG. 2 (al(bl). The capacity unit shown in FIG.
The lower layer wiring M1 to which Vss is supplied and the lower layer wiring M1 to which ground Vss is supplied are not coupled and are P-type MOS.
The three P-type diffusion regions (3), (4), and (5), which are the sources or drains of the transistor, are connected to the lower layer wiring M1 and the lower layer contacts CI, C1, CI, while the N
The 7N type diffusion regions (61, +71, (8), which are the three sources or drains of the type MOS transistor, are also connected to the lower layer wiring M1 through lower layer contacts C1, C1, C1. Furthermore, both gate electrodes ( 11 (contact space α0 of 21) is also tangential to the lower layer wiring M1 and the lower layer contacts CI, C1.These three lower layer wirings M1.M1.M1 are connected to the upper layer wiring M2 and the upper layer contacts C2, C2 and Cz are connected to each other.

Therefore, according to such a wiring contact of the 211th (al), transistor T11 (4 MOS as shown in bl) in the same figure
, T12, T21, and T22, the voltage at terminal A is applied to the gate, source, and drain of each of T22, so that in addition to the gate capacitance in the first embodiment shown in FIG. The capacitors are connected in parallel, and a larger capacitance can be obtained between the terminal A and the semiconductor substrate than in the first embodiment.

The capacity value of each capacity unit according to the above embodiment is 1PF.
To some extent, by using a plurality of basic cells as a capacity unit, it is possible to achieve a capacity of up to several QPF. Since the usage rate of basic cells as a logic circuit in a normal gate array type LSI is limited to about 90%, the remaining 10% or more of unused basic cells can be allocated as a capacity unit. There is no increase in area due to additional capacity.

(G) Effects of the Invention As is clear from the above description, the gate array type semiconductor device of the present invention can configure basic cells as capacitor units, so it is not necessary to form a specific capacitance in advance on the master chip itself. Furthermore, basic cells not used as logic circuits can be used as capacitor units, which greatly contributes to improving the versatility of such semiconductor devices.

[Brief explanation of the drawing]

FIG. 1(3) and (bl are main part wiring diagrams and circuit diagrams of one embodiment of the semiconductor device of the present invention, and FIG. 2(al) and (b) are other embodiments of the semiconductor device of the present invention. Main part wiring diagram and its circuit diagram, Fig. 3 is a plane M before wiring of main parts of a general semiconductor device, and Fig. 4 (a) and (b) are main part wiring diagrams of a general semiconductor device. , and its circuit diagram. +14+21...gate electrode, (31(4)(51・
...P type diffusion region, (6) (7) (8)...N type diffusion region, T11. T12, T21, T22...MOS
transistor.

Claims (1)

[Claims] 1) A specific number of P-type MOS transistors and a specific number of N-type M
In a gate array type semiconductor device in which a plurality of basic cells each consisting of an OS transistor and an N
A semiconductor device characterized in that a capacitance unit is formed by combining gate capacitance of a type MOS transistor or a composite capacitance of the gate capacitance and a junction capacitance.