JPS62256468A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To constitute a delay circuit longer in delay time than the one using an inverter circuit in the same number of constituent cells by a method wherein gate electrodes and source and drain regions which are the constituent elements of each transistor at the internal region are each used as a resistor element and a capacitance element. CONSTITUTION:The parasitic resistance of each gate is connected in series with wirings L1-L4 and the parasitic capacities of each source and drain regions are connected in parallel. Accordingly, a resistor R shows the sum of the parasitic resistances between the terminals of the gate electrodes G1-G4 of each transistor and a capacity C shows the sum of the parasitic capacities of the source and drain regions P1-P3 and N1-N3 of each transistor. In case a passive circuit or an active circuit is thought as a delay element consisting of the same one cell, the passive circuit consisting of the parasitic resistances and the parasitic capacities is more efficient than the active circuit consisting of the transistors. By using each of the gate electrodes and the source and drain regions as an R element and a C element in such a way, a delay circuit more efficient than the one using an inverter circuit in a number of necessary cells can be made without providing a special element at the internal region.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and more particularly to an MO8 gate array having a delay circuit in its internal circuit.

[Conventional technology]

Generally, an integrated circuit with a CMOS gate array structure is composed of an internal basic cell and an external I10 cell. The internal basic cell is a collection of unit elements to obtain the desired logic function, and the external I10 cell constitutes a logic level conversion circuit between the inside and outside of the integrated circuit and a buffer for reinforcing the driving capacity. This is a group of elements for

FIG. 4 shows an example of the structure of a basic cell inside a CMOS gate array. P-channel transistor (Pch Tr)
) source/drain regions PL, P2.degree.P3ri can be used as either source or drain regions as required on the circuit. A gate electrode G is formed to separate those regions.
1, G2 are placed and the channel region TI performs an effective transistor operation.

T2 is formed. Similarly, N-channel transistor (
Nch T'r) is also the source/drain region Nl.

N2. N3 and gate electrode G3. G4, and a channel region T3. T4 is formed. Both ends of each gate electrode are formed wide so that connection terminals can be formed.

A plurality of basic internal cells as described above are arranged in an array in the internal region of the chip, and a desired logic function can be obtained by interconnecting them with a wiring pattern.

The configuration of the internal basic cells of general gate arrays, including the basic cell structure example above, is designed based on the manufacturing process, taking into account constraints on cell occupation area, which has a strong correlation with chip size, and compatibility with computer-based automatic design. Consideration has been given to achieving the fastest circuit operation possible.

[Problem that the invention seeks to solve]

When constructing a delay circuit on the seven lays of internal basic cells as described above, the conventional method is to provide a delay function by arranging multiple stages of inverter circuits. However, when the operating speed of the unit inverter circuit is high, it is necessary to use a large number of internal basic cells to obtain a desired delay time, which greatly hinders effective use of the internal area.

[Means for solving problems]

The present invention is intended to solve the above problems, and includes a delay circuit in which the gate electrode of a transistor constituting a basic cell in an internal region is used as a resistance element, and the source or drain region is used as a capacitance element.

The semiconductor integrated circuit of the present invention has an internal region in which basic cells consisting of MOS transistors are arranged in a play shape,
The present invention is characterized in that it includes a circuit in which the gate electrodes of some MOS transistors in the basic cell array are resistive elements and the source or drain regions are capacitive elements.

〔Example〕

The present invention will be explained below with reference to the drawings.

FIG. 1 is a plan view of one embodiment of the present invention. P-channel transistor source/drain region PL, P2
, P3, source/drain regions Nl, N2, N3 of N-channel transistors and gate electrodes Gl, G2
．． G3. G4 indicates the constituent elements of each transistor as in FIG. Furthermore, in FIG. 1, the wiring #Lo, Ll,
This shows a state in which Lz, L3, and L4 connect each gate electrode and source/drain region.

FIG. 2 is an equivalent circuit of FIG. 1. Wiring IJ in Figure 1
I-L,a connects the parasitic resistance of each gate in series, and connects the parasitic capacitance of each north drain region in parallel.

Therefore, the resistor R shown in FIG. 2 is connected to the gate electrodes Gl, G2 . G3. Indicates the sum of parasitic resistance between the terminals of G4, and the capacitance C is the source/drain region P of each transistor.
It shows the sum of the parasitic capacitances of I, P2°P3, Nl, Nz, and N3.

When the material of the gate electrode is polysilicon and the source/drain regions are formed by general impurity diffusion, the value of resistance R is ~10''Ω and the value of resistance C is ~I, although it depends on the device dimensions.
You can also order ff″13F.

For example, in an equivalent circuit as shown in Fig. 2, Ω is set to R-=5.

When c=o, spF', time constant CRti2.5nse
It also becomes c. On the other hand, when an inverter is configured with the same basic cells, the delay time between input and output is less than Ins.

The definition of the time constant determined by CR and the delay time of an inverter is slightly different, but when considered as a delay element using the same cell, a passive circuit using parasitic resistance and capacitance is much more effective than an active circuit using transistors. 0 ゛By using the gate electrode and the north drain region as a C element in this way, the efficiency can be improved in terms of the number of cells required for the inverter circuit without providing special elements in the internal region. You can create a good delay circuit.

FIG. 3 is an example of an applied circuit of the present invention for obtaining a larger delay time. If the CR connection in Fig. 1 is implemented over a large number of cells, the delay time can be increased, but in this case,
It takes a long time to maintain the intermediate level between High and Low on the output waveform, and a large amount of through current flows due to simultaneous ON of the P-channel transistor and the N-channel transistor. Therefore, as shown in the figure, by incorporating a normal CMOS bus, B1, and B2 in the middle of a delay circuit using C@R and performing waveform shaping, a highly stable delay circuit with less cross current can be obtained.

〔Effect of the invention〕

As explained above, the present invention uses the gate electrode and source/drain regions, which are the constituent elements of the transistor in the internal region, as resistors and capacitors, respectively, so that it is superior to the inverter circuit with the same number of cells. It is possible to construct a delay circuit with a very long delay time, and it has a great effect on gate array design with high cell usage efficiency.

[Brief explanation of drawings]

FIG. 1 is a schematic plan view showing an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of FIG. 1, FIG. 3 is an equivalent circuit diagram of an application example of the present invention, and FIG. OPI, P2. P3...Source/drain region of P channel transistor JiLN1. N2. N3...
. . . Source/drain regions of N-channel transistors, Gl, G2 . G3. G4...Gate electrode,
T1. T2. T3. T3...channel area,
几. R1, Rz, R3...Resistance, C, CI, C2
, C3...Capacity, LO, Ll, L2, L3
, L4...m, Bx, Bz...C
MOS buffer. Agent Patent Attorney Uchihara "・Japanese, Pa)? l, l?', Fe2: Elephant Techniques (K and Electric) Theft 3 Wards CI, CZ, C3: N/'North, Sono-Ni Pickling °) F3L52 .-CMO5 H”y Fur Kuzu 4 Figure

Claims (2)

[Claims] (1) It has an internal region in which basic cells made of MOS transistors are arranged in an array, and includes a circuit in which the gate electrodes of some of the MOS transistors in the basic cell array are resistive elements and the source or drain regions are capacitive elements. A semiconductor integrated circuit characterized by: (2) Claim 1, characterized in that the circuit constituted by the resistive element and the capacitive element is a delay circuit.
Semiconductor integrated circuit described in Section 1.