JPS58175858A - Mis semiconductor integrated circuit - Google Patents
Mis semiconductor integrated circuitInfo
- Publication number
- JPS58175858A JPS58175858A JP58050403A JP5040383A JPS58175858A JP S58175858 A JPS58175858 A JP S58175858A JP 58050403 A JP58050403 A JP 58050403A JP 5040383 A JP5040383 A JP 5040383A JP S58175858 A JPS58175858 A JP S58175858A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- fet
- load element
- integrated circuit
- drive misfet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 3
- 239000004020 conductor Substances 0.000 claims description 17
- 238000009751 slip forming Methods 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 10
- 230000010354 integration Effects 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 2
- 229920005591 polysilicon Polymers 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 241000283690 Bos taurus Species 0.000 description 1
- 241000270666 Testudines Species 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 本発明はＭＩ８型牛型体導体集積回路する。[Detailed description of the invention] The present invention is an MI8 type bovine conductor integrated circuit.
従来、！Ｐ導体基板上に多結晶な用い抵抗素子を形成す
る場合 １１１図（組で示すように体肢体基板ＩＫ酸化
膜２が形成され、その上面にＰ形の半導体層３が第１図
ｔｂ＋で示すように蛇行状に形成されている。その半導
体層３の電一部とするところはオーミック抵抗な低くす
るためにＰ＋型の半導体層４になっている。この半導体
層３，４の上面にはこれらな保護するために酸化膜２′
が形成され、前記半導体層４領域には穴あけがなされ、
亀ＩＩ５が形成されている。Conventionally,! In the case of forming a polycrystalline resistor element on a P conductor substrate, FIG. The semiconductor layer 3 is formed in a meandering shape.The part of the semiconductor layer 3 that is used as the electric current is a P+ type semiconductor layer 4 in order to lower the ohmic resistance. Oxide film 2' to protect these
is formed, a hole is made in the semiconductor layer 4 region,
Turtle II5 is formed.
しかしながら前記半導体層３．４である抵抗素子は牛導
体基板上に占める面積がかなり大きくなり、集積度を向
上する妨げとなるといった欠点な生じていた。つまり５
２導体基板上に形成するＰをのシリコン層は、抵抗値の
ばらつきを生じさせないために、あまり薄く形成できす
、その最低厚さは３０００Ａはなければならない、この
ように厚さが大きいということは抵抗素子の断面接が大
きいということだから、そのシート抵抗値は減少する。However, the resistive element, which is the semiconductor layer 3.4, occupies a considerably large area on the conductive substrate, resulting in a drawback that it becomes a hindrance to improving the degree of integration. That is 5
The P silicon layer formed on the 2-conductor substrate cannot be formed too thin in order to prevent variations in resistance, and its minimum thickness must be 3000A. Since this means that the cross section of the resistance element is large, its sheet resistance value decreases.
したがって大きな抵抗値を得るためには抵抗素子の長さ
を大きくしなければならない。それ故に抵抗素子の占め
る面積は他の能動素子のそれよりもかなり大きくなって
しまうのである。Therefore, in order to obtain a large resistance value, the length of the resistance element must be increased. Therefore, the area occupied by the resistive element is considerably larger than that of other active elements.
そこで本発明は第２図に示すように、＃ｐ導体基板６上
Ｋｒ１ｌ化膜７が形成され、その上面にポリシリコン８
が形成され、そのポリシリコン８の一部にＰ＋形の拡散
層９１に形成し、その拡散層９の中間部にゲート電極ｌ
Ｏな形成して、ＭＩＳＦＥＴを構成した技術（ＩＥＥＥ
ＴＲＡＮＳＡＣＴＩＯＮ ０ＮＥＬＥＣＴＲＯＮ Ｄ
ＥＶＩＣＥＳ ＶＯＬ ＥＤ−１３Ｎｈ１２ＦＥＢＲ
ＵＡＲＹ １９６６ Ｐ２９０ ｒＴｈｅ Ｐｏ１ｙ
−８口１ｃｏｎ 工ｎ５ｕｌａｔｅｄ Ｑａｔｅ ｐｉ
ｅｌｄ−Ｅｆｆｅｃｔ’ｌ’ｒａｎｓｉｓｔｏｒ Ｊ
） ’に’基にそれを負荷ＭＩＳとして利用し抵抗素子
の占める面積１にΦさくして、ｈＩＰ導体装置の集積度
を向上させるとともに多層配線な可能とするものである
。 □
それ数本発明の目的は集積度を向上させる牛導体ｍ１ｌ
ｌを提供するものである。Therefore, in the present invention, as shown in FIG.
is formed, a P+ type diffusion layer 91 is formed in a part of the polysilicon 8, and a gate electrode l is formed in the middle part of the diffusion layer 9.
Technology to configure MISFET by forming
TRANSACTION 0NELECTRON D
EVICES VOL ED-13Nh12FEBR
UARY 1966 P290 rThe Poly
-8 mouths 1con engineeringn5ulated Qate pi
eld-Effect'l'ransistor J
) Based on this, it is used as a load MIS and the area occupied by the resistive element is reduced in Φ to improve the degree of integration of the hIP conductor device and enable multilayer wiring. □ The purpose of the present invention is to improve the degree of integration of the conductor M1L.
It provides l.
本発明によれば、＠１の駆１１１ＭＩｓＦＥＴおよび第
１の負荷素子な直列ＷＩＷ！ｌシて電源にｍｓ続して成
る前段回路と、＠２の駆動ＭＩＳＦＥＴおよび嬉２の負
荷素子な直列礎続して前記電源に接続して成る後段回路
とをＸ備し、前記後段回路の第２の駆動ＭＩＳＦＥＴの
ゲートが前記前段回路における前記第１の駆動ＭＩＳＦ
ＥＴと第１の負荷素子との接続部に電気的接続して成る
ＭＩＳ型中導体集積回路において、前記後段回路の第２
の駆動ＭＩ８ＦＥＴのゲートと、前記＠２の駆動ＭＩＳ
ＦＥＴのゲートから前記前段回路の前記接続部に至る配
線と、前記前段回路の前記接続部から前記第１の負荷素
子を介して前記電源に至る経路とが、単結晶シリコン字
導体基板上の絶縁膜上に形成された半導体層によって連
続的に形成されて成ることＩｋ％黴とする。According to the invention, the driver 111MIsFET of @1 and the first load element are connected in series WIW! A front-stage circuit connected to the power supply for ms, and a rear-stage circuit comprising a drive MISFET @2 and a load element connected in series and connected to the power supply. The gate of the second drive MISFET is connected to the first drive MISFET in the preceding stage circuit.
In the MIS type medium conductor integrated circuit which is electrically connected to the connection portion between the ET and the first load element, the second
The gate of the driving MI8FET and the driving MIS of @2
The wiring from the gate of the FET to the connection part of the pre-stage circuit, and the path from the connection part of the pre-stage circuit to the power supply via the first load element are insulated on a single-crystal silicon conductor substrate. It is assumed that Ik% mold is formed continuously by a semiconductor layer formed on a film.
以下実細例を用いて本発明をａ明する。The present invention will be explained below using detailed examples.
第３図は本発明によるＭＩＳｍ字導体体肢の一実施例で
ある。同図囚は本発明が適応されるＭＩ８溜牛導体装置
の等価回路であり、Ｑ、、Ｑ、が駆動ＭＩ ５ＦＥＴ、
Ｑ、、Ｑ４が負荷ＭＩＳＦＥＴである。同図■は本発明
によるＭＩＳ―雫導体装置の上面図で、１３はＱ、のＰ
”ｌｌソース領域、１４はＱ、のｒ１ドレイン領域、１
１はＱ、のソース電極用コンタクトホール、１２はＱ、
のドレイン電極用コンタクトホール、１５はＱ、のソー
スＡ１電極配線、１６はＱ、のドレインＡＪ電働配線で
あり、１７はＱ、のＰ＋型ポリシリコンゲートおよびＱ
、のＰ＋ソース領域およびこの間の配線層を兼用するも
のである。１９はＱ、のドレイン電極用コンタクトホー
ル、１８はＱ、のＰ＋ドレイン領域と配線層な兼用し、
２０はＱ、のゲート人！電極である。同図＋ＣＩは同図
■のＸＸ′断面図な示すものであり、２２ａはＱ、のゲ
ート絶縁膜、２２ｂはフィールド絶縁膜、２４はＱ、の
ゲート直下チャンネル領域、２３はＱ、のチャンネル領
域、２１はポリシリコン層上に形成された絶縁膜である
。FIG. 3 is an embodiment of an MIS m-shaped conductor limb according to the present invention. The figure shows an equivalent circuit of an MI8 conductor device to which the present invention is applied, where Q, , Q are driving MI 5FETs,
Q, , Q4 are load MISFETs. In the same figure, ■ is a top view of the MIS-drop conductor device according to the present invention, 13 is Q, P
"ll source region, 14 is Q, r1 drain region, 1
1 is a contact hole for the source electrode of Q, 12 is a contact hole for Q,
15 is the source A1 electrode wiring of Q, 16 is the drain AJ power wiring of Q, and 17 is the P+ type polysilicon gate of Q and the contact hole for the drain electrode of Q.
, and the wiring layer therebetween. 19 is a contact hole for the drain electrode of Q, 18 is also used as a P+ drain region of Q and a wiring layer,
20 is Q, the gate person! It is an electrode. 22a is the gate insulating film of Q, 22b is the field insulating film, 24 is the channel region directly under the gate of Q, and 23 is the channel region of Q. , 21 are insulating films formed on the polysilicon layer.
さらに同図０は同図■のＹＹ’断面図であり、駆動ＭＩ
ＳＦＥＴＱ、がシリコンゲート構造であることを示して
いる。Furthermore, Figure 0 is a YY' sectional view of Figure ■, and the drive MI
This shows that SFETQ has a silicon gate structure.
尚１本発明のＭＩＳａ＆１字導体装置体肢１ｌｌ造する
Ｋは、従来のシリコンゲー）ＭＩＳ牛導体装置の一部方
法とほとんど同じであり、まずＮｌｉポリシリコンをデ
ボジシ曹ンした後、同図ｔｅｌに示すように負荷ＭＩ８
素子チャンネル拡散マスク３（ｌ使用し、Ｑまのチャン
ネル部２３に不純匍が導入されないようにした俵、拡散
法などでポリシリコンＫＰ型不純物を導入することによ
り、容易に一部することが可能である。1 The method for manufacturing the body and limbs of the MISa & 1-character conductor device of the present invention is almost the same as a part of the conventional silicon game) MIS conductor device, and after first depositing Nli polysilicon, Load MI8 as shown in
By using a device channel diffusion mask 3 (l) to prevent impurities from being introduced into the Q-channel channel portion 23, it can be easily partially removed by introducing polysilicon KP-type impurities using a diffusion method. It is.
このようにすると、負荷ＭＩ８素子ではゲート電＆によ
って誘起された移動キャリアはゲート電極上の酸化膜の
ａ面に薄く集まりチャンネル層を形成する。この薄さは
従来Ｐａ＆１層で形成したよりもかなり薄く数１００λ
であり、高い抵抗値を得ることができる。In this way, in the load MI8 element, mobile carriers induced by the gate voltage & are thinly collected on the a-plane of the oxide film on the gate electrode to form a channel layer. This thinness is considerably thinner than that formed with conventional Pa&1 layer, which is several hundred λ.
Therefore, a high resistance value can be obtained.
本発明によれば、前段回路の負荷素子と、後段回路の駆
動ＭＩ８ＦＥＴのゲートと、上記負荷素子と上記駆動Ｍ
ＩＳＦＥＴのゲートとの間の配線と、上記負荷素子と電
源との間の配線とがすべて絶縁膜上の中導体層内に連続
的に形成されるので。According to the present invention, the load element of the front-stage circuit, the gate of the drive MI8FET of the rear-stage circuit, the load element and the drive M
The wiring between the gate of the ISFET and the wiring between the load element and the power supply are all formed continuously in the middle conductor layer on the insulating film.
これら回路構成ａｍ間に心安とされるコンタクト領域を
減少させることができる。これによって。The safe contact area between these circuit structures can be reduced. by this.
集積回路の集積度を増すことができる。The degree of integration of integrated circuits can be increased.
本実施例ではシリコン基板なｎａＩｌにしたが、これに
限らすＰａｌでもよい。ただし、この場合能の導電型の
牛導体層はこれと興なる導電型の中導体層としなければ
ならない。また、ＡＪ配線層に限定されることなく、配
線層は全てポリシリコンで形成してもよい。In this embodiment, a silicon substrate, naIl, is used, but the substrate is not limited to this, and Pal may also be used. However, in this case, the conductive layer of the current conductivity type must be a medium conductive layer of the same conductivity type. Further, the wiring layer is not limited to the AJ wiring layer, and all wiring layers may be formed of polysilicon.
な示す構成図□、第３図（２）〜ａは本発明に係るＭＩ
Ｓｍｉ中導体集積回路な示し、第３図囚は、その等価回
路図、第３図（６）はその平向図、第３図１ｃＩおよび
０はその断面図をそれぞれ示す。The configuration diagram □ shown in FIG. 3 (2) to a shows the MI according to the present invention.
FIG. 3 shows an equivalent circuit diagram, FIG. 3 (6) shows a plan view thereof, and FIGS. 1cI and 1c show a cross-sectional view thereof.
１．６・・・体肢体基板、２ 、２’、 ７・・・酸化
膜、３・・・Ｐ型半導体層、４・・・ｐ” ａｔ中中休
体層５・・１１．８・・・ポリシリコン、９・・・Ｐ＋
拡散層、１０・・・ゲート電極、１３・・・ソース領域
、１４・・・ドレイン領域、１５．１６・・・電−配線
、１７，１８．２３・・・ポリシリコン層、２１・・・
絶縁膜、２２ａ・・・ゲート絶縁膜＆２２ｂ・・・フィ
ールド絶縁膜、３０・“・マスク。1.6... Body/extremity body substrate, 2, 2', 7... Oxide film, 3... P-type semiconductor layer, 4... p'' at intermediate body layer 5... 11.8.・Polysilicon, 9...P+
Diffusion layer, 10... Gate electrode, 13... Source region, 14... Drain region, 15.16... Electric wiring, 17, 18.23... Polysilicon layer, 21...
Insulating film, 22a...gate insulating film &22b...field insulating film, 30.'' mask.
２０・・・ゲー１１゜ 第 １ 図 ４ 第 ２ 図 第 ３ 図 １・ ２２、ｂ ／ フＴ７− １″７−ン （Ｄ）20...Game 11° Figure 1 4. Figure 2 Figure 3 1・ 22,b / Fu T7- 1″7-n (D)
Claims (1)
列接続して電源Ｋｌｌ続して成る前段回路と。 第２の駆動ＭＩＳＦＥＴおよび第２の負荷素子な直列接
続して前記電源に接続して成る後段回路とな具備し、前
記後段回路の第２の駆動ＭＩ８ＦＥＴのゲートが前記前
段回路における前記第１の駆動ＭＩＳＦＥＴとｗＥｌの
負荷素子との接続部に電気的接続して成るＭＩＳａｔ中
導体集積回路において、前記後段回路の第２の駆動ＭＩ
５ＦＥＴのゲートと、前記第２の駆動ＭＩＳＦＥＴの
ゲートから前記前段回路の前記接続部に至る配線と、前
記前段回路の前記＊ａ部から前記第１の負荷素子を介し
て前記電源に至る経路とが、単結晶シリコン午導体基板
上の絶縁膜上に形成された半導体層によって連続的に形
成されて成ることす特徴とするＭＩＳ蟲牛導体集積回路
。[Scope of Claims] 1. A front-stage circuit comprising a first drive MISFET and a first load element connected in series and connected to a power supply Kll. A second drive MISFET and a second load element are connected in series and connected to the power supply, the gate of the second drive MISFET of the latter circuit being connected to the first drive MISFET of the first stage circuit. In the MISat medium conductor integrated circuit which is electrically connected to the connection portion between the drive MISFET and the load element of wEl, the second drive MISFET of the latter stage circuit
a gate of the 5FET, a wiring from the gate of the second drive MISFET to the connection part of the pre-stage circuit, and a route from the *a section of the pre-stage circuit to the power supply via the first load element. 1. A MIS conductor integrated circuit characterized in that the MIS conductor integrated circuit is continuously formed by a semiconductor layer formed on an insulating film on a single-crystal silicon conductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58050403A JPS58175858A (en) | 1983-03-28 | 1983-03-28 | Mis semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58050403A JPS58175858A (en) | 1983-03-28 | 1983-03-28 | Mis semiconductor integrated circuit |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10205673A Division JPS5731306B2 (en) | 1973-09-12 | 1973-09-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58175858A true JPS58175858A (en) | 1983-10-15 |
Family
ID=12857897
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58050403A Pending JPS58175858A (en) | 1983-03-28 | 1983-03-28 | Mis semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58175858A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0166218A2 (en) * | 1984-06-28 | 1986-01-02 | International Business Machines Corporation | Silicon-on-insulator transistors |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS48102056A (en) * | 1972-04-06 | 1973-12-21 | ||
| JPS5850402A (en) * | 1981-09-21 | 1983-03-24 | Ohbayashigumi Ltd | Detecting method for position of underwater excavator and measuring ruler thereof |
-
1983
- 1983-03-28 JP JP58050403A patent/JPS58175858A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS48102056A (en) * | 1972-04-06 | 1973-12-21 | ||
| JPS5850402A (en) * | 1981-09-21 | 1983-03-24 | Ohbayashigumi Ltd | Detecting method for position of underwater excavator and measuring ruler thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0166218A2 (en) * | 1984-06-28 | 1986-01-02 | International Business Machines Corporation | Silicon-on-insulator transistors |
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