JP3738369B2 - Semiconductor integrated circuit device - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a semiconductor integrated circuit device including a MOSFET, and more particularly to a semiconductor integrated circuit device including a MOSFET in which surfaces of a source region and a drain region are formed of a silicon-metal compound (metal silicide).
[0002]
[Prior art]
3 Ri configuration diagram der representing a conventional unmodified MOSFET, and is the same as the FIG., The drain region 21, 22 _1, 22 ₂ a source region, 23 denotes a drain electrode, 23 ₁₁ drain contact, 24 _1, 24 ₂ Denotes a source electrode, 24 ₁₁ and 24 ₂₁ denote source contacts, and 25 denotes a gate electrode.
[0003]
In the conventional MOSFET shown in this figure, source regions 22 ₁ and 22 ₂ are formed on both sides of the drain region 21, a drain electrode 23 is formed in the drain region 21, and each source region 22 ₁ and 22 ₂ has Source electrodes 24 ₁ and 24 ₂ are formed, and a bifurcated gate electrode 25 is formed between the drain region 21 and the source regions 22 ₁ and 22 ₂ on both sides thereof.
[0004]
Since the surfaces of the drain region 21 and the source regions 22 ₁ , 22 ₂ of this conventional MOSFET are relatively high resistance semiconductor diffusion layers, the drain electrode 23 and the source electrodes 24 ₁ , 24 ₂ are respectively connected to the drain region 21 and the source region. It is necessary to make contact with the surfaces of 22 ₁ and 22 _{2 over} a wide area and to take a large number of drain contacts 23 ₁₁ and source contacts 24 ₁₁ and 24 ₂₁ .
[0005]
Therefore, the drain region 21 and the source regions 22 ₁ , 22 ₂ need to have a shape in which opposing sides are parallel, for example, a rectangle, so that the area of the drain region 21 and the source regions 22 ₁ , 22 ₂ is more than necessary. When this MOSFET is integrated to form a logic circuit or the like, it has become a bottleneck for high integration.
Therefore, it has been considered to reduce the area of the drain electrode 23 and the source electrodes 24 ₁ and 24 ₂ by forming a low-resistance metal silicide on the surfaces of the drain region 21 and the source regions 22 ₁ and 22 ₂ .
[0006]
Figure 4 is Ri configuration diagram der representing the conventional advanced MOSFET, and is the same as the FIG., The drain region 31, 32 _1, 32 ₂ a source region, 33 denotes a drain electrode, 33 ₁₁ drain contact, 34 _1, 34 ₂ source electrode, 34 _11, 34 ₂₁ source contact, 35 denotes a gate electrode.
[0007]
In the conventional improved MOSFET seen in FIG. 4, the source region 32 ₁ on both sides of the drain regions 31, 32 ₂ are formed, the drain electrode 33 is formed on the drain region 31, to the source regions 32 _1, 32 ₂ Source electrodes 34 ₁ and 34 ₂ are formed, and a bifurcated gate electrode 35 is formed between the drain region 31 and the source regions 32 ₁ and 32 ₂ on both sides thereof.
[0008]
In the conventional improved MOSFET shown in FIG. 4, a low resistance silicon and metal compound (metal silicide) is formed on the surfaces of the drain region 31 and the source regions 32 ₁ and 32 _2. The source electrodes 34 ₁ and 34 ₂ are in contact with the drain region 31 and the surfaces of the source regions 32 ₁ and 32 _{2 in} a small area, respectively, and a small number of drain contacts 33 ₁₁ and source contacts 34 ₁₁ and 34 ₂₁ are taken. Thus, the resistance of the extraction electrode from the drain region 31 and the source regions 32 ₁ and 32 ₂ can be sufficiently reduced.
[0009]
Therefore, in the conventional improved MOSFET shown in FIG. 4, the area required to take a small number of drain contacts 33 ₁₁ and source contacts 34 ₁₁ and 34 ₂₁ as the surface areas of the drain region 31 and the source regions 32 ₁ and 32 _2. since it is only necessary to ensure, can be compressed in the drain region 31 and source region 32 _1, 32 in the _{plane 2} opposite side is curved or bent with a non-rectangular, depending on it, the junction capacitance of the drain region In addition, the occupation area is reduced, and the degree of integration of logic circuits and the like and high-speed operation can be improved. In this conventional improved MOSFET, since the gate electrode is often bent (bent), this is hereinafter referred to as a bent gate.
[0010]
As described above, the vent gate is a technique that is extremely advantageous for high integration and high speed operation of the MOSFET . Conventionally, the low resistance metal silicide can be formed on the surfaces of the drain region and the source region. had been applied to all of the MOSFET constituting the in the internal circuit in a semiconductor integrated circuit such as a logic circuit.
[0011]
FIG. 5 is a diagram illustrating the configuration of a conventional semiconductor integrated circuit device.
In this figure, L is the first MOSFET of the logic circuit, P is a protection circuit, 41 is a drain region, 42 ₁ and 42 ₂ are source regions, 43 is a drain electrode, 43 ₁₁ is a drain contact, and 44 ₁ and 44 ₂ are sources. Electrodes, 44 ₁₁ and 44 ₂₁ are source contacts, 45 ₁ and 45 ₂ are gate electrodes, 46 is an external connection pad, 46 ₁ and 46 ₂ are drain electrodes, 47 ₁ and 47 ₂ are drain regions, and 48 ₁ and 48 ₂ are Source regions 49 ₁ and 49 ₂ are gate electrodes, and 50 ₁ and 50 ₂ are well contacts.
[0012]
This figure partially shows a part from the external connection pad 46 through the protection circuit (P) to the first-stage MOSFET (L) of the logic circuit (internal circuit) in the conventional semiconductor integrated circuit device.
[0013]
The first-stage MOSFET (L) of the logic circuit (internal circuit) in this conventional semiconductor integrated circuit device is vented in the same way as the conventional improved MOSFET shown in FIG. 4 as well as the MOSFET (not shown ) of other internal circuits . It has a gate structure. This is because the bent gate structure is more advantageous in terms of the degree of integration and the like if the difference in ESD (electrostatic discharge) breakdown voltage is not a concern.
[0014]
Further, in the protection circuit (P) against static electricity in this conventional semiconductor integrated circuit device, gate electrodes 49 ₁ and 49 ₂ are formed between the drain regions 47 ₁ and 47 ₂ and the source regions 48 ₁ and 48 ₂ , and the source A V _SS electrode is connected to the region 48 ₁ and the well contact 50 ₁ , and V _DD is connected to the source region 48 ₂ and the well contact 50 ₂ .
[0015]
Further, the drain region 47 _1, 47 ₂ is connected to the drain electrode 46 _1, 46 _2, these drain electrodes 46 _1, 46 ₂ at both ends merges, the external connection pads 46, the logic circuit (internal circuit) Are connected to the gate electrodes 45 ₁ and 45 ₂ of the first-stage MOSFET (L).
[0016]
The protection circuit (P), when under heavy static electricity from an external connection pads 46, before the charge is applied to the gate electrode 45 _1, 45 ₂ of the first-stage MOSFET in the logic circuit (internal circuit) (L) To absorb .
[0017]
[Problems to be solved by the invention]
However, in a semiconductor integrated circuit device using a MOSFET having a bent gate structure at the first stage of this conventional logic circuit, even if a protective circuit (P) is provided, electrostatic discharge (Electro Static Discharge ESD) charged to the human body or the like. ) Often breaks an active element composed of a MOSFET constituting an internal circuit.
[0018]
As a result of investigating the cause, it was found that there is a problem in using a MOSFET having a bent gate structure as all active elements constituting an internal circuit such as a logic circuit.
The reason is that the source region, the drain region, or the gate electrode is bent (curved or bent), so that defects in the semiconductor layer and the insulating film are likely to occur in the manufacturing process at the curved or bent portion, and external connection It can be considered that due to the synergistic effect that electric field concentration is likely to occur in the curved or bent portion when static electricity is applied to the pad, dielectric breakdown is likely to occur in the curved or bent portion, resulting in a decrease in ESD withstand voltage.
[0019]
An object of the present invention is to provide a semiconductor integrated circuit device having high electrostatic resistance and high integration.
[0020]
[Means for Solving the Problems]
In the semiconductor integrated circuit device according to the present invention, in a semiconductor integrated circuit including a MOSFET, all MOSFET having a gate electrode connected to the external connection pads, silicon on the surface - or curved in the source and drain regions having a metal compound The non-bent sides are formed to face each other, and the gate electrode extends substantially linearly on the boundary between the source region and the drain region, and the gate is connected to the external connection pad. All MOSFETs to which electrodes are not connected are formed in a structure in which curved or bent sides in the drain region and the source region having a silicon-metal compound on the surface face each other, and the gate electrode is in the source region And a curved or bent extension extending on the boundary between the drain region and the drain region.
[0021]
In this case, at least one surface of the source region and the drain region of the MOSFET connected to the input / output unit can be formed by low resistance metal silicide, and the low resistance electrode can be drawn.
[0022]
[Action]
In the semiconductor integrated circuit device including the MOSFET having the configuration of the present invention, the MOSFET is formed in a structure in which the source region and the drain region of the MOSFET having the gate electrode connected to the external connection pad are opposed to each other with a side that is not curved or bent, By forming the gate electrode extending substantially linearly on the boundary between the source region and the drain region , defects generated in the semiconductor layer and the insulating film in the manufacturing process can be reduced, and the external connection pad can be reduced. When static electricity is applied to the capacitor, the electric field can be dispersed, and as a result, the ESD withstand voltage can be improved.
[0023]
Note that it is not necessary to form the source region and drain region of all MOSFETs close to the external connection pad so as to face each other with the sides that are not curved or bent as described above, and the gate electrode is directly connected to the external connection pad. the only a MOSFET T which is able to improve the ESD withstand voltage by employing the structure described above.
[0024]
Further, the source region and drain region of the MOSFET whose gate electrode is not connected to the external connection pad are formed to face each other with curved or bent sides , and on the boundary between the source region and the drain region. By forming the gate electrode extending in a curved or bent manner, the areas of the source region and the drain region can be reduced. As a result, internal circuits such as logic circuits can be highly integrated.
[0026]
【Example】
Examples of the present invention will be described below.
FIG. 1 is a diagram illustrating the configuration of a semiconductor integrated circuit device according to an embodiment of the present invention.
In this figure, L is a first-stage MOSFET of a logic circuit, P is a protection circuit, 1 is a drain region, 2 ₁ and 2 ₂ are source regions, 3 is a drain electrode, 3 ₁₁ is a drain contact, 4 ₁ and 4 ₂ are sources the electrodes, 4 _11, 4 ₂₁ source contact, 5 _1, 5 ₂ gate electrode, the external connection pads 6, 6 _1, 6 ₂ drain electrode, 7 _1, 7 ₂ drain region, 8 _1, 8 ₂ Source regions, 9 ₁ and 9 ₂ are gate electrodes, and 10 ₁ and 10 ₂ are well contacts.
[0027]
This figure shows a part from the external connection pad 6 through the protection circuit (P) to the first-stage MOSFET (L) of the logic circuit (internal circuit) in the semiconductor integrated circuit device of one embodiment of the present invention. It shows.
[0028]
First stage MOSFET logic circuit (internal circuit) in the semiconductor integrated circuit device of this embodiment (L), the conventional Unfinished MOSFET the same way as shown in FIG. 3, the drain region 1 and the source region 2 _1, 2 ₂ Although it is rectangular, a low-resistance metal silicide is formed on the surface of the drain region 1 and the source regions 2 ₁ and 2 ₂ , so that the illustration is omitted, but the internal circuit to which the drain electrode 3 is connected is 4 has the same bent gate structure as the conventional improved MOSFET shown in FIG.
[0029]
In the protection circuit (P) against static electricity in the semiconductor integrated circuit device of this embodiment, gate electrodes 9 ₁ and 9 ₂ are formed between the drain regions 7 ₁ and 7 ₂ and the source regions 8 ₁ and 8 ₂ . A V _SS electrode is connected to the source region 8 ₁ and the well contact 10 ₁ , and V _DD is connected to the source region 8 ₂ and the well contact 10 ₂ .
[0030]
Further, drain electrodes 6 ₁ and 6 ₂ are connected to the drain regions 7 ₁ and 7 ₂ , and both ends of these drain electrodes 6 ₁ and 6 ₂ are joined to form an external connection pad 6 and a logic circuit (internal circuit). Are connected to the gate electrodes 5 ₁ and 5 ₂ of the first-stage MOSFET (L).
[0031]
The protection circuit (P), when under heavy static electricity from an external connection pad 6, the charge is applied to the gate electrode 5 _1, 5 ₂ of the logic circuit in the first stage of the MOSFET (internal circuit) (L) to absorb before that.
[0032]
According to the semiconductor integrated circuit device of this embodiment, formed on the structure with opposite sides having no curvature or bending piece a source region and a drain region of the MOSFET (L) having a gate electrode connected to the external connection pads, since substantially is formed with gate electrode extending linearly in the source region and the drain region sandwiched by the boundary, it is possible to reduce the defects generated in the semiconductor layer and the insulating film in the manufacturing process, also, an external The electric field when static electricity is applied to the connection pad can be dispersed, and as a result, the ESD withstand voltage can be improved.
[0033]
Further, formed in are opposed edges with a curved or bending song source and drain regions of the MOSFET which is not connected to the gate electrode to the external connection pad structure, on sandwiched boundaries in the source and drain regions Since the gate electrode extending in a curved or bent manner is formed, the areas of the source region and the drain region can be reduced, and as a result, internal circuits such as logic circuits can be highly integrated.
[0034]
In this embodiment, it has been described that low resistance silicide is formed on the surface of the source region and drain region of all MOSFETs. However, in the MOSFET connected to the input / output unit, the source region and drain region are Since it is rectangular, the electrode can be drawn out from a large-area source region and drain region with low resistance without forming silicide.
[0036]
In order to confirm the effect of this example, an electrostatic breakdown test was performed on a semiconductor integrated circuit device manufactured under the following conditions.
1. First-stage MOSFET (Nch) of logic circuit (internal circuit)
Channel length L = 0.35μm
Channel width W = 5.0μm × 2 = 10.0μm
2. Protection circuit Nch side channel length L = 0.70μm
Channel width W '= 100μm
Pch side channel length L = 0.35μm
Channel width W '= 100μm
[0037]
FIG. 2 is an explanatory view of an electrostatic breakdown test apparatus used in one embodiment of the present invention.
In this figure, 11 is a variable voltage DC power source, 12 is a stable resistor, 13 is a capacitor, 14 is a switch, 14 ₁ and 14 ₂ are contacts, and 15 and 16 are connection terminals.
[0038]
The electrostatic breakdown test device connects the ballast resistor 12 in series with the variable voltage DC power supply 11 which can vary the voltage up to 300 V, a capacitor 13 of 200pF through the first contact point 14 of _the switches 14 At both ends of the capacitor 13, a connection terminal 15 connected to the external connection pad of the semiconductor integrated circuit device under test via the second contact 14 ₂ of the switch 14 and a connection terminal 16 connected to the V _SS pad are provided. It is connected.
[0039]
The connection terminal 15 of the electrostatic breakdown test apparatus is connected to the external connection pad of the semiconductor integrated circuit device to be tested, and the connection terminal 16 is connected to the V _SS pad of the semiconductor integrated circuit device to be tested. 14 ₁ was closed and the capacitor 13 was charged by the variable voltage DC power supply 11 with regulated voltage, and then the first contact 14 ₁ of the switch 14 was opened and the second contact 14 ₂ was closed to charge the capacitor 13. Whether or not the characteristics of the semiconductor integrated circuit device under test deteriorate by simulating the state when static electricity is applied between the external connection pad and the _VSS pad of the semiconductor integrated circuit device under test by discharging the electric charge Was measured.
Note that the voltage of the variable voltage DC power source 11 increased in steps of 10V, and the test was stopped up to 300V.
[0040]
In the semiconductor integrated circuit device as in this embodiment, it is generally considered that a withstand voltage of about 300 V or more is sufficient, but in the conventional semiconductor integrated circuit device to be tested shown in FIG. 40 cases were measured, and about 3 cases had a breakdown voltage of 300 V or less (all 290 V).
However, in the semiconductor integrated circuit device under test of the embodiment of the present invention shown in FIG. 1, 40 cases were measured and all had a withstand voltage of 300 V or more.
[0041]
In the semiconductor integrated circuit device according to the above-described conventional example and the embodiment of the present invention, the example in which the gate electrode is divided into two portions and two MOSFETs are controlled by the same gate signal has been described. Needless to say, the present invention can be applied to a normal MOSFET having the same effect.
[0042]
【The invention's effect】
As described above, according to the present invention, a semiconductor integrated circuit device with high electrostatic resistance can be obtained, which greatly contributes to improving the reliability of a logic circuit device of a computer.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a configuration of a semiconductor integrated circuit device according to an embodiment of the present invention.
FIG. 2 is an explanatory diagram of an electrostatic breakdown test apparatus used in one embodiment of the present invention.
FIG. 3 is a diagram illustrating the configuration of a conventional MOSFET.
FIG. 4 is a diagram illustrating the configuration of an improved MOSFET.
FIG. 5 is a diagram illustrating a configuration of a conventional semiconductor integrated circuit device.
[Explanation of symbols]
L First-stage MOSFET of logic circuit
P protection circuit 1 drain region 2 ₁ , 2 ₂ source region 3 drain electrode 3 ₁₁ drain contact 4 ₁ , 4 ₂ source electrode 4 ₁₁ , 4 ₂₁ source contact 5 ₁ , 5 ₂ gate electrode 6 external connection pads 6 ₁ , 6 ₂ Drain electrode 7 ₁ , 7 ₂ Drain region 8 ₁ , 8 ₂ Source region 9 ₁ , 9 ₂ Gate electrode 10 ₁ , 10 ₂ Well contact 11 Variable voltage DC power source 12 Stability resistor 13 Capacitor 14 Switch 14 ₁ , 14 ₂ Contact 15 16 Connection terminal

Claims (2)

In a semiconductor integrated circuit including a MOSFET,
All of the MOSFETs whose gate electrodes are connected to the external connection pads are formed in a structure in which the source region having a silicon-metal compound on the surface and the non-curved or bent sides in the drain region face each other, and the gate electrode Extending substantially linearly on the boundary between the source region and the drain region,
All of the MOSFETs whose gate electrodes are not connected to the external connection pads are formed in a structure in which the source region having a silicon-metal compound on the surface and the curved or bent sides in the drain region face each other, and the gate A semiconductor integrated circuit device, wherein an electrode is curved or bent and extends on a boundary between the source region and the drain region. 2. The semiconductor integrated circuit device according to claim 1, wherein the at least one MOSFET whose gate electrode is connected to the external connection pad is a first-stage MOSFET of a logic circuit that has passed through a protection circuit from the external connection pad.

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