JPH05307190A - Signal input circuit and active matrix display panel - Google Patents

Abstract

PURPOSE:To provide the signal input circuit and active matrix display panel which are improved in reliability by suppressing the influence of electric components being parasitic on a signal input line and an abnormal potential leader line. CONSTITUTION:In the signal input circuit 1, a 1st abnormal potential leader line 6 between abnormal potential leader lines connecting 1st and 2nd signal input lines 3 and 4 to an input protecting circuit 2 crosses the 2nd signal input line 4 on an output end side as compared with the conductive connection position 4a between the 2nd abnormal potential lead-out line 7 and 2nd signal input line 4. Further, the 1st electric resistance value R1b from the conductive connection position 4a to the 2nd input protecting circuit 2b is set smaller than the 2nd electric resistance value R2b from the conductive connection position 4a to an output terminal 4c.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has a signal input circuit having an input protection circuit for protecting an active matrix drive circuit and the like formed on an insulating substrate from an abnormal potential generated by static electricity and the like, and the signal input circuit. The present invention relates to an active matrix liquid crystal display panel, and more particularly to a wiring connection structure between a signal input line side and an input protection circuit side.

[0002]

2. Description of the Related Art When a semiconductor integrated circuit or the like is formed on the surface side of an insulating substrate, there is no common substrate that should have the same potential, unlike when forming an integrated circuit on the surface side of the semiconductor substrate. It is necessary to provide an input protection circuit for protection from the above. For example, in an active matrix liquid crystal display panel which is a typical flat type display panel, the pixel matrix circuit for displaying the screen, its source line driving circuit and gate line driving circuit are all on the surface of an insulating transparent substrate. Since it is formed on the side, the input protection circuit shown in FIG. 6 is conventionally provided in the signal input circuit. In this figure, the input protection circuit 70 corresponding to the first and second signal input lines 71 and 72 formed in parallel on the front surface side of the insulating transparent substrate is
The second signal input line 72 is formed at a lateral position opposite to the formation position of the first signal input line 71 among the lateral positions of the second signal input line 72. This input protection circuit 70 and the first signal input line are formed. 71 is connected to the first abnormal potential lead wire 73,
The second signal input line 72 and the input protection circuit 70 are connected by a second abnormal potential lead line 74. Here, the first and second abnormal potential lead lines 73 and 74 are both
As shown in FIG. 7A, the first and second signal input lines 71 and 72 are conductively connected to intermediate positions, and the second abnormal potential lead-out line 74 and the second signal input line 72 are connected. The conductive connection position 72a of is located closer to the output end 75 (the direction of the signal indicated by the arrow D) than the conductive connection position 71a of the first abnormal potential lead-out line 73 and the first signal input line 71. .. Therefore, the first abnormal potential lead-out line 73 is not connected to the second signal input line 7
The structure intersects 2, but at this intersection 76,
Since the first abnormal potential lead-out line 73 is formed on the surface of the interlayer insulating film 77 on the upper layer side of the second signal input line 72 as shown in FIG. 7B, their insulation is secured. Has been done.

[0003]

However, in the conventional signal input circuit, the abnormal potential supplied to the first and second signal input lines 71 and 72 can be extracted toward the input protection circuit 70. However, in reality, the abnormal voltage is not sufficiently absorbed or mitigated by the input protection circuit 70, and the main circuit on the output terminal 75 side is damaged.

As a result of investigating the cause of such a problem, the inventor of the present invention has found that the cause is the influence of an electrical component parasitic on the signal input circuit. That is, when the second signal input line 72 is described as an example, the first electrical component from the conductive connection position 72a between the second signal input line 72 and the second abnormal potential lead line 74 to the input protection circuit 70. Is set as R ₁₁ , and the conductive end 72a is connected to the output end 7
When the second electric resistance up to 5 is R ₁₂ , R ₁₁ >
If it is R ₁₂ , the second signal input line 7 is
Even if an abnormal potential occurs at 2, the inrush current that branches off at the conductive connection position 72a does not flow to the protection circuit 70 side, but flows to the one having a smaller electric resistance, that is, the output end 75 side. The main circuit side is damaged by the rush current output from the output terminal 75.

In addition to these problems, in the conventional signal input circuit, the first abnormal potential lead line 73 and the second abnormal potential lead line 73
The capacitance C ₂ is formed by the interlayer insulating film 77 at the intersection 76 with the signal input line 72, and the capacitance C ₂ is larger than the capacitance parasitic on the wiring. Therefore, the second signal input line 7
The electric charge of the abnormal voltage supplied to ₂ is accumulated in the capacitor C ₂ before being absorbed by the input protection circuit 70, and a high voltage is generated between the first abnormal potential lead-out line 73 and the second signal input line 72. The voltage is applied. Here, when the voltage between the first abnormal potential lead-out line 73 and the second signal input line 72 exceeds the withstand voltage of the interlayer insulating film 77, the interlayer insulating film 77 at the intersection 76 is destroyed and the first There is also a problem that the abnormal potential lead-out line 73 and the second signal input line 72 are short-circuited.

In view of the above problems, the object of the present invention is to
By improving the layout structure of the abnormal potential lead-out line that connects the signal input line and the input protection circuit, the influence of the electrical component parasitic on the line can be suppressed and the reliability of the signal input circuit and active circuit can be improved. It is to realize a matrix display panel.

[0007]

Means for Solving the Problems In order to solve the above-mentioned problems, means taken in the present invention include a signal input line formed on the front surface side of an insulating substrate and a side position of the signal input line. , Input protection circuit that protects the circuit on the output end side of this signal input line from the abnormal potential supplied to this signal input line, and conductively connects to the signal input line, and input the abnormal potential supplied to this signal input line In a signal input circuit having an abnormal potential lead-out line drawn to the protection circuit, a first electrical resistance value from the conductive connection position between the abnormal potential lead-out line and the signal input line to the input protection circuit is calculated from the conductive connection position. This is to set it smaller than the second electrical resistance value up to the output end of the input line.

Further, the conductive connection position is output from the signal input line for the purpose of lowering the abnormal potential by utilizing the voltage drop due to the electrical resistance parasitic on the signal input line on the front side of the input protection circuit. Set to the end side, the third electrical resistance value from the input end of this signal input line to the conductive connection position is set to the second
It is preferable to set it larger than the electrical resistance value of

Further, the signal input lines are formed in parallel as the first and second signal input lines, and the side position of the second signal input line opposite to the formation position of the first signal input line. An input protection circuit is formed at a lateral position of the
In addition to the above means, for the signal input circuit in which the first and second abnormal potential lead-out lines are formed as the abnormal potential lead-out lines for conductively connecting the signal input line and the input protection circuit, For the purpose of eliminating the influence of the parasitic capacitance between the wirings at the intersections, the first and second abnormalities as the abnormal potential lead-out lines that conductively connect the first and second signal input lines and the input protection circuit, respectively. Of the potential lead wires,
The first abnormal potential lead-out line conductively connected to the first signal input line outputs the second signal input line compared to the position where the second abnormal potential lead-out line conductively connects to the second signal input line. It is preferable that it intersects with the second signal input line on the end side. The first and second signal input lines in the present invention are
It goes without saying that only two signal input lines are provided, and three or more signal input lines are provided, of which two signal input lines are the above-mentioned first and second signal input lines. In this case, the case where any of the signal input lines of the three or more signal lines and the other signal input lines have the above-mentioned first and second signal input lines is also included.

Here, the input protection circuit is formed on the front surface side of an insulating display panel transparent substrate which is an insulating substrate together with the pixel matrix circuit, source line driving circuit and gate line driving circuit, and the first and second signals are formed. The output end of the input line is conductively connected to the gate of any one of the thin film transistors formed in the source line drive circuit and the gate line line drive circuit, and is used as a signal input circuit of the active matrix display panel. be able to.

[0011]

In the signal input circuit and the active matrix display panel according to the present invention having the above-mentioned means, even if an abnormal potential is supplied to the signal input line formed on the front surface side of the insulating substrate by static electricity or the like, an abnormality occurs. Since the potential is drawn to the input protection circuit via the abnormal potential lead line,
The abnormal potential is not output from the output end. Here, the first electrical resistance value from the conductive connection position to the input protection circuit is the second electrical resistance from the conductive connection position between the abnormal potential lead-out line and the signal input line to the output end of this signal input line. Since the value is set smaller than the value, when an abnormal potential occurs on the signal input line due to static electricity, the inrush current that branches and flows at the conductive connection position flows to the side of the protection circuit with a small wiring resistance, and the output Difficult to flow to the edge side. Therefore, the input protection circuit reliably absorbs and alleviates abnormal potential (inrush current).
Since the abnormal potential (rush current) does not damage the main circuit connected to the output end side, the reliability of the signal input circuit and the active matrix display panel is improved.

Further, two or more signal input lines and two or more abnormal potential signal input lines are formed, and further, of these signal input lines, the first of the side positions of the second signal input line is formed.
If the input protection circuit is formed at a side position opposite to the formation position of the signal input line, the first abnormal potential lead-out line inevitably intersects the second signal input line. Although a parasitic capacitance is formed between the first abnormal potential lead line and the second abnormal potential lead line, the second abnormal potential lead line is conductively connected to the second signal input line. When the structure in which the output terminal side intersects with the second signal input line is adopted, when viewed from the second signal output terminal side, the first abnormal potential lead-out line and the second signal input line intersect. This means that the input protection circuit is conductively connected to the preceding stage side via the second abnormal potential lead-out line as compared with the section. Therefore, the abnormal potential supplied to the second signal input line is first absorbed by the input protection circuit,
It is sent to the output end side in a relaxed state. Therefore, even if the capacitance is formed at the intersection of the second signal input line and the first abnormal potential lead-out line, a high voltage is applied between the second signal input line and the first abnormal potential lead-out line. Does not occur. Therefore,
Since the interlayer insulating film at the intersection is not damaged, these input lines are not short-circuited, and the reliability of the signal input circuit and the active matrix display panel is further improved.

[0013]

An embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 1A is a configuration diagram showing the configuration of a signal input circuit according to the first embodiment of the present invention, and FIG. 2A is a plan view showing the arrangement of the signal input line and the abnormal potential lead-out line. Figure 2
2B is a sectional view taken along the line VV ′ of FIG.

Since the signal input circuit of this example is formed in the active matrix liquid crystal display panel, the active matrix liquid crystal display will be described with reference to FIGS. 3 and 4 before describing the configuration of the signal input circuit. The configuration of the panel will be described.

FIG. 3 is a block diagram of an active matrix liquid crystal display panel including the signal input circuit of this example, and FIG. 4 is a circuit diagram of the source line driving circuit thereof.

In the active matrix liquid crystal display panel 10 shown in FIG. 3 and FIG.
2, source line drive circuit 12 and gate line drive circuit 21
Are formed on an insulative transparent substrate 11 (insulating substrate), of which the source line driving circuit 12 has a shift register 13, a sample hold circuit 17, and video signal input lines 14, 15 and 16. On the other hand, the gate line driving circuit 21 has a shift register 20 and a buffer circuit 23 as necessary. Also, the pixel matrix 2
Reference numeral 2 denotes a plurality of source lines 26, 27, 28 ... Connected to the source line drive circuit 12, a plurality of gate lines 24, 25 ... Connected to the gate line drive circuit 21, and these gates. , Which are formed at the intersections of the lines and the source lines, and each of the pixels 32, 33 ,.
Has a thin film transistor (TFT) 29 and a liquid crystal cell 30. Further, two clock signal input lines 34 for inputting the clock signal CKA to the shift register 13 are arranged on the source line drive circuit 12 side, while the shift signal is input to the gate line drive circuit 21 side. A clock signal input line 37 for inputting a clock signal to the register 20 is arranged. Reference numerals 35 and 36 denote start signal input lines for inputting a start signal to the source line drive circuit 12 and the gate line drive circuit 21. Here, as shown in FIG. 4, the shift register 13 is
It is composed of one inverter 13a and two clocked inverters 13b and 13c.
a has a CMOS structure composed of p-type TFTs and n-type TFTs, while clocked inverters 13b and 13c
Is composed of two p-type TFTs and two n-type TFTs. Each analog switch 17a of the sample hold circuit 17 is also composed of an n-type TFT, and its buffer circuit is also an inverter circuit 17b composed of a complementary TFT.
It is composed of 17c. Reference numeral 18 denotes a positive power supply line for driving each circuit portion of the active matrix liquid crystal display panel 10, the potential of which is held at V _dd , while 19 is its negative power supply line and the potential thereof. Is held at V _ss . Here, the active matrix liquid crystal display panel 10 is in a state in which a counter substrate (not shown) faces the transparent substrate 11, and a liquid crystal cell 30 is constituted by liquid crystal sealed between them.

In the active matrix liquid crystal display panel 10 having such a structure, since each circuit portion is formed on the front surface side of the insulating transparent substrate 11, a semiconductor having an integrated circuit formed on the front surface side of the semiconductor silicon substrate. Unlike the device, there is no conductive common substrate at the same potential. For this reason,
During the manufacturing process such as the dicing process or after completion, the circuit is likely to be damaged by static electricity or the like.

Therefore, in the active matrix liquid crystal display panel 10 of this example, on the front surface side of the transparent substrate 11,
As shown in FIG. 1A, the signal input circuit 1 has an input protection circuit 2 together with the pixel matrix 22 (pixel matrix circuit), the source line drive circuit 12, the gate line drive circuit 21, and the like. Here, the signal input circuit 1 is
The source line drive circuit 12 shown in FIG. 4 is provided for any one of the gate input circuits formed of TFTs.

In FIG. 1A, the signal input circuit 1 is
From the abnormal potential supplied to the first signal input line 3 and the second signal input line 4 formed in parallel on the surface side of the transparent substrate 11 to the output ends 3c, 4c side (the signal direction side indicated by arrow A) The input protection circuit 2 for protecting the main circuit 5 (gate input circuit of the source line drive circuit 12) is provided, and this input protection circuit 2 is the first signal input of the side position of the second signal input line 4. The line 3 is formed at a lateral position opposite to the formation position of the line 3. Further, the first input protection circuit 2a of the input protection circuit 2 and the first signal input line 3 are connected by the first abnormal potential lead-out line 6, while the second input protection circuit 2b is connected.
And the second signal input line 4 are connected by a second abnormal potential lead-out line 7. Here, the first input protection circuit 2a and the second input protection circuit 2b are connected to the positive power supply line 18 of the active matrix liquid crystal display panel 10 and the first and second abnormal signal input lines 6 and 7, respectively. The source / drain is conductively connected to the p-type TFT 201 whose source / drain is conductively connected to the negative power supply line 19 of the active matrix liquid crystal display panel 10 and the first and second abnormal signal input lines 6 and 7. Type TFT 202. Also, p
The gate of the n-type TFT 201 is conductively connected to the positive power supply line 18, and the gate of the n-type TFT is conductively connected to the negative power supply line 19.

Here, the first abnormal potential lead-out line 6 and the first abnormal potential lead-out line 6
As shown in FIG. 2A, the conductive connection position 3a with the signal input line 3 of is compared with the conductive connection position 4a between the second abnormal potential lead-out line 7 and the second signal input line 4. On the side of the output end 4c of the second signal input line 4a, the first abnormal potential lead-out line 3 is located at the conductive connection position 4a between the second abnormal potential lead-out line 7 and the second signal input line 4. In comparison, the second signal input line 4
The second signal input line 4 is crossed on the output terminal 4c side. Therefore, when viewed from the side of the input end 4b of the second signal input line 4, the second input protection circuit 2b is located at the intersection 8 of the second signal input line 4 and the first abnormal potential lead-out line 6. On the other hand, it is conductively connected to the second signal input line 4 on the front side (the side of the input end 4b). The first abnormal potential lead-out line 6 has a structure intersecting with the second signal input line 4, but the first and second
Since the abnormal potential lead lines 6 and 7 are formed on the surface of the interlayer insulating film on the upper layer side of the first and second signal input lines 3 and 4, as shown in FIG. The potential lead-out line 6 and the second signal input line 4 are arranged at the intersection 8 with the interlayer insulating film 9 interposed therebetween, and their insulating properties are secured. However, due to the interlayer insulating film 9 at the intersection portion 8,
As shown in (a), the first abnormal potential lead-out line 6 and the second abnormal potential lead-out line 6
The capacitance C ₁ is in a parasitic state at the intersection 8 with the signal input line 4.

Further, in the signal input circuit 1 of this example,
As shown in the equivalent circuit of FIG. 1B, the resistance components of electric resistance R _1a , R _2a , R _3a , R _1b , R _2b , and R _3b are parasitic in each wiring. From the conductive connection positions 3a and 4a of the first and second signal input lines 3 and 4 and the first and second abnormal potential lead lines 6 and 7 to the first and second input protection circuits 2a and 2b, respectively. 1 electrical resistance values R _1a , R
_1b is from each conductive connection position 3a, 4a to each signal input line 3,
The second electrical resistance value R _2a up to the output terminals 3c, 4c of 4;
It is set smaller than R _2b . Further, each conductive connection position 3a, 4a has a first and a second output end 3c, 4c.
Of the first and second signal input lines 3 and 4 while ensuring the relationship between the first electrical resistance value R ₁ and the second electrical resistance value R ₂ described above. The third electrical resistance values R _3a , R _3b from the ends 3b, 4b to the respective conductive connection positions 3a, 4a are the first electrical resistance values R _1a , R _1b and the second electrical resistance value R _2a. , R _2b are set to be large. Here, the first and second signal input lines 3 and 4 are both made of polycrystalline silicon, while the first and second abnormal potential leading lines 6 and 7 are made of an aluminum layer. The conductive connection between the first and second signal input lines 3 and 4 and the first and second abnormal potential lead lines 6 and 7 is made through the connection hole of the interlayer insulating film. In the case where the contact resistance between them is not negligible compared with the electrical resistance of the wiring itself, the electrical resistance values R _1a , R _2a , R _3a , R _1b , R _2b , and R _3b are the contact resistances at the respective connection portions. A predetermined magnitude relationship is set as including the following.

The operation of the input protection circuit 2 in the signal input circuit 1 having such a configuration will be described with reference to FIGS. 5 (a), 5 (b) and 5 (c) by taking the operation of the second input protection circuit 2b as an example. ) Will be described.

FIG. 5A is a circuit diagram showing the configuration of the second input protection circuit 2b, and FIG. 5B is its p-type TFT 201.
Is a graph showing the relationship between the gate-source voltage V _gs and the source-drain current I _sd, and FIG. 5C is an n-type TF.
FIG. 9 is a graph showing the relationship between the gate-source voltage V _gs and the drain-source current I _{ds of} T202. In the following description, the positive power supply potential of the positive power supply line 18 is V _dd , the negative power supply potential of the negative power supply line 19 is V _ss , and the second signal input line 4 is
The input potential of which is drawn out to the second input protection circuit 2b through the second abnormal potential lead-out line 7 is V _in . The input stage of the main circuit 5 shown in FIG.
It is a gate input circuit of the source line drive circuit 12 including an inverter 5a composed of an S structure TFT.

[0025] First of all, V _ss ≦ V _in ≦ V in the case of a _dd, the potential V _gs between the gate and the source in TFT201 of the p-type 0
V, and its drain-source voltage V _ds is (V _in −V _dd ).
v and V _ds ≤0. Therefore, the p-type TFT 20
1 functions as a resistor, and a source-drain current I _sd corresponding to the input potential V _in flows along the line indicated by the solid line 41 in FIG. On the other hand, the gate-source potential V _gs in the n-type TFT 202 is 0 V, and its drain
The source-to-source voltage V _ds is (V _in −V _ss ) v, and V _ds ≧ 0.
Is. Therefore, the n-type TFT 202 also functions as a resistor, and a drain-source current I _ds corresponding to the input potential V _in is generated along the line indicated by the solid line 42 in FIG.

On the other hand, when V _dd <V _in , that is, when an abnormal potential higher than the positive power supply potential V _dd of the positive power supply line 18 is applied to the second signal input line 4, Indicates that the gate-source potential V _gs in the p-type TFT 201 is (V _dd -V _in ) v, V _gs <0 V, and the drain-source voltage V _ds is (V _dd -V _in ) v. V _ds ≦ 0. Therefore, as the input potential V _in (abnormal potential) is higher, the gate-source potential V _gs and the drain-source voltage V _ds are more greatly shifted to the negative side, and the solid line 4 in FIG.
3, the p-type TFT 201 is turned on. In this case, the n-type TFT 202 is shown in FIG.
The characteristics shown by the solid line 42 remain unchanged. Therefore, when an abnormal potential higher than the positive power supply potential V _dd of the positive power supply line 18 is applied to the second signal input line 4 by static electricity or the like, the positive power supply is passed through the p-type TFT 201. Current passes through line 18.

On the other hand, when V _in <V _ss , that is, the second
When an abnormal potential lower than the negative power supply potential V _ss of the negative power supply line 19 is applied to the signal input line 4 of the n-type TFT
The gate-source potential V _{gs at} 202 is (V _ss −V
_in ) v, V _gs > 0 V, drain-source voltage V
_ds is a (V _ss -V _in) v, is a V _ds> 0. Therefore, the lower the input potential V _in (abnormal potential), the larger the gate-source potential V _gs and the drain-source voltage V _ds are on the plus side, and the characteristic indicated by the solid line 44 in FIG. , N-type TFT 202 is turned on.
In this case, the p-type TFT 201 has a solid line 41 in FIG.
The characteristics shown in are retained. Therefore, when an abnormal potential lower than the negative power supply potential V _ss of the negative power supply line 19 is supplied to the second signal input line 4, a current is supplied to the negative power supply line 19 via the n-type TFT 202. Passes through.

In this way, the main circuit 5 is protected by the second input protection circuit 2b from an abnormal potential caused by static electricity or the like.

Here, the first electrical resistance value R _1b from the conductive connection position 4a between the second signal input line 4 and the second abnormal potential lead-out line 7 to the second input protection circuit 2b is 2 is set smaller than the second electrical resistance value R _2b from the conductive connection position 4a between the abnormal potential lead-out line 4a and the second signal input line 7 to the output end 4c of the second signal input line 4. Therefore, when an abnormal potential is generated in the second signal input line 7 due to static electricity or the like, a rush current that branches and flows at the conductive connection position 4a flows to the side of the input protection circuit 2b having a small wiring resistance. Difficult to flow to the output end 4c side. Further, the conductive connection position 4a is arranged on the side of the output end 4a of the second signal input line 4, and the third end from the input end 4b to the conductive connection position 4a.
Has an electric resistance value R ₃ larger than both the first electric resistance value R ₁ and the second electric resistance value R ₂ without extending the length of the signal input line 4, Moreover, since it is set to the maximum size, the abnormal potential generated in the second signal input line 4 is transmitted from the input end 4b to the conductive connection position 4
Since it is drawn out to the input protection circuit 2b in a state where it is relaxed by the third electrical resistance R _3b up to a, an excessive rush current will not damage the side of the input protection circuit 2b or the like. The same applies to the first signal input line 3 side.

Further, since the signal input line and the abnormal potential signal input line are formed in two columns, the first abnormal potential lead-out line 6 inevitably intersects with the second signal input line 4,
Although the capacitance C ₁ is parasitic on this crossing portion 8, the first abnormal potential lead-out line 6 is connected to the second abnormal potential lead-out line 7 and the second abnormal potential lead-out line 7.
Since the second signal input line 4 is crossed with the second signal input line 4 on the side of the output end 4c of the second signal input line 4 compared to the electric connection position 4a with the signal input line 4 of FIG. Looking at the first
The second input protection circuit 2b is electrically conductively connected via the second abnormal potential lead-out line 7 to the front side of the intersection 8 between the abnormal potential lead-out line 6 and the second signal input line 4. .. Therefore,
The abnormal potential generated in the second signal input line 4 is first sent to the output terminal 4c side while being absorbed and relaxed in the second input protection circuit 2b. Therefore, the capacitance C ₁ is formed at the intersection 8 of the second signal input line 4 and the first abnormal potential lead-out line 6.
However, since a high voltage is not generated between them, no short circuit occurs between the wirings.

As described above, in the active matrix liquid crystal display panel 10 including the signal input circuit 1 of this example, the main circuit 5 is protected by the input protection circuit 2 from an abnormal potential caused by static electricity or the like. Here, the rush current flows to the side of the input protection circuit 2 having a small wiring resistance, and the input protection circuit 2 reliably absorbs and alleviates the abnormal potential (rush current). Therefore, due to the abnormal potential (rush current), the output terminal 3
Since the main circuit 5 connected to the c and 4c sides is not damaged, the reliability of the signal input circuit 1 and the active matrix display panel 10 is improved. Also, the conductive connection position 3
a, 4a are arranged on the side of the output ends 3c, 4c and do not extend the first and second signal input lines 3 and 4 and the third from the input ends 3b, 4b to the conductive connection positions 3a, 4a. Since the electrical resistance values R _3a and R _{3b of} are set to the maximum values, the inrush current is relaxed by this electrical resistance,
It is also possible to prevent damage to the input protection circuit 2 side due to the inrush current.

Furthermore, the first abnormal potential lead-out line 6 outputs the second signal input line 2 in comparison with the conductive connection position 4a of the second abnormal potential lead-out line 7 to the second signal input line 4. When crossing the second signal input line 4 on the end side and seen from the input end 4b side of the second signal input line 4, the second input protection circuit 2b is
It is on the upstream side of the capacitance C ₁ parasitic on the intersection 8 between the second signal input line 4 and the first abnormal potential lead-out line 6. For this reason,
The abnormal potential reaches the intersection 4a between the second signal input line 4 and the first abnormal signal input line 6 while being reliably absorbed and relaxed by the second input protection circuit 2b. Therefore, even if the capacitance C ₁ is formed at the crossing portion 8, since the voltage generated between the second signal input line 4 and the first abnormal potential lead-out line 6 is low, the interlayer insulating film at the crossing portion 8 is formed. 9 is not damaged. Therefore, since the second signal input line 4 and the first abnormal potential lead-out line 6 are not short-circuited due to the abnormal voltage, the reliability of the signal input circuit 1 and the active matrix liquid crystal display panel 10 including the signal input circuit 1 is improved. improves.

In this example, the signal input circuit having the signal input lines in two columns has been described. However, the present invention is not limited to this, and the parasitic capacitance can be applied to a signal input circuit having signal input lines in three or more columns. It is possible to adopt a structure in which the influence of is suppressed. That is, regarding two columns of the three or more column signal input lines, the signal input line on the input protection circuit side is used as the second signal input line, and the signal input line on the other side is used as the first signal input line. The first and second abnormal potential lead lines are arranged in the above-described configuration. Further, the configurations of the input protection circuit side and the main circuit side are not limited.

[0034]

As described above, in the signal input circuit according to the present invention and the active matrix display panel including the signal input circuit, the first part from the conductive connection position of the signal input line and the abnormal potential lead-out line to the input protection circuit is provided. The electrical resistance value is
It is characterized in that it is set smaller than the second electric resistance value from the conductive connection position to the output end of the signal input line. Therefore, according to the present invention, the inrush current flows to the side of the input protection circuit having a small wiring resistance and is reliably absorbed,
Since this is alleviated, the main circuit connected to the output end side is not damaged by the abnormal potential, and the reliability of the signal input circuit and the active matrix display panel is improved.

Further, when the conductive connection position is arranged on the output end side of the signal input line and the third electric resistance value from the input end of the signal input line to the conductive connection position is set to the maximum value, Since the rush current can be alleviated by the voltage drop due to this electric resistance, the input protection circuit side can be protected without extending the signal input line.

Further, two or more signal input lines and two or more abnormal potential signal input lines are formed, respectively, and one of the lateral positions of the second signal input line is opposite to the formation position of the first signal input line. Even if the input protection circuit is formed at the position, the first abnormal potential lead-out line is compared to the conductive connection position between the second abnormal potential lead-out line and the second signal input line, When the second signal input line is crossed on the output end side, the input protection circuit is provided on the front side as compared with the crossing portion between the first abnormal potential lead-out line and the second signal input line. Even if an abnormal potential is supplied to the second signal input line due to static electricity or the like, the abnormal potential reaches the intersection while being absorbed and relaxed by the input protection circuit. Therefore, even if the capacitance is formed at the intersection, the voltage generated between the second signal input line and the first abnormal potential lead-out line is low, and the interlayer insulating film at the intersection is not damaged. Therefore, there is an effect that the short circuit between the wirings does not occur at the crossing portion, and the reliability of the input protection circuit and the active matrix display panel including the input protection circuit is improved.

[Brief description of drawings]

1A is a configuration diagram showing a configuration of an input protection circuit according to a first embodiment of the present invention, and FIG. 1B is an equivalent circuit diagram thereof.

2A is a plan view showing the arrangement of a signal input line of the input protection circuit shown in FIG. 1 and an abnormal potential lead-out line for the protection circuit, and FIG. 2B is a V-V 'line of FIG. 2A. FIG.

FIG. 3 is a block diagram showing a configuration of an active matrix liquid crystal display panel including the input protection circuit shown in FIG.

4 is a circuit diagram showing a configuration of a source line driving circuit of the active matrix liquid crystal display panel shown in FIG.

5A is a circuit diagram showing a configuration of the signal input circuit shown in FIG. 1, and FIG. 5B is a relationship between a gate-source voltage V _gs and a source-drain current I _sd of the p-type TFT. FIG. 3C is a graph showing the relationship between the gate-source voltage V _gs and the drain-source current I _ds of the n-type TFT.

FIG. 6 is a configuration diagram showing a configuration of a conventional signal input circuit.

7A is a plan view showing the arrangement of a signal input line and an abnormal potential lead-out line for the input protection circuit in the signal input circuit shown in FIG. 6, and FIG. 7B is a VI-VI ′ line in FIG. 7A. It is sectional drawing in a line.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Signal input circuit 2, 70 ... Input protection circuit 2a ... 1st input protection circuit 2b ... 2nd input protection circuit 3, 71 ... 1st signal input line 3a, 4a ... Conductive connection part 3b, 4b ... Input end 3c, 4c ... Output end 4, 72 ... Second signal input line 5 ... Main circuit 6, 74 ... First Abnormal potential lead-out line 7,75 ... Second abnormal potential lead-out line 8,76 ... Intersection 9,77 ... Interlayer insulating film 10 ... Active matrix liquid crystal display panel 11 ... Transparent substrate 12・ ・ ・ Source line drive circuit 13, 20 ・ ・ ・ Shift register 17 ・ ・ ・ Sample hold circuit 18 ・ ・ ・ Positive side power supply line 19 ・ ・ ・ Negative side power supply line 21 ・ ・ ・ Gate line drive circuit 22 ・ ・ ・Pixel matrix 30 ... Liquid crystal cell 34 ... Clock signal input line 201 ... p-type TFT (p-type thin film transistor) 202 ... n-type TFT (n-type thin film transistor)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 29/784

Claims (4)

[Claims] 1. A signal input line formed on the front surface side of an insulating substrate and an output terminal side of this signal input line from an abnormal potential supplied to the signal input line formed at a lateral position of the signal input line. An abnormal potential lead-out line that is conductively connected to the signal input line and draws out the abnormal potential supplied to the signal input line to the input protection circuit. The first electrical resistance value from the conductive connection position between the line and the signal input line to the input protection circuit is higher than the second electrical resistance value from the conductive connection position to the output end of the signal input line. And a small signal input circuit. 2. The conductive connection position according to claim 1, wherein the conductive connection position is arranged on the output end side of the signal input line, and the third electrical resistance value from the input end of the signal input line to the conductive connection position is The signal input circuit is set to be larger than the second electrical resistance value. 3. The input protection circuit according to claim 1, wherein the signal input line is formed as first and second signal input lines arranged in parallel on the front surface side of the insulating substrate. The circuit is formed at a lateral position of the lateral positions of the second signal input line opposite to the formation position of the first signal input line, and the circuit is formed at the lateral position of the first and second signal input lines. Of the first and second abnormal potential lead-out lines as the abnormal potential lead-out lines that conductively connect to the input protection circuit, respectively, a first conductively connect to the first signal input line.
Is connected to the second signal input line at the output end side of the second signal input line as compared with the position where the second abnormal potential lead line is conductively connected to the second signal input line. A signal input circuit characterized by intersecting a line. 4. A pixel matrix circuit, a source line drive circuit, and a signal input circuit defined in any one of claims 1 to 4 on the front surface side of an insulating display panel transparent substrate which is the insulating substrate. An active matrix display panel formed together with a gate line drive circuit, wherein the output terminals of the first and second signal input lines are formed in the source line drive circuit and the gate line line drive circuit, respectively. An active matrix display panel, which is conductively connected to the gate of one of the thin film transistors.