JPH05307165A - Active matrix display panel - Google Patents

Abstract

PURPOSE:To provide the active matrix display panel which can be improved in display characteristics and reliability by making an electric component, which is parasitic on a video signal line, equivalent. CONSTITUTION:On the source line driving circuit side of the active matrix liquid crystal display panel, source-side wiring layers Sa1 and Sa2 crossing video signal lines V1, V2, and V3 are made nearly equal in wiring width at specific parts to make the parasitic capacities of the paths of the video signals nearly equal, and, an extension part S11 and a narrow part S22 (electric resistance correction part) having the wiring width are provided according to the wiring lengths of the source-side wiring layers Sa1, SBa2, and Sa3 and electric resistances which are parasitic on them are made nearly equal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix panel such as a liquid crystal display panel, and more particularly to a wiring structure around a video signal line thereof.

[0002]

2. Description of the Related Art Among flat type display panels that display information by utilizing the alignment state of liquid crystal, in an active matrix type liquid crystal display panel, as shown in a block diagram of FIG. A pixel matrix 22, a source line driving circuit 12, and a gate line driving circuit 21 are formed on the side. The source line drive circuit 12 has a shift register unit 13, switch circuits T ₁ , T ₂ , T ₃ ... Composed of TFTs (thin film transistors) and video signal lines V ₁ , V ₂ , V ₃ and shifts. Register section 1
From the side of 3 to each of the switch circuits T ₁ , T ₂ , T _3, ..., The bit signal (driving signal) output from the shift register unit 13 is driven by the driving signal lines G ₁ , G ₂ , G _3.・ ・
It is possible to input via. Therefore, when the bit signal is input through the driving signal lines _{G 1, G 2, G 3} ··· in the switch circuits _{T 1, T 2, T 3} ···, the switch circuits T _1, T ₂ , T _3, ... Are switched from the high impedance state to the low impedance state. By this switching, the video signals supplied to the video signal lines V ₁ , V ₂ , V ₃ are source lines X ₁ , X ₂ , X ₃ ...
In the pixels P ₁ , P _2, ..., The video signal changes the alignment state of the liquid crystal of the liquid crystal cell 30 to display the screen.

In the active matrix liquid crystal display panel having such a structure, since the source line driving circuit 12 is arranged between the pixel matrix 22 and the outer peripheral edge of the transparent substrate 11, the video signal lines V ₁ and V _{1 are provided} . ₂ , V ₃ and
The drive signal lines G ₁ , G ₂ , G _3, ... And the source side wiring layers S ₁ , S ₂ inevitably intersect with each other as shown in FIG. That is, the source side interconnect layer S _b1 (S ₁₎ conductively connected to the video signal lines V ₁ was intersects the video signal line V _2, V _3, the source side interconnect layer is electrically connected to the video signal lines V ₁ S _b2 ( S ₂ ) intersects the video signal line V ₃ . However, the source side wiring layer S _b3 (S ₃ ) that is conductively connected to the video signal line V ₃ does not depend on which video signal line V ₁ ,
Neither V ₂ nor V ₃ intersect. Here, since the switch circuits T ₁ , T ₂ , T ₃ are collectively formed at the lateral positions of the video signal lines V ₁ , V ₂ , V ₃ , the source side wiring layers S _b1 , S _b2 , S are formed. Video signal lines V ₁ , V ₂ , V in _b3
3 switching circuit from the conductive connection position between the T _1, T _2, T ₃
And the length dimension up to the conductive connection position is different. If the electric resistances during this period are different, the pixels P ₁ and P corresponding to the video signal lines V ₁ , V ₂ and V ₃ respectively.
The display state in ₂ ... tends to vary.
Therefore, in accordance with the wiring length of the source side interconnect layer _{S b1, S b2, S b3} , by changing their width dimension, one of the source side interconnect layer S _b1, also in S _b2, S _b3, the The electrical resistance is set to be equal. That is, since the wiring length is long in the order of the source side wiring layers S _b1 , S _b2 , S _b3 ,
The wiring width is set wider in the order of the source-side wiring layers S _b1 , S _b2 , and S _b3 .

[0004]

Here, the video signal lines V ₁ , V ₂ , V ₃ and the source side wiring layers S _b1 , S _b2 and the driving signal lines G ₁ , G ₂ , G ₃ ... 6, the source side wiring layers S _b1 , S _b2 and the driving signal lines G ₁ , G ₂ , G ₃ ... Are formed on the lower layer side and the video signal line V is formed. ₁ , V ₂ and V ₃ are formed on the upper layer side, and the interlayer insulating film 14 exists between them.
Therefore, there is a parasitic capacitance between the wiring layers at the intersection due to the interlayer insulating film 14. Here, the driving signal lines G ₁ and G
_Since the widths of ₂ and G ₃ are equal to each other, the parasitic capacitances at the intersections of the driving signal lines G ₁ , G ₂ and G ₃ and the video signal lines V ₁ , V ₂ and V ₃ are shown in FIG. As described above, both are equivalent in Ca. However, in the conventional active matrix liquid crystal display panel, since the wiring widths are set wider in order on the source side wiring layers S _b1 , S _b2 , S _b3 , the source side wiring layer S _b1 and the video signal line V ₂ , Let Cb _{21 be} the magnitude of the parasitic capacitance at the intersection with V _3, and let Cb _{22 be} the magnitude of the parasitic capacitance at the intersection of the video signal line V ₂ and the source side wiring layer S _b3 . Cb ₂₁ > Cb ₂₂ is there.
Moreover, the parasitic state of the capacitance for each wiring is different.
Therefore, the capacitance of (3Ca + 2Cb ₂₁ ) is parasitic on the first path formed by the video signal line V ₁ and the source side wiring layer S _b1, and the video signal line V ₂ and the source side wiring layer S _b2 are formed. the second path parasitic capacitance of _{(3Ca + Cb 21 + Cb 22} ), the third path constituting the video signal line V ₃ and the source-side wiring layer S _b3 and parasitism _{(3Ca + Cb 21 + Cb 22} ) There is. Therefore, the first path formed by the video signal line V ₁ and the source-side wiring layer S _b1 has a larger parasitic capacitance than the other paths. Therefore, in the conventional active matrix liquid crystal display panel,
The delay of the video signal transmitted through the first path constituted by the video signal line V ₁ and the source side wiring layer S _b1 is larger than the delays in the other paths, and the pixel P corresponding to these paths is
Such as display unevenness of ₁ to 3 every other occurs. Further, since the parasitic capacitance on the first path formed by the video signal line V ₁ and the source-side wiring layer S _b1 is large, if an abnormal potential is supplied to any of the wires due to static electricity or the like, the first path There is also a problem in that the rush current is concentrated on the area V and the video signal line V ₁ is apt to be defective.

In view of the above problems, the object of the present invention is to
An object of the present invention is to realize an active matrix display panel capable of improving display characteristics and reliability by optimizing the structure of a wiring layer intersecting with a video signal line to equalize electrical components parasitic on the video signal line and the wiring.

[0006]

Means for Solving the Problems In order to solve the above-mentioned problems, the means taken in the present invention is a source line driving circuit side formed between a pixel matrix forming region on the same substrate and an outer peripheral edge of the substrate. In the outer peripheral side of the pixel matrix formation region, the pixels are formed in the lateral direction and are arranged in parallel from the shift register portion formation region side of the source line driving circuit toward the pixel matrix formation region in parallel (where n
Is an integer of 3 or more. ) Columns of video signal lines, each of these video signal lines is conductively connected through an interlayer insulating film, and n columns of source-side wiring layers extending from there to the pixel matrix formation region side, and each of these source-side wiring layers And a state in which the source line wiring layer and the source line are conductively connected based on a driving signal output from the shift register unit side, which is interposed between each source line corresponding to each of the source side wiring layers. Switched driving signals by n switch parts whose operation is switched to a non-conductive connection state and a video signal line which is formed from the shift register part side toward the switch part and intersects the video signal line through an interlayer insulating film. For an active matrix display panel having n columns of driving signal lines to be input for each set, the overlapping area of the wiring in each intersection region of these driving signal lines and video signal lines is set. Shift also equivalent,
The overlapping areas of the wirings in each crossing region of the source side wiring layer and the video signal line are made equal, and the source side wiring layer has the conductive connection position from the conductive connection position with the video signal line to the switch part. That is, the width dimension is adjusted in accordance with the wiring length between the two, and an electric resistance correction unit is provided to make the electric resistance between the source side wiring layers equal to each other. That is, from the conductive connection position with the video signal line in each source side wiring layer to the conductive connection position with the switch part while making the overlapping area of the wiring in each intersection region of the source side wiring layer and the video signal line equal. For the purpose of equalizing the electrical resistance, the electrical resistance is adjusted by an electrical resistance correction portion such as an extension portion or a narrow portion in the wiring width direction formed in the source side wiring layer.

[0007]

In the active matrix display panel according to the present invention having the above-mentioned means, for the n columns of video signal lines arranged in parallel on the outer peripheral side of the pixel matrix forming region, the pixel matrix forming region side is formed from these video signal lines. Since the n-row source side wiring layers toward the switch section intersect with the n-row drive signal lines for inputting the drive signal for each switch section, capacitance is parasitic at the intersections. Here, the magnitudes of the parasitic capacitances at the intersections of the video signal lines and the driving signal lines are equal, but the parasitic capacitances at the intersections of the video signal lines and the source-side wiring layers are equalized. If the wiring widths of the side wiring layers are made equal, the electrical resistance parasitic on the source side wiring layer will be different for each source side wiring layer. Therefore, in the present invention, by making the wiring width of the source side wiring layer in each intersection region of the source side wiring layer and the video signal line equal at any intersection, the video signal line and the source side wiring layer are While equalizing the parasitic capacitance at the intersection, the electrical resistance is adjusted by an electrical resistance correction portion such as an extension portion or a narrow portion in the wiring width direction formed in the source side wiring layer. Therefore, the capacitance and resistance parasitic on the path of the video signal formed by the video signal line and the source side wiring layer can be made equal in any path. Therefore, since there is no difference in the delay of the video signal in each path,
The display characteristics are improved. Further, even if an abnormal potential is supplied to the wiring due to static electricity or the like, the rush current does not concentrate on a specific path, so that the reliability is improved.

[0008]

An embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a schematic plan view of the periphery of a video signal line formation region on the source line drive circuit side of an active matrix liquid crystal display panel according to an embodiment of the present invention. Here, the overall configuration of the active matrix liquid crystal display panel of this example is almost the same as the block diagram shown in FIG.
The overall configuration will be described with reference to FIG. 4 as in the conventional example. Further, since the active matrix liquid crystal display panel of the present example and the conventional active matrix liquid crystal display panel have basically the same configuration, corresponding parts will be denoted by the same reference numerals.

First, before explaining the structure around the formation region of the video signal line on the source line drive circuit side, which is a characteristic point of the active matrix liquid crystal display panel of this example, FIG.
The entire configuration of the active matrix liquid crystal display panel of this example will be described with reference to FIG. In this figure,
A pixel matrix 22, a source line drive circuit 12 and a gate line drive circuit 21 are formed on the front surface side of the transparent substrate 11 to achieve downsizing, high definition, and cost reduction of the display device. Here, the source line drive circuit 12 has a shift register unit 13, switch circuits T ₁ , T ₂ , T ₃ ... Composed of TFTs (thin film transistors), and video signal lines V ₁ , V ₂ , V ₃ . Shift register unit 1
From the side of 3 to each of the switch circuits T ₁ , T ₂ , T _3, ..., The bit signal (driving signal) output from the shift register unit 13 is driven by the driving signal lines G ₁ , G ₂ , G _3.・ ・
It is possible to input via. Here, the clock signal line 34 is added to the shift register unit 13 of the source line drive circuit 12.
A clock signal is input via the switch circuit, and the bit signals output from the clock signal are transmitted via the drive signal lines G ₁ , G ₂ , G ₃ ... Each switch circuit T ₁ , T ₂ , T ₃ ... Is input to each of the switch circuits T ₁ , T ₂ , T _3, ... Switches from the high impedance state to the low impedance state. By this switching, the video signal lines V ₁ , V ₂ ,
The video signal supplied to V ₃ is the source side wiring layers S ₁ , S ₂ , S ₃ ... And each switch circuit T ₁ , T 3.
₂ , T _3, ..., Source lines X ₁ , X ₂ , X ₃ ...
.. and a plurality of pixels P ₁ , P ₂ ... Formed at the intersections of the source lines X ₁ , X ₂ , X ₃ ... And the gate lines Y ₁ , Y ₂ , Y ₃ ... Is output to. In these pixels P ₁ , P _2, ... A thin film transistor (TFT) 29 is driven on the basis of the gate signal, and the video signal changes the alignment state of the liquid crystal of the liquid crystal cell 30 in accordance with the operating state. Change and display the screen. The gate line drive circuit 21 has a shift register section 20 and a buffer circuit 23 as necessary, and a clock signal line 37 is provided therein.
Therefore, the clock signal can be input to the shift register unit 20. Further, 35 and 38 are the source line drive circuit 12
And a start signal line for inputting a start signal to the gate line drive circuit 21.

In the active matrix liquid crystal display panel having such a structure, since the source line driving circuit 12 is arranged between the pixel matrix 22 and the outer peripheral edge of the transparent substrate 11, the video signal lines V ₁ and V ₁ thereof are arranged. ₂ , V ₃ and
Driving signal lines _{G 1, G 2, G 3} ··· and source-side wiring layer S ₁ to conductively connected to the video signal line V _1, V _2, S ₂
And inevitably intersect with each other, as shown in FIG. That is, the video signal lines V ₁ , V ₂ , and V ₃ are formed in the side direction of the pixel matrix 22, and are arranged in parallel from the shift register unit 13 side toward the pixel matrix 22 in sequence. source-side wiring layer S _a1 conductively connected to line V ₁ (S ₁₎ intersects the video signal line V _2, V _3, the source side interconnect layer is electrically connected to the video signal lines V ₁ S _a2 (S ₂₎ is It intersects with the video signal line V ₃ . However, the source side interconnect layer is electrically connected to the video signal line V ₃ S _a3 (S ₃₎ is one of the video signal lines V _1,
Neither V ₂ nor V ₃ intersect. Here, the structure of the intersection of the video signal lines V ₁ , V ₂ , V ₃ and the source side wiring layers S _a1 , S _a2 and the driving signal lines G ₁ , G ₂ , G ₃ ... 2, the source-side wiring layers S _a1 , S _a2 and the drive signal lines G ₁ , G ₂ , G ₃ ... Video signal lines V ₁ , V ₂ , V formed of crystalline silicon
₃ is formed of an aluminum layer on the upper layer side, and the interlayer insulating film 14 exists between them. For this reason, a parasitic capacitance exists between the wiring layers at the intersections due to the interlayer insulating film 14, but since the driving signal lines G ₁ , G ₂ , and G _{3 have} the same width, the wiring shown in FIG. As shown in the equivalent circuit,
Driving signal lines G ₁ , G ₂ , G ₃ and video signal lines V ₁ , V
The parasitic capacitances at ₂ and V ₃ and at the intersection are the same for Ca.

Here, the magnitude of the parasitic capacitance at the intersection of the source side wiring layer S _a1 and the video signal lines V ₂ and V ₃ ,
If the magnitude of the parasitic capacitance at the intersection of the video signal line V ₂ and the source side wiring layer S _a3 is different, it is parasitic on the first path formed by the video signal line V ₁ and the source side wiring layer S _a1. Of the capacitance, the amount of capacitance parasitic on the second path formed by the video signal line V ₂ and the source side wiring layer S _a2, and the size of the video signal line V ₃ and the source side wiring layer S _a3. The magnitudes of the parasitic capacitances on the third path are different, the video signals transmitted through the respective paths are different in delay, and display irregularity of every three lines occurs on the screen. In addition, when an abnormal potential occurs, the rush current concentrates on a specific path having a large parasitic capacitance. On the other hand, the switch circuit T ₁ ,
Since T ₂ , T _3, ... Are collectively formed at the lateral positions of the video signal lines V ₁ , V ₂ , V ₃ , the video signal lines in the source side wiring layers S _a1 , S _a2 , S _a3 V ₁ , V ₂ , V
₃ switching circuit from the conductive connection position between the T _1, T _2, T ₃
The length dimension up to the conductive connection position with ... differs. Here, if the electrical resistance between them is different, the pixel P corresponding to each video signal line V ₁ , V ₂ , V ₃
The display states of ₁ , P _2, ... Are likely to vary.

Therefore, in the active matrix liquid crystal display panel of this embodiment, as shown in FIG. 1, the source side wiring layer S _{a1 is used for} the purpose of equalizing both the parasitic capacitance and the resistance in each path between the paths. , S _a2 , and the video signal line V
_{While making} the overlapping areas of the wirings in the respective intersecting regions with ₁ , V ₂ and V ₃ equal, the source side wiring layers S _a1 ,
The switch circuits T ₁ , T ₂ , T ₃ ... Are connected to S _a2 , S _a3 from their conductive connection positions with the video signal lines V ₁ , V ₂ , V _3.
An expanded portion in which the width dimension is adjusted in accordance with the length dimension up to the conductive connection position with and the electric resistance therebetween is made equal in each source side wiring layer S _a1 , S _a2 , S _a3. S ₁₁ and a narrow portion S ₂₂ (electrical resistance correction portion) are formed. That is, in the active matrix liquid crystal display panel of this example, each of the source side wiring layers S _a1 , S _a2 , S _a3 has a wiring width L ₁ , a wide extension S _11, and a wiring width L ₂ . is composed of a narrow narrow portion S _22, the source side interconnect layer S _a1, S
_a2 are both intersects the video signal line V _2, V ₃ at the narrow portion S _11. For this reason, the overlapping areas of the wirings at any intersections are the same. Therefore, FIG.
As shown in, the parasitic capacitance at the intersection of the source side wiring layer S _a1 and the video signal lines V ₂ and V ₃ and the parasitic capacitance at the intersection of the video signal line V ₂ and the source side wiring layer S _a3 are , And its size can be represented by Cb. As described above, the driving signal line G ₁ ,
Since the widths of G ₂ and G ₃ are constant, the driving signal lines G ₁ ,
The magnitudes of the parasitic capacitances at the intersections between G ₂ and G ₃ and the video signal lines V ₁ , V ₂ and V ₃ are all represented by Ca.
As shown in this figure, the parasitic capacitance C
Although a and Cb are parasitic, the sum of the parasitic capacitances in the first path formed by the video signal line V ₁ and the source side wiring layer S _a1 is (3Ca + 2Cb), and the video signal line V ₂ and the source side wiring are The total parasitic capacitance of the second path formed by the layer S _a2 is (3Ca + 2Cb), and the total parasitic capacitance of the third path formed by the video signal line V ₃ and the source side wiring layer S _a3 is ( 3Ca + 2Cb), and the parasitic capacitance of the same size is parasitic in any of the paths. In addition,
The equivalent structure of the above parasitic capacitance is not limited to the source side wiring layers S _a1 , S _a2 , S _a3 , but any source side wiring layers S _a1 , S _a2 formed in the active matrix liquid crystal display panel of this example. It is also used in S _a3 ....

Further, in the active matrix liquid crystal display panel of this example, the switch circuits T ₁ , T ₂ , T ₃
Are collectively formed at the lateral positions of the video signal lines V ₁ , V ₂ and V ₃ , so that the source side wiring layers S _a1 , S _a2 and S _{a3 are formed.}
The lengths from the conductive connection positions with the video signal lines V ₁ , V ₂ , V ₃ to the conductive connection positions with the switch circuits T ₁ , T ₂ , T ₃ ... The electric resistance is adjusted by the expanded portion S ₁₁ and the narrowed portion S ₂₂ formed in each of the source side wiring layers S _a1 , S _a2 , S _a3 .
That is, in the source-side wiring layer S _a1 having a long wiring length from the conductive connection position with the video signal line V ₁ to the conductive connection position with the switch circuit T ₁ , the proportion occupied by the expanded portion S ₁₁ is set to be large. ing. On the other hand, in the source side wiring layer S _a3 having a short wiring length from the conductive connection position with the video signal line V ₃ to the conductive connection position with the switch circuit T ₃ , the ratio of the narrow portion S ₂₂ occupies. It is set large. Here, since the source side wiring layers S _a1 , S _a2 , S _a3 are formed of impurity-doped polycrystalline silicon, the video signal lines V ₁ , V formed of an aluminum layer are used.
_2, since the specific resistance compared to V ₃ is large, by adjusting the resistance of the source side interconnect layer _{S a1, S a2, S a3} , video signal lines V
_This means that the electrical resistance of the video signal path constituted by ₁ , V ₂ , V ₃ and the source side wiring layers S _a1 , S _a2 , S _a3 is adjusted. Therefore, as shown in the equivalent circuit of FIG. 3B, in any of the source side wiring layers S _a1 , S _a2 , S _a3 , conductive connection positions with the video signal lines V ₁ , V ₂ , V ₃ are formed. The ratio occupied by the expanded portion S ₁₁ and the narrowed portion S ₂₂ is set in accordance with the wiring length from the switch circuit T ₁ T ₁ , T ₂ , T ₃ to the conductive connection position and the electrical resistance between them is set. The sizes are all the same for R. Regarding the equivalent structure of the above parasitic resistance, the source side wiring layer S _a1 ,
Not only S _a2 and S _a3, but also any source side wiring layer S _a1 formed in the active matrix liquid crystal display panel of this example,
It is also used in S _a2 , S _a3 ....

As described above, in the active matrix liquid crystal display panel according to this example, the video signal lines V ₁ ,
The wiring widths of the predetermined portions of the source side wiring layers S _a1 and S _a2 intersecting V ₂ and V ₃ are set equal at any intersection,
Since the parasitic capacitances in the paths of the video signals are made equal, there is no difference in the delay of the video signals in the paths, so that the display characteristics are improved. Further, even if an abnormal potential is supplied to the wiring due to static electricity or the like, the rush current does not concentrate on a specific path, so that the reliability is improved.

Further, the source side wiring layer S corresponding to the intersection portion
while _a1, the line width of the S _a2 equivalent, in accordance with the wiring length of the source side interconnect layer S _a1, S _a2, S _a3, and an expansion portion S ₁₁ and the narrow portion S ₂₂ of the wiring width is provided to them, The magnitude of the electrical resistance parasitic on them is also the same. Therefore, it is possible to further prevent the difference between the delays of the video signals in the respective paths, and further improve the display characteristics.

In this embodiment, the video signal lines V ₁ , V ₂ , V ₃ are associated with red, green, and blue, and three columns of video signal lines are described, but the present invention is not limited to this. The number may be increased. Furthermore, video signal lines V ₁ and V
_Although only the source side wiring layer and the driving signal line have been described as the wirings intersecting V ₂ and V ₃ , the present invention can be applied to the case where other wirings intersect.

[0018]

As described above, in the active matrix display panel according to the present invention, the overlapping area of the wiring in each crossing region of the source side wiring layer and the video signal line is made equal at any crossing portion, and It is characterized in that the electric resistance of the source side wiring layer is adjusted correspondingly to the wiring length by an electric resistance correction section formed in the source side wiring layer. Therefore, according to the present invention, since the parasitic capacitance and electric resistance of the video signal line are equal to each other, there is no difference in the delay of the video signal in each path, so that the display characteristics are improved. Also, even if an abnormal potential is supplied to the wiring due to static electricity, etc., the rush current does not concentrate on a specific path, so
This has the effect of improving its reliability.

[Brief description of drawings]

FIG. 1 is a schematic plan view around a formation region of a video signal line in an active matrix liquid crystal display panel according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line IV-IV ′ in FIG.

3A is an explanatory diagram showing a capacitance parasitic on a video signal line shown in FIG. 1, and FIG. 3B is an explanatory diagram showing a resistance parasitic on a source side wiring layer thereof.

FIG. 4 is a block section showing the overall configuration of an active matrix liquid crystal display panel.

FIG. 5 is a schematic plan view around a formation region of a video signal line in a conventional active matrix liquid crystal display panel.

6 is a cross-sectional view taken along line VI-VI ′ of FIG.

FIG. 7 is an explanatory diagram showing a capacitance parasitic on the video signal line shown in FIG.

[Explanation of symbols]

11 ... Transparent substrate 12 ... Source line drive circuit 13, 20 ... Shift register section 21 ... Gate line drive circuit 22 ... Pixel matrix 29 ... Thin film transistor 30 ... Liquid crystal cell G ₁ , G ₂ , G ₃ ... Driving signal lines S ₁ , S ₂ , S ₃ ... Source side wiring layers S _a1 , S _a2 , S _a3 ... Source side wiring layers S _b1 , S _b2 , S _b3 · · · source side interconnect layer S ₁₁ · · · extension (electrical resistance correction portion) S ₂₂ · · · narrow portion (electric resistance correction _{portion) T 1, T 2, T} 3 ··· switch circuit V ₁ , V ₂ , V ₃ ... Video signal line X ₁ , X ₂ , X ₃ ... Source line Y ₁ , Y ₂ ... Gate line

Claims (1)

[Claims] 1. On the source line drive circuit side formed between the pixel matrix formation region on the same substrate and the outer peripheral edge of the substrate, when n is an integer of 3 or more, the pixel matrix formation region is formed. Video signal lines of n columns which are formed on the outer peripheral side in the direction of the side thereof and are arranged in parallel from the side of the formation region of the shift register portion of the source line drive circuit toward the side of the formation region of the pixel matrix, and Each video signal line is conductively connected through an interlayer insulating film, and the n-side source side wiring layers from which the pixel matrix formation region side is provided, each of these source side wiring layers, and each of these source side wiring layers And a state in which the source line wiring layer and the source line are conductively connected to each other based on a driving signal output from the shift register section side. N switch parts whose operations are respectively switched to the connected state, and the drive signal which intersects the video signal line formed from the shift register part side toward the switch part through the interlayer insulating film. And n driving signal lines for inputting each of the switch units, and the overlapping areas of the wirings in each intersection region of the driving signal lines and the video signal lines are equal to each other, The overlapping areas of the wirings in the respective intersecting regions of the source side wiring layer and the video signal line are equal to each other, and the source side wiring layer has the switch from the conductive connection position with the video signal line. Adjust the width dimension according to the wiring length to the conductive connection position with the part,
An active matrix display panel, characterized in that an electric resistance correction section is formed so that the electric resistance between the source side wiring layers should be equal to each other.