JP3114372B2 - Active matrix display panel - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix display panel with a built-in driver, and more particularly to a wiring layer structure technology.

[0002]

2. Description of the Related Art Among flat display panels that display information by utilizing the orientation state of liquid crystal, etc., among active-matrix liquid crystal display panels with built-in drivers,
As shown in a block diagram in FIG. 10, the overall configuration is such that a pixel matrix 10, a signal line driving circuit 11 (X side driver circuit) and a scanning line driving circuit 12 (Y side driver circuit) are formed on the same transparent substrate. Accordingly, the display device has been reduced in size, increased in definition, and reduced in cost. Here, the signal line driving circuit 11 generates the clock signals CL, CL *
(A clock signal having a phase opposite to that of CL), a sample-and-hold circuit section 14 having an n-type TFT operating as an analog switch based on an output signal sent from the shift register section 13 and a video signal line 15. On the other hand, the scanning line driving circuit 12 has a shift register and a buffer circuit as necessary. The pixel matrix 10 includes a plurality of signal lines X 1, X 2, X 3... Connected to the signal line driving circuit 11 and a scanning line driving circuit 12.
Are connected to a plurality of scanning lines Y1, Y2,..., And these scanning lines Y1, Y2,.
, X2, X3,..., Are formed at the intersections of the pixel regions G11, G12,..., G21, G22,. .., T21,..., T22,. Here, the shift register unit 13 includes a shift register 130 formed of an inverter 131 and a clocked inverter 132, and a buffer circuit 133 formed of an inverter. Each of these inverters is a p-type TFT and an n-type TFT. The p-type TFT and the n-type TFT are wiring-connected in a wiring layer to form a drive circuit. The signal line drive circuit 11 is provided with a positive power supply line VDD from the positive power supply side and a negative power supply line VSS from the negative power supply side. The shift register section 13 receives clock signals CL and CL * in the shift register section. 13
, Two clock signal lines 161a and 161b are formed.

In a driver-incorporated active matrix display panel having such a structure, the conventional pixel area is formed by a transparent substrate 51 (glass substrate) supporting the entire liquid crystal display panel, as shown in a sectional view of FIG. A polycrystalline silicon layer 52 is formed on the front surface side. Phosphorus as an n-type impurity is introduced into the polycrystalline silicon layer 52 except for a channel region 52a which is an intrinsic polycrystalline silicon region. (TFT) source 53
And a drain 54 are formed. Here, the introduction of phosphorus is performed by ion implantation using the gate electrode 56 on the gate oxide film 55 formed on the surface side of the polycrystalline silicon layer 51 as a mask. Also, on the front side of the TFT 57,
An interlayer insulating film 58 made of a silicon oxide film is deposited, of which a signal line 59 as an aluminum layer is conductively connected to a source 53 through a first connection hole 58a.
The pixel electrode 60 serving as an ITO layer is conductively connected to the drain 54 through the connection hole 58b.

[0004]

However, in an active matrix display panel with a built-in driver, both the pixel region side and the drive circuit side have a gate oxide film 55 and an interlayer insulating film 58 (the drive circuit side has these insulating layers). Since the multilayer wiring structure is configured using only the same layer as the interlayer insulating film), the degree of freedom in designing these structures is low, so that a structure suitable for each function cannot be realized. is there. For example, in the pixel region, both the signal line 59 and the pixel electrode 60 are formed on the surface side of the interlayer insulating film 58 and are in the same layer. A planar gap of a predetermined dimension must be secured between the end portion and the gap, and the portion corresponding to the gap hinders high integration, and at the same time, the ratio of the area through which light can pass in the pixel area (opening area). Rate) is sacrificed. Moreover, since the pixel region side and the drive circuit side are formed on the transparent substrate 51 with the help of each other, the structure on the pixel region side and the structure of the drive circuit are mutually restricted, and The structure cannot be adapted to the function. For example, since the signal line 59 and the wiring layer on the drive circuit side must be formed simultaneously and made of the same material, the clock signal line 161
In order to prevent signal delay in wiring layers such as a and 161b, the wiring layer on the drive circuit side has a thickness of 0.5 to 1.0.
When a thick aluminum layer having a thickness of μm is employed, the thickness of the signal line 59 on the pixel region side also increases,
Since the surrounding flatness is impaired, rubbing of the liquid crystal there is hindered, and there is a problem that display quality is deteriorated.

[0005] In view of the above problems, an object of the present invention is to provide:
A driver-incorporated active type that can improve the display quality by increasing the degree of freedom in designing the multilayer wiring structure and adopting a wiring structure suitable for the function on both the pixel area side and the drive circuit side It is to realize a matrix display panel.

[0006]

In order to solve the above-mentioned problems, the present invention provides a plurality of scanning lines and a plurality of signal lines on a substrate.
And a thin film transistor connected to each of the scanning lines and each of the signal lines.
Transistor and a pixel electrode connected to the thin film transistor.
And a source and a drain of the thin film transistor.
Silicon layer to be a region, gate insulating film, and gate electrode
And an active matrix display in which
In the panel, it is arranged on the silicon layer and the gate electrode.
A first interlayer insulating film disposed on the first interlayer insulating film and
Through the first connection hole formed in the gate insulating film.
The signal line connected to the source region and the first interlayer insulation
Through the film and the second connection hole formed in the gate insulating film.
A stacked electrode connected to the drain region
Second interlayer insulation formed on signal lines and the stacked electrodes
An edge film and a third connection hole formed in the second interlayer insulating film.
And the pixel electrode connected to the stacked electrode through
The signal lines and the stacked electrodes are etch-resistant
It consists of a conductive light-shielding layer with high
The end of the pixel electrode is connected to the signal line and the second interlayer insulating film.
Are overlapped with each other .

Here, the signal line and the stacked electrode
Preferably contains molybdenum as a main component .

The signal line and the signal line are provided on the substrate.
A drive circuit for sending a signal to at least one of the scanning lines
And the wiring layer of the drive circuit is lower than the signal line.
Preferably, it is made of a resistive material .

The wiring layer is mainly made of aluminum.
Minutes .

[0010]

[0011]

In the pixel region of the active matrix display panel according to the present invention, the signal line is conductively connected to the source region of the thin film transistor via the first connection hole formed in the first interlayer insulating film and the gate insulating film. On the other hand, the pixel electrode is provided through the second connection hole of the first interlayer insulating film and the gate insulating film.
The stacked electrode and signal line connected to the drain region
And third contact of the second interlayer insulating film formed on the stacked electrode
Conductive connection to the stacked electrode through the connection hole, and communication with the pixel electrode
No. electrode and has a structure via a second interlayer insulating film,
Signal lines and stacked electrodes are resistant to etching and light
Of the pixel electrode
Overlap with the signal line via the second interlayer insulating film . Therefore, the aperture ratio in the pixel region can be increased.
Further, for the pixel region, even in the driver circuit side, in an interlayer insulating film in the same layer on the first interlayer insulating film and the second interlayer insulating film
Kill for, that-out <br/> in that providing the low-resistance wiring layer sets the material and the thickness is preferentially only low resistance on the second interlayer insulating film.

[0012]

Next, an embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a plan view showing a part of an active matrix of a liquid crystal display panel with a built-in driver according to a first embodiment of the present invention. FIG. 2 is a sectional view taken along line AA 'of FIG. 3 is a sectional view taken along line BB '.
Here, the overall configuration of the liquid crystal display panel with a built-in driver according to the present embodiment is the same as that of the liquid crystal display panel with a built-in driver shown in FIG. 10, and a description thereof will be omitted.

In FIG. 1, in the active matrix of the liquid crystal display panel with a built-in driver of this embodiment, vertical signal lines 21a, 21b... (Signal lines) and horizontal scanning lines 31a, 31b. (Scanning lines) are wired in a grid pattern, and pixel regions 20a, 20b,... Of the matrix array are formed between them.

Hereinafter, the structure of the pixel region 20b will be described as an example. In the pixel region 20b, a thin film transistor (TFT) 8 is formed by the source 4 to which the signal line 21a is conductively connected, the gate electrode 5 to which the scanning line 31b is conductively connected, and the drain 7 to which the pixel electrode 6 is conductively connected.
Are formed. Here, the pixel electrode 6 is a transparent electrode made of ITO, and is formed over substantially the entire surface of the pixel region 20b. For example, the end 6 of the pixel electrode 6
1a is located above the signal line 21a, while the opposite end 61b is located above the signal line 21b. The end 62a of the pixel electrode 6 is located above the preceding scanning line 31a, and a capacitance is formed in the pixel region 20b. The signal line 21a is formed of a molybdenum layer as a conductive light-shielding layer having high etching resistance and light-shielding properties, whereas the scanning line 31b is formed of an impurity-doped polycrystalline silicon layer. I have.

As shown in FIG. 2, the TFT 8 has a cross-sectional structure in which a polycrystalline silicon layer 24 is formed on the front side of a transparent substrate 9 (glass substrate) supporting the entire liquid crystal display panel. Except for the channel region 24a, which is an intrinsic polycrystalline silicon region, the source 24 and the drain 7 are formed by introducing phosphorus as an n-type impurity. Here, the phosphorus is introduced by using ion implantation or ion shower doping using the gate electrode 5 on the gate oxide film 22 formed on the surface side of the polycrystalline silicon layer 24 as a mask.
And the drain 7 is self-aligned. A lower interlayer insulating film 23 made of a silicon oxide film is deposited on the surface side of the TFT 8, and the first connection hole 2 is formed in the lower interlayer insulating film 23 and the gate oxide film 22.
3a is open. A signal line 21a made of a molybdenum layer is formed on the surface side of the lower interlayer insulating film 23. The signal line 21a is conductively connected to the source 4 of the TFT 8 through the first connection hole 23a. ing. Further, an upper interlayer insulating film 27 is formed on the surface side of the lower interlayer insulating film 23.
7. A second connection hole 27a is opened in the lower interlayer insulating film 23 and the gate oxide film 22. A pixel electrode 6 made of an ITO layer is formed on the surface side of the upper-layer interlayer insulating film 27, and the pixel electrode 6 is connected to the second connection hole 2.
It is conductively connected to the drain 7 of the TFT 8 via 7a. Thus, a potential can be applied from the drain 7 to the pixel electrode 6.

As shown in FIG. 1 and FIG. 3, the pixel electrode 6 of the pixel region 20b has an end 61a having a signal line 21a for dividing the pixel region 20b to which the pixel electrode 6 belongs from an adjacent pixel region 20a. In the upper position, the end 61a of the pixel electrode 6 in the pixel region 20b and the end 61c of the pixel electrode in the adjacent pixel region 20a face each other at a position above the signal line 21a. Here, the pixel electrode 6 is formed on the upper layer side of the upper interlayer insulating film 27, while the signal line 21a is formed on the lower layer side of the upper interlayer insulating film 27. A multilayer wiring structure is formed via an upper interlayer insulating film 27. For this reason, even if the end 61a of the pixel electrode 6 and the signal line 21a are arranged close to each other, they are not short-circuited, so that the formation area of the pixel electrode 6 can be widened and the aperture ratio is high. In addition, by utilizing the fact that the end 61a of the pixel electrode 6 is disposed above the signal line 21a and that the signal line 21a is formed of a light-shielding molybdenum layer, the driver built-in type liquid crystal display of this example is used. In the active matrix of the panel, the signal line 21a is used as a light-shielding mask in this direction, and the scanning line 31a,
Only the light shielding mask in the direction of 31b is formed.

Further, the active matrix 20 of this embodiment
In FIG. 10, as shown in FIG. 10, a video signal from a video signal line 15 is
X2, X3 (pixel line G1) via (signal line 21a)
, G21, G22,... (Pixel region 20b) and a signal line driving circuit 11 (X-side driver circuit) for transmitting the signals in time series to each pixel region G11, G12,.
(Pixel region 20b) of thin film transistors T11, T12,.
A scanning line driving circuit 12 (Y side driver circuit) for transmitting a scanning signal for turning on / off the T21, T22... (TFT 8) via the scanning lines Y1, Y2. Display devices have been reduced in size, definition and cost have been reduced. Here, both the signal line driving circuit 11 and the scanning line driving circuit 12 constitute a shift register. For example, in the signal line driving circuit 11, an inverter 131 using a TFT as a circuit element, a clocked inverter 132 and a buffer circuit 133, and these inverters are both p-type TFTs and n-type TFTs.
And FT. Here, a p-type TFT and an n-type TFT
The FT is, for example, wired and connected as shown in FIG.
It has a MOS structure. That is, in FIG.
While the drain 301 of the p-type TFT 30 and the drain 311 of the n-type TFT 31 are conductively connected in the first wiring layer 32 (lower wiring layer), the source 3 of the p-type TFT 30
02 has a thickness of 0.5 μm from the side of the positive power supply wiring layer _VDD.
Second wiring layer 33 of aluminum layer (low-resistance wiring layer) is conductively connected to the source 312 of the n-type TFT31 from thickness 0.5μm layer of aluminum from the side of the negative power supply wiring layer V _SS of Third wiring layer 34 (low-resistance wiring layer)
Are conductively connected. Here, the p-type TFT on the drive circuit side
The 30, the n-type TFT 31, the wiring layer and the interlayer insulating film thereof are formed by making maximum use of the process of forming each component on the pixel region side. 2 and 4
The respective components formed in the steps after the TFT forming step will be described with reference to FIG. First,
The lower interlayer insulating film 23 on the pixel region 20b side and the second interlayer insulating film 36 on the lower layer side of the first wiring layer 32
Simultaneously formed and in the same layer. The signal line 31a on the side of the pixel region 20b and the first wiring layer 32 are formed simultaneously and are in the same layer, and both are molybdenum layers. Further, the upper interlayer insulating film 27 on the pixel region 20b side and the first interlayer insulating film 37 on the upper layer side of the second interlayer insulating film 36 and the first wiring layer 32 are formed at the same time. In layers. Utilizing the fact that the upper interlayer insulating film 27 is formed in the pixel region 20b, the second wiring layer 33 and the third wiring layer 34 are formed separately from the step of forming the pixel region 20b. .

Therefore, the second wiring layer 33 and the third wiring layer 34 are made of an aluminum layer (low-resistance wiring layer) having a thickness of 0.5 to 1.0 μm that is not used in the pixel region 20b.
To reduce the wiring resistance. That is, in a liquid crystal display panel with a built-in driver, when the number of pixels is increased and the number of shift registers is increased to 200 or more, low resistance such as an aluminum layer or an aluminum-silicon layer having a thickness of 0.5 to 1.0 μm is obtained. This is because it is necessary to set the sheet resistance to 100 to 50 mΩ / □ using a wiring layer to prevent signal delay. Here, the low-resistance wiring layer composed of the aluminum layer is provided between the p-type TFT 30 and the n-type TFT 31 in addition to the wiring layer.
Positive power supply wiring V _DD , negative power supply wiring V _SS , video signal line 15 and clock signal line 16 required to have low resistance
1a and 161b. Note that the first wiring layer 3
2 and the signal line 21a are formed of a molybdenum layer having a thickness of about 0.2 μm, and have a sheet resistance of 0.5 to 0.6.
Although it is Ω / □, if the liquid crystal display panel has a diagonal of 5 to 6 ″, the problem of delay due to the sheet resistance does not occur.

As described above, in the active matrix display panel of this embodiment, the signal line 21a is connected to the source of the TFT 8 via the gate insulating film 22 of the TFT 8 and the lower interlayer insulating film 23 formed on the surface side of the gate electrode 5. 4, the pixel electrode 6 is connected to the upper interlayer insulating film 27 formed on the surface side of the lower interlayer insulating film 23.
And the signal line 21a and the pixel electrode 6 have a multilayer structure with an interlayer insulating film interposed therebetween, so that the ends 61a and 61b of the pixel electrode 6 are located near the signal lines 21a and 21b, Can be arranged up to the upper position, so that the aperture ratio in the pixel region can be increased. In addition, since the contact resistance between molybdenum forming the signal line 21a and silicon on the TFT side is small, the connection hole 23a in the pixel region 20b can also be reduced. In other words, in order to secure the same aperture ratio, the pixel region 20b can be reduced, while the drive circuit side can be formed at a fine pitch by utilizing the three-layer structure on the drive circuit side. High integration of the active matrix display panel can be realized. In addition, the end 61a of the pixel electrode 6 is arranged up to the position above the signal line 21a, and the signal signal line 21a is formed of a molybdenum layer having a light-shielding property. As a result, hillocks and the like do not occur, and the signal line 21a and the pixel electrode 6 are not short-circuited. In addition, the signal line 21a itself can constitute a light-shielding mask (black stripe) in the direction of the signal line 21a. it can. Therefore, the light-shielding mask in the signal line 21a direction is
Since it is not necessary to provide on the counter electrode side (counter substrate), a margin for alignment is not required. Moreover, the molybdenum layer constituting the signal line 21a has a high light-shielding property, and is formed separately from the drive circuit side to have a thickness of about 0.2 μm.
Since the molybdenum layer has a small m, the flatness in the vicinity of the signal line 21a is not impaired. Therefore, the orientation of the liquid crystal rubbed on the transparent substrate 9 is not disturbed even in the vicinity of the signal line 21a. Therefore, in the active matrix display panel of this example, as shown by the hatched area in FIG. 5 in the opening of the pixel region 20b, a light-shielding mask BM in the direction of the scanning line 31a is required on the counter electrode side. In the direction of the signal line 21a, since the signal line 21a itself functions as a light shielding mask, there is no need to provide a margin.
Up to a can be used as an opening. For this reason, 50 μm
In the corner pixel region 20b, the vertical dimension of the opening is 38 μm.
m, the lateral dimension of the opening can be assured to 45 μm, and the opening ratio is as high as 68.4%. On the other hand, in the conventional active matrix display panel, as shown by the hatched area in FIG. 6, the vertical dimension of the opening is equal to 38 μm in the pixel area of 50 μm square.
When a light-shielding mask is provided on the counter electrode side, a margin M1 of about 4 μm corresponding to the alignment accuracy and a margin M2 of about 3 μm for shielding the vicinity of a signal line where the alignment of liquid crystal is disturbed by a step are required. The lateral dimension of the opening can only be secured at 31 μm, and the aperture ratio is 47.1%.
And low. Therefore, in the active matrix display panel of the present example, since the aperture ratio is high, the display quality is high. Further, in the active matrix display panel of this example, the power required for displaying the same luminance is small and the power consumption is reduced, so that the active matrix display panel is suitable for an apparatus using a battery as a power source, such as a portable video camera.

Further, since the molybdenum layer forming the signal line 21a has etching resistance to the HBr-based ITO etchant, it is not etched even if it is provided below the pixel electrode 6, so that there is a problem in the manufacturing process. There is no. Moreover, even if there is a pinhole or the like in the upper interlayer insulating film 27, there is no occurrence of disconnection in the signal line 21a.

[Embodiment 2] FIG. 7 is a sectional view of an active matrix of a liquid crystal display panel with a built-in driver according to Embodiment 2 of the present invention. Here, a plan view of the active matrix of the liquid crystal display panel with a built-in driver according to the present embodiment is shown in the same manner as in FIG. 1, and the entire configuration is the same as that of the liquid crystal display panel with a built-in driver shown in FIG. Corresponding parts have the same reference characters allotted, and description thereof will not be repeated.

As shown in FIG. 7, in the active matrix of the liquid crystal display panel with a built-in driver according to the present embodiment, the TFT 8 formed in the pixel region 40b is formed on a transparent substrate 9 (glass substrate) supporting the entire liquid crystal display panel. A polycrystalline silicon layer 24 is formed on the surface side, and the polycrystalline silicon layer 24 has a source 4 doped with phosphorus as an n-type impurity except for a channel region 24a which is an intrinsic polycrystalline silicon region. And a drain 7 are formed.
A lower interlayer insulating film 43 made of a silicon oxide film is deposited on the front side of the TFT 8, and a first connection hole 43 is formed in the lower interlayer insulating film 43 and the gate oxide film 22.
a is open. A signal line 41a made of a molybdenum layer is formed on the surface of the lower interlayer insulating film 43. The signal line 41a is conductively connected to the source 4 of the TFT 8 via the first connection hole 43a. ing. further,
The lower interlayer insulating film 43 and the gate oxide film 22
The connection hole 43b is also opened, and the lower interlayer insulating film 4 is formed.
3, a stacked electrode 49 made of a molybdenum layer formed simultaneously with the signal line 41a is formed, and the stacked electrode 49 is connected to the TFT 8 via the second connection hole 43b.
Is electrically connected to the drain 7 of the semiconductor device. An upper interlayer insulating film 47 is formed on the surface side of the lower interlayer insulating film 43, and a third connection hole 47a is opened in the upper interlayer insulating film 47. In addition, the upper interlayer insulating film 47
A pixel electrode 46 made of an ITO layer is formed on the surface of the pixel electrode 46. The pixel electrode 46 is conductively connected to the stacked electrode 49 via the third connection hole 47a. Thus, a potential can be applied from the drain 7 to the pixel electrode 46.

In the active matrix of the liquid crystal display panel with a built-in driver according to the present embodiment, as shown in FIG. 8, the end 461a of the pixel electrode 46 partitions the pixel region 40b to which the pixel electrode 46 belongs from the pixel region 40a. Signal line 4
1a. Here, the pixel electrode 46 is formed on the upper layer side of the upper interlayer insulating film 47, while the signal line 41 a is formed on the lower layer side of the upper interlayer insulating film 47.
The pixel electrode 46 and the signal line 41a are connected to the upper interlayer insulating film 47.
, The pixel electrode 46 has a multilayer wiring structure.
Even if the end portion 461a and the signal line 41a are arranged close to each other, they are not short-circuited, so that the formation area of the pixel electrode 46 is wide and the aperture ratio is high.

Further, in the active matrix according to the present embodiment, similarly to the active matrix according to the first embodiment, a video signal is applied to the pixel region 40 on the transparent substrate 9.
a signal line driving circuit (X-side driver circuit) for transmitting a time-series signal to the pixel region 40b, and a scanning line driving circuit (Y-side driver circuit) for transmitting a scanning signal for turning on and off the TFT 8 to the pixel region 40b. The wiring layer of the shift register formed in the signal line driving circuit and the scanning line driving circuit utilizes the fact that the upper interlayer insulating film 47 is formed on the signal line 41a in the pixel region 40b. Then, as shown in FIG. 4, the second wiring layer 33 and the third wiring are formed of an aluminum layer (low-resistance wiring layer) having a thickness of 0.5 to 1.0 μm that is not used in the pixel region 40b. By forming the layer 34, the wiring resistance is reduced.

As described above, in the active matrix display panel of this example, the signal line 41a and the pixel electrode 46
Has a multilayer structure with an interlayer insulating film interposed therebetween, so that the pixel electrode 46 and the signal line 41a do not short-circuit, so that the formation area of the pixel electrode 46 is maximized and the aperture ratio of the pixel area 46 is reduced. Can be enhanced. In addition, since the pixel area signal line 41a is made of a molybdenum layer having a light-shielding property, the light-shielding mask can be formed by itself. Therefore, in the signal line 41a direction, the light-shielding width of the light-shielding mask is minimized. The aperture ratio can be improved.
Further, since the molybdenum layer forming the signal line 41a has high etching resistance, the same effect as the active matrix display panel according to the first embodiment is obtained, for example, there is no trouble in the manufacturing process. Further, the third connection hole 47a is formed in the upper interlayer insulating film 47 by using the stacked electrode 49 formed of a molybdenum layer having high etching resistance.
Even when dry etching using CF ₄ or the like is employed, the drain electrode 7 is protected by the stacked electrode 49, so that the degree of freedom in the process is high.

Further, in the active matrix display panel of this embodiment, the pixel electrode 46 is conductively connected to the drain 7 of the TFT 8 via the stacked electrode 49, and the molybdenum layer forming the stacked electrode 49 is formed of a TFT.
The contact resistance with respect to the silicon constituting the drain 7 is lower than that of aluminum or ITO. For example, in a 3 μm square contact, silicon and ITO
Has a contact resistance of 30 to 50 kΩ,
The contact resistance between silicon and molybdenum is 0.1 to 0.1.
5 kΩ, contact resistance between molybdenum and ITO is 0.0
1 to 0.02 kΩ. Therefore, the first connection hole 43a and the second connection hole 43b may be small while the electrical characteristics are improved. Also, the lower interlayer insulating film 43
The second connection hole 43b having a minimum dimension, for example, a 3 μm square.
After forming, as shown in FIG. 8, an extended portion 241a of the polycrystalline silicon layer 24 called a dogbone shape is formed.
Since the stacked electrode 49 is formed according to the shape and size of the (drain 7), as shown in FIG. 9A, a third connection hole for conductively connecting the pixel electrode 46 to the stacked electrode 49 is formed. 47a can also be formed in 3 μm square.
Therefore, the size of the expanded portion 241a of the polycrystalline silicon layer 24 and the size of the stacked electrode 49 are sufficient to be 7 μm square even if a margin of 2 μm is added to both sides of the size of the second connection hole 43b of 3 μm square. is there. Therefore, even if a two-layer structure of the lower interlayer insulating film 43 and the upper interlayer insulating film 47 is used,
The aperture ratio is not sacrificed. That is, unlike the active matrix display panel of the present example, as shown in FIG. 9B, when forming a connection hole communicating with the upper interlayer insulating film and the lower interlayer insulating film, the alignment accuracy is taken into consideration. Then, the size of the connection hole 431b formed in the lower interlayer insulating film needs to be larger than the size of the connection hole 471a formed in the upper interlayer insulating film. Even if the size of the hole 471a is 3 μm square,
The dimensions of the connection hole 431b formed in the lower interlayer insulating film are as follows:
Since it is necessary to add a margin of 2 μm to both sides and make it 7 μm square, the size of the expanded portion 241 b of the polycrystalline silicon layer 241 needs to be made 11 μm square by adding a margin of 2 μm to both sides. However, the active matrix display panel of the present example does not require a large extension.

The shape and size of each region of the liquid crystal display panel are properties that should be set to predetermined conditions according to the size and use of the liquid crystal display panel to be manufactured, and are not limited. It is. As the conductive light-shielding layer having high etching resistance, tungsten or the like can be used in addition to molybdenum.

[0029]

As described above, according to the present invention, in the active matrix display panel according to the present invention, the signal line and the pixel electrode has a structure through the second interlayer insulating film, the signal line及
And stacked electrodes are conductive with high etching resistance and light shielding.
It consists of an electrically conductive light-shielding layer, and the end of the pixel electrode
And a second interlayer insulating film . Therefore, according to the present invention, the display quality can be improved by increasing the aperture ratio in the pixel region. Also,
Since the second interlayer insulating film is provided on the surface side of the signal line, the wiring layer on the drive circuit side is not formed simultaneously with the signal line, but is separately formed on the surface side of the interlayer insulating film in the same layer as the second interlayer insulating film. Therefore, an appropriate wiring material can be adopted for each region between the pixel region side and the drive circuit side. Therefore, the signal line is composed of a thin conductive light shielding layer,
By using itself as a light-shielding mask, it is possible to minimize the light-shielding width of the light-shielding mask and increase the aperture ratio.
The display quality can be further improved.

Furthermore, since a structure that electrically connected to the drain via the electrode stacked pixel electrode, the electrode stacked between the second interlayer insulating film and the first interlayer insulating film relays, the first interlayer insulating Since the size of the second connection hole formed in the film can be minimized, the aperture ratio is not sacrificed even with a two-layer structure of the first interlayer insulating film and the second interlayer insulating film.

[Brief description of the drawings]

FIG. 1 is a plan view showing a part of a matrix array of a liquid crystal display panel with a built-in driver according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line AA 'of FIG.

FIG. 3 is a sectional view taken along the line BB 'of FIG.

FIG. 4 is a cross-sectional view showing a part of a driving circuit formed on the same substrate as the matrix array shown in FIG. 1;

5 is an explanatory diagram showing an opening region in a pixel region of the matrix array shown in FIG.

FIG. 6 is an explanatory diagram showing an opening region in a pixel region of a conventional matrix array for explaining an effect of enlarging an opening region in a pixel region of the matrix array shown in FIG. 1;

FIG. 7 is a cross-sectional view illustrating a part of a matrix array of the liquid crystal display panel with a built-in driver according to the first embodiment of the present invention.

8 is a plan view showing a part of a matrix array of the liquid crystal display panel with a built-in driver shown in FIG. 7;

9A is an explanatory view showing the periphery of a region where second and third connection holes are formed in the matrix array of the liquid crystal display panel with a built-in driver shown in FIG. 7, and FIG. 9B is a view showing FIG. FIG. 9 is an explanatory diagram around a connection hole formation region as a comparative example for describing feature points around a second and third connection hole formation region.

FIG. 10 is a block diagram showing an entire configuration of a matrix array of a liquid crystal display panel with a built-in driver.

FIG. 11 is a sectional view of a matrix array of a conventional liquid crystal display panel with a built-in driver.

[Explanation of symbols]

 4, 302, 312 Source 5 Gate electrode 6, 46 Pixel electrode 7, 301, 311 Drain 8 TFT (thin film transistor) 10 Pixel matrix 11 Signal line drive circuit 12 Scanning line drive circuit 13 Shift register section 14 Sample hold circuit section 15 Video signal lines 20a, 20b, 40a, 40b Pixel regions 21a, 21b, 41a: Signal line 31a, 31b: Scan line 22: Gate oxide film 23, 43: Lower interlayer insulating film 27, 47: Upper interlayer insulating film 30: p-type TFT 31 ... n-type TFT 32 ... first wiring layer (lower wiring layer) 33 ... second wiring layer (low resistance wiring layer) 34 ... third wiring layer (low resistance wiring) Layer) 36... Second interlayer Insulating film 37: First interlayer insulating film 49: Stacked electrode 131: Inverter 132: Clocked inverter 130: Shift register 133: Buffer circuit G11, G12, G21, G22 ··· Pixel area T11, T12 ··· T21, T22 ··· Thin film transistor X1, X2, X3 ··· Signal line Y1, Y2 ··· Scanning line

Claims (4)

(57) [Claims] A plurality of scanning lines and a plurality of signal lines are provided on a substrate.
And a thin film transistor connected to each of the scanning lines and each of the signal lines.
Transistor and a pixel electrode connected to the thin film transistor.
And a source / drain of the thin film transistor
Silicon layer to be a region, gate insulating film, and gate electrode
And an active matrix display in which
In the panel, a first interlayer disposed on the silicon layer and the gate electrode
An insulating film, the first interlayer insulating film and the gate insulating film;
The source region is connected to the source region through the formed first connection hole.
The signal line, the first interlayer insulating film, and the gate
The drain region is formed through a second connection hole formed in the insulating film.
A stacked electrode connected to a region, the signal line and the product
A second interlayer insulating film formed on the lift-up electrode;
Stacking via a third connection hole formed in the interlayer insulating film;
And the pixel electrode connected to the gate electrode, wherein the signal line and the stacked electrode have etching resistance and
And a conductive light-shielding layer having high light-shielding properties and the pixel
An end of the electrode is interposed between the signal line and the second interlayer insulating film.
An active matrix display panel characterized by overlapping . 2. The signal line and the stacked electrode are
2. The method according to claim 1, wherein the main component is lithium.
Active matrix display panel of the mounting. 3. The method according to claim 1 , wherein the signal line and the scanning line are provided on the substrate.
A drive circuit for sending a signal to at least one of the lines
Wherein the wiring layer of the drive circuit has a lower resistance than the signal line.
3. The method according to claim 1, wherein the material is made of a suitable material.
An active matrix display panel according to 1. 4. The wiring layer contains aluminum as a main component.
The active matrix display panel according to claim 3, wherein: