JP3064596B2 - Liquid crystal panel and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal panel and a method of manufacturing the same, and more particularly, to a structure technology of a wiring layer thereof.

[0002]

2. Description of the Related Art A liquid crystal display panel, which is a typical flat panel display, includes a transparent substrate on one side on which a common electrode is formed and a transparent substrate on the other side on which a matrix array having a large number of pixel regions is formed. Liquid crystal is sealed between the pixel electrodes, and the potential applied between the common electrode and the pixel electrode in each pixel region is controlled to change the alignment state of the liquid crystal in each pixel region. The typical one is TFT
This is a method in which a predetermined signal potential is applied to each pixel electrode using a (thin film transistor), and the structure of the matrix array is shown in FIG. As shown in FIG.
1 have a source 4, a drain 7 and a gate 5
Is formed, and its source 4 has a data line 2a through a connection hole 52a of an interlayer insulating film 52.
(Signal line) is conductively connected, while a gate line (scanning line / not shown) is conductively connected to the gate 5. Also,
A pixel electrode 6 made of ITO is conductively connected to the drain 7 via a connection hole 52b of the interlayer insulating film 52. An equivalent circuit of such a matrix array is represented, for example, as shown in FIG. In this equivalent circuit, in each pixel region, through the data line D _i in a state in which a predetermined data signal is applied to the source of the TFT _ij, the drive potential from the gate line G _j to the gate of the TFT _ij applied Then, a predetermined signal potential is applied to the liquid crystal display element _Cij formed by the pixel electrode and the common electrode.
Thereby, a potential is applied to the liquid crystal of the liquid crystal display element C _ij ,
The alignment state of the liquid crystal changes.

[0003] Here, the data lines D _i gate line drive circuit 32 supplies a drive signal to the data line driving circuit 31 and the gate line G _j and supplies the data signal to, any, TF
It is composed of T _i , TFT _{j, and the} like, and is formed on a transparent substrate on which a matrix array is formed because the number of lead lines to the outside of the substrate can be greatly reduced.

[0006] In these drive circuits 31 and 32, a wiring layer for circuit-connecting TFT _i and TFT _j is formed on a transparent substrate 9 by a first wiring layer 53, as shown in FIG. Second wiring layer 54 and third wiring layer 5
5 are formed to form a two-layer wiring structure with an interlayer insulating film 52 interposed therebetween.

[0005]

In a liquid crystal display panel having such a configuration, in addition to a large display surface and a low price, a high definition display is required.
In order to respond to this demand, there is a tendency that each pixel area is miniaturized to increase the number of pixels. However, in the conventional liquid crystal display panel, there are the following problems in miniaturizing the pixel region.

In order to cope with miniaturization of each pixel area,
It is necessary to narrow the pitch between the elements forming the data line driving circuit 31 and the gate line driving circuit 32. To do that,
The pitch of each wiring layer 53, 54, 55 is also, for example, 10 μm.
m or less, but the wiring layers 53, 5
4 and 55 are formed in a plane corresponding to the arrangement of the TFTs constituting the drive circuit, and thus there is a limit to narrowing their pitch.

With the miniaturization of each pixel region, restrictions on the data lines _Di and the gate lines _Gj increase, and the reliability of the conventional liquid crystal panel tends to be reduced if the structure is not changed. For example, if disconnection to the data line D _i is generated, all the pixel areas display defects corresponding thereto. Therefore, it is desired to adopt a redundant design of the wiring layer with respect to the conventional liquid crystal display panel. This will hinder lower prices.

[0008] In view of the above problems, an object of the present invention is to provide:
An object of the present invention is to realize a driver-incorporated liquid crystal panel capable of coping with the miniaturization of a pixel region and a method of manufacturing the same.

[0009]

According to the present invention, a gate line, a data line, a thin film transistor connected to the gate line and the data line, a pixel electrode connected to the thin film transistor, and a driving circuit are provided on a substrate. Wherein the data line comprises a first wiring and a second wiring,
The wiring of the driving circuit includes a multilayer wiring formed of the same material as the first wiring, the second wiring, and the gate line.

Further, the present invention provides a liquid crystal panel having a gate line, a data line, a thin film transistor connected to the gate line and the data line, a pixel electrode connected to the thin film transistor, and a driving circuit on a substrate. Forming the gate line and the first drive wiring of the drive circuit with the same material; and forming a first insulating film on the gate line and the first drive wiring, The first
Forming a first data line of the data line and a second drive line of the drive circuit on an insulating film, and forming a second insulating film on the first data line and the second drive line And forming the second data wiring and the third driving wiring of the driving circuit on the second insulating film.

Further, the present invention provides a liquid crystal panel having a gate line, a data line, a thin film transistor connected to the gate line and the data line, a pixel electrode connected to the thin film transistor, and a driving circuit on a substrate. In the above, the wiring of the driving circuit includes the data line, the gate line,
It is characterized by comprising a multilayer wiring composed of the same material as the pixel electrode. Still further, the present invention provides a method of manufacturing a liquid crystal panel having a gate line, a data line, a thin film transistor connected to the gate line and the data line, a pixel electrode connected to the thin film transistor, and a driving circuit on a substrate. Forming a first insulating film on the gate line and the first driving line of the driving circuit; forming a first insulating film on the gate line and the first driving line of the driving circuit; Forming the data line and a second drive wiring of the drive circuit on the first insulating film;
Forming a second insulating film on the data line and the second driving wiring; and forming a pixel electrode and a third driving wiring of the driving circuit on the second insulating film. It is characterized by the following.

[0012]

In the present invention, since the wiring layers of the driving circuit formed on the same transparent substrate as the matrix array have a three-layer wiring structure, the degree of freedom in the arrangement of the wiring layers is large. Accordingly, the pitch between the drive circuit elements can be reduced, so that the drive circuit side can sufficiently cope with miniaturization of the matrix array. The drive circuit has a three-layer wiring structure;
That is, since the step of forming the wiring layer of the driver circuit is performed three times, the first data line or the second data line is formed with the help of the step suitable for forming the data line. Therefore, unlike the manufacturing method in which the first data line and the second data line are formed in individual steps to form the data line in a multiple wiring structure, a data line having a multiple wiring structure, that is, a data line having a redundant wiring structure is formed. , Can be formed with a small number of steps.

[0013]

Next, an embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a plan view showing a part of a matrix array of a liquid crystal display panel with a built-in driver according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line II. Here, portions having the same functions as those of the conventional matrix array shown in FIG. 6 are denoted by the same reference numerals.

In this embodiment, as shown in FIG. 1, vertical data lines 2a, 2b... (Signal lines) and horizontal gate lines 3a, 3b. And each pixel region 1 of the matrix array is arranged between them.
a, 1b... are formed.

Hereinafter, the structure of the pixel region 1a will be described by way of example. In this pixel region 1a, the data line 2
The TFT 8 is formed by the source 4 to which a is conductively connected, the gate 5 to which the gate line 3b is conductively connected, and the drain 7 to which the pixel electrode 6 is conductively connected. Here, the pixel electrode 6 is a transparent electrode made of ITO, and is formed over substantially the entire surface of the pixel region 1a. The data line 2a has a two-layer structure including a lower chromium layer (first data line) and an upper aluminum layer (second data line), while the gate line 3b has an impurity doped layer. It is composed of a polycrystalline silicon layer.

As shown in FIG. 2, the cross-sectional structure of this TFT 8 is such that a polycrystalline silicon layer 10 is formed on the surface side of a transparent substrate 9 (glass substrate) that supports the entire liquid crystal display panel. Except for the channel region 11 which is an intrinsic polycrystalline silicon region, phosphorus as an n-type impurity is introduced into the source 10 and the source 4 and the drain 7.
Are formed. Here, the source 4 and the drain 7 are self-aligned by utilizing ion implantation using the gate 5 on the gate oxide film 12 formed on the surface side of the polycrystalline silicon layer 10 as a mask. It is done to become. A first interlayer insulating film 13 (lower interlayer insulating film) made of a silicon oxide film is deposited on the front side of the TFT 8, and a first connection hole 13 a is formed in the first interlayer insulating film 13.
And the second connection hole 13b are opened. The first data line 14 made of a chromium layer is conductively connected to the source 4 through the first connection hole 13a among them.
The second data line 15 made of an aluminum layer is connected to the first data line 14 through the connection hole 17a of the second interlayer insulating film 17 (upper interlayer insulating film) formed on the surface side. Conductive connection to the surface. The first and second data lines 14 and 15 thus formed constitute a data line 2a, and the data line 2a has a redundant wiring structure having a double structure. On the other hand, the first interlayer insulating film 13
A stacked electrode layer 16 made of a chromium layer is conductively connected through the second connection hole 13b, and a second interlayer insulating film 17 and a third interlayer insulating film 18 The pixel electrode 6 made of ITO is conductively connected to the stacked electrode layer 16 via a connection hole 18a penetrating through the contact hole 18a. Thus, a potential can be applied from the drain 7 to the pixel electrode 6. Here, regarding the connection structure between the pixel electrode 6 and the drain 7, the stacked electrode layer 16 is formed of a metal layer such as a chromium layer,
Alternatively, a structure composed of an ITO layer can be used, and a structure in which the pixel electrode 6 is directly conductively connected to the drain 7 can be employed.

In this liquid crystal display panel, as will be described later, since the data lines 2a are composed of the chromium layer 14 and the aluminum layer 15 formed in a step different from the chromium layer 14, the data lines 2a are disconnected. Even if it is assumed that there is a portion, the data line 2a will not be in a disconnected state unless the positions of the disconnected portions overlap. In other words, since the redundant wiring structure has a relationship in which the disconnection state of one side is complemented by the other side, even if restrictions such as the pixel region 2a being miniaturized and the width of the data line 2a being narrowed are added, the data line 2a is not affected. Since data signals are reliably applied to all the pixel regions to which 2a is connected, display line defects are extremely unlikely to occur in this liquid crystal display panel.

Further, a driving circuit (not shown) for driving the matrix array is provided on the front side of the transparent substrate 9.
Is also formed. The driving circuit is an example of the equivalent circuit as shown in FIG. 5 with an equivalent circuit of the matrix array, for any pixel regions through the data line D _i is a predetermined signal potential to the source of the TFT _ij It can be applied. The gate line G is connected to the gate of the TFT _ij.
The driving potential from _j is applied, and a predetermined signal potential is applied to the liquid crystal display element C _ij constituted by the pixel electrode and the common electrode.
Is applied, a potential is applied to the liquid crystal of the liquid crystal display element C _ij , and the alignment state of the liquid crystal changes to display information.
Here, the data line D _i gate line drive circuit 32 supplies a gate signal to the data line driving circuit 31 and the gate line G _j supplying a data signal, the both are formed in the outer peripheral region of the transparent substrate, its For example, in the data line drive circuit 31, the image signal _Sp is applied to the source of the TFT _i for controlling the line memory 31a, while the vertical synchronization pulse _Sv and the vertical shift pulse _Sv are applied. With the pulses φ ₁ and φ ₂ , each stage of the vertical shift register 31b can be sequentially turned on for the pulse duration from left to right in FIG. Thus, the image signal S _p is sequentially stored in separated by capacitor C _i line memory for each pixel. And
These image signals are transferred to the data lines based on the applied line switch signal S _L to the line switch TFT _Li. On the other hand, the gate drive circuit 32 also has a substantially similar circuit configuration, and a description thereof will be omitted. However, each of the data line drive circuit 31 and the gate drive circuit 32 includes a TFT or the like connected to a predetermined circuit configuration. It is composed of

In this embodiment, each wiring layer for connecting the respective TFTs of the data line driving circuit 31 and the gate line driving circuit 32 is formed on the surface of the transparent substrate 9 as shown in FIG. The first wiring layer 19, the second wiring layer 20 on the first interlayer insulating film 13 (lower interlayer insulating film) formed on the surface side, and the second interlayer insulating film formed on the surface side Third wiring layer 2 on film 17 (upper interlayer insulating film)
1 has a three-layer wiring structure. Therefore, the pitch between these wiring layers 19, 20, 21 electrically connected to the data lines 2a, 2b... Or the gate lines 3a, 3b is narrow. Therefore, even when the pixel region is miniaturized for higher definition of the display screen, the drive circuit side can sufficiently cope with the pitch of the miniaturized pixel region. In addition, since the region for forming the driving circuit itself can be narrowed, the panel size can be reduced.

Here, the first wiring layer 19 is formed of an impurity-doped polycrystalline silicon layer formed simultaneously with the gate 5 and the gate line 3b, and the second wiring layer 20 is formed of the first data line. The third wiring layer 21 is formed of an aluminum layer formed simultaneously with the second data line 15.

A method for manufacturing a matrix array of a liquid crystal display panel having such a structure will be described with reference to FIG.

FIG. 3 is a process sectional view showing a part of a method of manufacturing a liquid crystal panel display.

First, as shown in FIG. 3A, an intrinsic polycrystalline silicon layer 10a is deposited on the surface of a glass substrate 9 by a CVD method, and then thermal oxidation is performed to form a gate oxide film 12. Form.

Next, as shown in FIG. 3 (b), a phosphorus-doped polycrystalline silicon layer is formed on these surface sides by a CVD method, and then patterned to form a gate 5 and a gate line 3.
a, 3b... and the first wiring layer 19 are left. Thereafter, phosphorus is ion-implanted using the gate 5 as a mask to make the source 4 and the drain 7 conductive. Here, an intrinsic polycrystalline silicon portion is left immediately below the gate 5, and this becomes the channel region 11.

After forming the TFT 8 together with the TFT (not shown) on the drive circuit side in this way, as shown in FIG. 3C, the first interlayer is formed on the surface side by a CVD method or the like. An insulating film 13 is deposited. After that, a first connection hole 13a and a second connection hole 13b are formed above the source 4 and the drain 7. Similarly, a connection hole is formed at a predetermined position on the drive circuit side. Next, a chromium layer is deposited on these surface sides by a sputtering method to form a chromium layer on the entire surface, and then, in a state where a resist mask layer having a predetermined region opened in a window is formed, cerium ammonium nitrate or the like is formed. 1st data line 1 by chemically etching the entire chromium layer with an etching solution for chromium containing
4. The second wiring layer 20 and the stacked electrode layer 16 are left.

Next, as shown in FIG. 3D, a second interlayer insulating film 17 is
Is deposited, a connection hole 17a is formed. Also in this case, a connection hole is formed at a predetermined position on the drive circuit side. Further, an aluminum layer is deposited on these surface sides by a sputtering method to form an aluminum layer on the entire surface, and then a resist mask layer in which a predetermined region is opened in a window is formed.
In this state, the entire aluminum layer is chemically etched with an etching solution for aluminum containing phosphoric acid, nitric acid, or the like, so that the second data line 15 and the third wiring layer 21 are etched.
To form

Next, a third interlayer insulating film 18 is deposited on these surfaces by a CVD method or the like.
8a is formed. Then, after depositing the ITO layer by the sputtering method, a resist mask layer having a predetermined area opened on the surface thereof is formed on the surface of the ITO layer, and then the ITO layer is chemically etched with an ITO etching solution containing hydrochloric acid, nitric acid and the like. To leave the pixel electrode layer 6 as shown in FIG.

As described above, in this example, the data line 2
In order to form a double structure, a first data line 14 made of a chromium layer is provided on the lower layer side, and aluminum which can be etched with a phosphoric acid or nitric acid based etchant having no etching ability on the chromium layer is provided on the upper layer side. A second data line 15 composed of layers is employed. Therefore, the resist mask layer for forming the second data line 15 has a defect,
Even if a disconnection occurs in the data line 15 of the
No disconnection occurs in the data line 14.

For this reason, the first and second data lines 1
Unless a disconnection occurs at the same position of the data lines 4 and 15, the data line 2a itself does not become disconnected. Therefore, in the liquid crystal display panel of this example, a display line defect due to the disconnection of the data line 2a hardly occurs. And the first
And the second data lines 14 and 15 are formed of the wiring layers 20 and 21 with the help of the formation process of the second wiring layer 20 and the third wiring layer 21 among the wiring layers constituting the drive circuit.
Is formed at the same time. Further, the steps for forming the gate 5 and the gate lines 3a, 3b,... Are formed simultaneously with the aid of the step for forming the first wiring layer 19. In addition, since all of the interlayer insulating films 13, 17, and 18 are similarly arranged on the drive circuit side and the matrix array side, their formation steps are also used. For this reason, even if a redundant wiring structure is adopted for the data lines 2a, 2b,... Of the liquid crystal display panel, the increase in the number of manufacturing steps is minimized, so that cost responsiveness is also provided. Moreover,
Since the formation area of the data line 2a is not expanded, the aperture ratio is maintained, so that the display quality does not deteriorate.

Embodiment 2 Next, a liquid crystal display panel according to Embodiment 2 of the present invention will be described with reference to FIG.

FIG. 4 is a cross-sectional view of a matrix array of a liquid crystal display panel with a built-in driver according to the second embodiment. Portions having functions common to those of the liquid crystal display panel with a built-in driver according to the first embodiment are described below. With the same sign,
A description thereof will be omitted. The plane of the matrix array has substantially the same configuration as that of FIG.

In the liquid crystal display panel of the present embodiment, a first interlayer insulating film 13 (lower interlayer insulating film) is formed on the front side of the TFT 8 formed on the transparent substrate 9, and a connection hole thereof is provided. A first data line 14 made of a chromium layer is conductively connected to the source 4 of the TFT 8 via 13a. A second data line 15 made of an aluminum layer is directly conductively connected to the front side of the first data line 14, and the second data line 15 is not formed on the interlayer insulating film. . Here, the gate 5 and the gate lines 3a, 3b.
.. Consist of an impurity-doped polycrystalline silicon layer as in the first embodiment.

On the other hand, on the drive circuit side, the first wiring layer 19 is formed of an impurity-doped polycrystalline silicon layer formed simultaneously with the gate 5 and the gate lines 3a, 3b,. First interlayer insulating film 1 formed in
2 is formed of an aluminum layer formed simultaneously with the second data line 15, and the third wiring layer 21 on the second interlayer insulating film 17 formed on the surface side of the second wiring layer 20 is formed.
Is composed of an ITO layer formed simultaneously with the pixel electrode 6. That is, each of the wiring layers 19, 20,... Constituting a driving circuit such as a data line driving circuit and a gate line driving circuit.
The data line 2 has a three-layer wiring structure.
a, 2b... or the pitch between wiring layers for transferring signals to the gate lines 3a, 3b is narrow. Therefore, even when the pixel region is miniaturized for higher definition of the display screen, the driving circuit side can sufficiently cope with the size of the miniaturized pixel region. In addition, since the area for forming the driving circuit is small, the panel size can be reduced.
In this example, the pixel electrode 6 is formed on the second interlayer insulating film 17 and is conductively connected to the stacked electrode layer 16 made of a chromium layer, an ITO layer, or the like via the connection hole 17b. However, instead of this structure, a structure in which the pixel electrode 6 is directly conductively connected to the drain 7 is also possible.

Also in the liquid crystal display panel having such a structure, each of the data lines 2a, 2b,... Has a redundant wiring structure composed of multiple wirings including a first data line 14 and a second data line 15. Therefore, similarly to the first embodiment, even if a disconnection occurs in one of the data lines 2a,
2b... Itself does not break.

In the method of manufacturing the liquid crystal display panel of this embodiment, the step of forming layers using the same material among the steps of forming the wiring layers 19, 20, and 21 on the drive circuit side and the matrix array side is also performed. About each other, a process is called for. That is, the step of forming the first wiring layer 19 using the same impurity-doped polycrystalline silicon and the step of forming the gate 5 and the gate lines 3a, 3b,. The step of forming the line 15 and the step of forming the second wiring layer 20 are the same step, the step of forming the pixel electrode 6 using the same ITO,
The step of forming the third wiring layer 21 is performed as the same step.

As described above, also in the present embodiment, the layers on the matrix array side can be formed with the aid of three of the steps for forming the drive circuit, and the redundant wiring is formed by one of the steps. Second data line 1 constituting the structure
5, the signal lines 2a... Of the redundant wiring structure are provided without unnecessarily increasing the number of manufacturing steps. 2b... Can be formed.

In addition to the combination of the materials used for the liquid crystal display panels according to the first and second embodiments, at least one of the first and second data lines is connected to each wiring layer on the drive circuit side. , The gate 5 and the gate lines 3a, 3a
b. use an impurity-doped polycrystalline silicon layer, a chromium layer for the first data line 14, and an aluminum layer for the second data line 15, and a gate 5 for the first wiring layer 19.
, And a different type of impurity-doped polycrystalline silicon layer from the gate lines 3a, 3b..., And the same type of impurity-doped polycrystalline silicon layer as the gate 5 and the gate lines 3a, 3b. The same aluminum layer as the second data line 15 may be used for the crystalline silicon layer and the third wiring layer 21. In this case, the step of forming the second wiring layer 20 and the step of forming the gate 5 and the gate lines 3a, 3b,.
1 and the step of forming the second data line 15 are performed simultaneously as the same step.

The gate 5 and the gate lines 3a, 3b
.., An impurity-doped polycrystalline silicon layer, an aluminum layer for the first data line 14 and an aluminum layer for the second data line 15, while the gate 5 and the gate line are used for the first wiring layer 19. 3a, 3b,... Are the same kind of impurity-doped polycrystalline silicon layer, the second wiring layer 20
Alternatively, the same aluminum layer as the first data line 14 and the same aluminum layer as the second data line 15 may be used as the third wiring layer 21. In this case, the step of forming the first wiring layer 19, the gate 5, and the gate lines 3a, 3b,.
Forming a second wiring layer 20;
Step of Forming First Data Line 14, Third Wiring Layer 21
And the step of forming the second data line 15 are performed simultaneously as the same step.

Further, also for the first data line, an impurity-doped polycrystalline silicon layer or the like can be used.

The size of the liquid crystal display panel to be manufactured depends on the size of the liquid crystal display panel to be manufactured.
It is a property that should be set to a predetermined condition depending on the use and the like, and is not limited.

[0042]

As described above, in the liquid crystal panel according to the present invention, the matrix array having the data lines of the double wiring structure composed of the first and second data lines on the same transparent substrate, and the three-layer wiring Since a driving circuit having a structure is formed, the following effects can be obtained.

Since the wiring layer of the drive circuit has a three-layer wiring structure, the pitch between the wiring layers can be narrowed.
It can sufficiently cope with miniaturization of the matrix array, and can realize high definition of the liquid crystal panel. Further, the area for forming the driving circuit can be reduced, and the size of the liquid crystal panel can be reduced without reducing the area occupied by the matrix array.

The drive circuit has a three-layer wiring structure,
That is, since the step of forming the wiring layer of the driver circuit is performed three times, the first data line or the second data line is used with the aid of a step suitable for forming a data line having a double wiring structure. Can be formed. Therefore, unlike the manufacturing method in which the first data line and the second data line are formed in individual steps, the data lines having the redundant wiring structure can be formed in a small number of steps.

Since the wiring layer on the driving circuit side and the wiring layer on the matrix array side are formed of the same material, the three-layer wiring structure of the driving circuit and the redundant wiring structure of the data lines can be realized with a minimum number of steps. Can be formed.

[Brief description of the drawings]

FIG. 1 is a plan view showing a part of a matrix array of a liquid crystal display panel with a built-in driver according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line II of FIG.

FIGS. 3A to 3D are process cross-sectional views each showing a part of a process of manufacturing a matrix array of the liquid crystal display panel with a built-in driver according to the first embodiment of the present invention.

FIG. 4 is a sectional view showing a part of a matrix array of a liquid crystal display panel with a built-in driver according to a second embodiment of the present invention.

FIG. 5 is an equivalent circuit diagram schematically showing a matrix array and a driving circuit of a driver-incorporated liquid crystal display panel.

FIG. 6 is a cross-sectional view showing a part of a matrix array of a conventional liquid crystal display panel with a built-in driver.

[Explanation of symbols]

 1a, 1b: Pixel region 2a, 2b: Data line 3a, 3b: Gate line 4: Source 5, Gate 6: Pixel electrode 7, Drain 8, TFT 13 first interlayer insulating film (lower interlayer insulating film) 14 first data line 15 second data line 17 second interlayer insulating film (upper interlayer insulating film) 19) First wiring layer 20 ... Second wiring layer 21 ... Third wiring layer

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G02F 1/1368

Claims (4)

(57) [Claims] A gate line, a data line, a thin film transistor connected to the gate line and the data line on a substrate,
In a liquid crystal panel having a pixel electrode connected to the thin film transistor and a driving circuit, the data line includes a first wiring and a second wiring, and the wiring of the driving circuit includes the first wiring and the second wiring. A liquid crystal panel comprising a wiring and a multilayer wiring formed of the same material as the gate line. 2. A gate line, a data line, a thin film transistor connected to the gate line and the data line on a substrate,
In a method for manufacturing a liquid crystal panel having a pixel electrode connected to the thin film transistor and a driving circuit, a step of forming the gate line and a first driving wiring of the driving circuit with the same material; Forming a first insulating film on one drive wiring; forming a first data wiring of the data line and a second drive wiring of the drive circuit on the first insulating film; Forming a second insulating film on the first data wiring and the second driving wiring; and forming the second data wiring and the third driving wiring of the driving circuit on the second insulating film. And a method for manufacturing a liquid crystal panel. 3. A gate line, a data line, a thin film transistor connected to the gate line and the data line on a substrate,
In a liquid crystal panel including a pixel electrode connected to the thin film transistor and a driving circuit, a wiring of the driving circuit includes the data line, the gate line, and a multilayer wiring formed of the same material as the pixel electrode. A liquid crystal panel characterized by the above-mentioned. 4. A gate line, a data line, a thin film transistor connected to the gate line and the data line on a substrate,
In a method for manufacturing a liquid crystal panel having a pixel electrode connected to the thin film transistor and a driving circuit, a step of forming the gate line and a first driving wiring of the driving circuit with the same material; Forming a first insulating film on a first drive wiring of a circuit; forming the data line and a second drive wiring of the drive circuit on the first insulating film; Forming a second insulating film on a line and the second driving wiring; and forming a pixel electrode and a third driving wiring of the driving circuit on the second insulating film. Characteristic liquid crystal panel manufacturing method.