JP2003076298A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase a degree of integration of a circuit by allowing degrees-of- freedom for a writing pattern design of display part peripheral circuits. SOLUTION: Each output of load latches LLA (L-LA1-L-LLA6) is connected with each signal input of load latches LLB (L-LB1-L-LLB6) via metallic wiring, and also connected with each signal input of a D-A converter via ITO wiring 17. The ITO wiring 17 is of the same material as pixel electrodes 4 of the display part 32, and is formed at the same time when the pixel electrodes 4 are formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit for a display device, and more particularly to a wiring pattern configuration of the drive circuit.

[0002]

2. Description of the Related Art A thin film transistor (TF) is provided for each pixel electrode.
The active matrix type liquid crystal display device in which the pixel switching element composed of T) is arranged has a clear image quality and has a high-density display performance higher than that of a CRT, and is widely used in information equipment terminals, thin-screen televisions and the like. ing.
Usually, amorphous silicon or polycrystalline silicon is used for the semiconductor active layer (channel region) of the TFT.

Particularly in recent years, in order to expand the effective screen area on the insulating substrate having the same area and to reduce the manufacturing cost, the peripheral circuits of the display section such as the scanning line driving circuit and the video signal line driving circuit are provided as pixel TFTs. At the same time, development of a TFT-LCD with a built-in drive circuit, which is integrally formed on a transparent insulating substrate such as glass, is in progress.

[0004]

In general, the wiring of the peripheral circuit of the display portion such as the driving circuit is formed by wiring patterns which are located above and below via an interlayer insulating film or the like. The upper and lower wiring patterns are connected by a contact hole (Via pattern). The wiring pattern is formed from one electrode to the other electrode through a contact hole if necessary, avoiding other wiring patterns or circuit elements. Therefore, there are many restrictions on the design of the wiring pattern, and the more the circuit configuration is complicated, the more the area occupied by the wiring pattern increases.

Therefore, it is an object of the present invention to provide a degree of freedom in designing a wiring pattern of a peripheral circuit of a display section and increase the degree of integration of the circuit.

[0006]

A display device according to the present invention includes a plurality of video signal lines, a plurality of scanning lines orthogonal to the video signal lines, and a pixel switching thin film transistor provided near an intersection of the video signal lines and the scanning lines. And a display section in which a pixel electrode electrically connected to a source electrode of the thin film transistor is provided on a transparent insulating substrate, and a scanning line driving circuit provided on the insulating substrate and driving the plurality of scanning lines. And a video signal line drive circuit which is provided on the insulating substrate and drives the video signal line, wherein at least a part of a wiring pattern of the video signal line drive circuit or the scanning line drive circuit is the pixel electrode. It is composed of the same layer.

Since the same transparent conductive film wiring as the pixel electrode is used as the wiring pattern of the driving circuit in addition to the conventional metal wiring, the wiring pattern structure becomes simpler than the conventional one. In addition, the degree of freedom in designing the wiring pattern is increased, and the degree of integration of the display peripheral circuit can be increased. Since the wiring pattern of the transparent conductive film is formed when the pixel electrode of the display section is formed, the manufacturing process does not increase.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a schematic structure of an active matrix type liquid crystal display device incorporating a drive circuit to which the present invention is applied. This liquid crystal display device has a transparent insulating substrate 3 such as glass.
1 includes at least the display unit 32, the scanning line driving circuit 33, and the video signal line driving circuit 34.

In the display section 32, a pixel switching element (TFT) 3 is provided near an intersection of a plurality of video signal lines 1 and a plurality of scanning lines 2 orthogonal to the video signal lines 1. The pixel electrode 4 is connected to the source electrode of the pixel switching element 3, and the liquid crystal capacitance Clc and the auxiliary capacitance Cs are connected to the pixel electrode 4 to form the display pixel 5. Then, such display pixels 5 are provided in a matrix on the insulating substrate.

The scanning line driving circuit 33 is composed of a shift register and a scanning line driving buffer (not shown), and the output of each buffer is connected to each scanning line 2. The scanning line drive circuit 33 as described above is provided with the basic clock CLK2.
And the trigger signal IN2 are input.

The video signal line drive circuit 34 includes, for example, a shift register, a sampling latch, a load latch, a DA.
C, an analog amplifier, and a signal line selection circuit. Then, the basic clock CLK1, the trigger signal IN1, and the digital video signal DATA are input to the video signal line drive circuit 34.

2 (a) and 2 (b) show the display unit 3 of FIG.
2 is a plan view and a sectional view of FIG. The same components as those in FIG. 1 are designated by the same reference numerals.

A plurality of signal lines 1 and scanning lines 2 are formed in a matrix on the insulating substrate 31, and the signal lines 1 and the scanning lines 2 are formed.
A thin film transistor T whose one end is connected to the signal line 1 and a part of the scanning line 2 is used as a gate electrode at the intersection with
The switch element 3 of FT is formed. As the switch element 3, a thin film transistor TFT having an active layer made of polycrystalline silicon is used. The video signal is supplied from the signal line 1, reaches the thin film transistor through the contact hole 44, and further reaches the pixel electrode 4 made of a transparent conductive film (ITO) through the contact hole 45. In FIG. 2B, the signal line 1 is located above the contact hole 44.

Then, a liquid crystal 51 is enclosed between the counter electrode 50 formed on the insulating substrate 49 facing the insulating substrate 31 and the pixel electrode 4 to form a liquid crystal cell, whereby a liquid crystal capacitance Cls is formed. ing.

A part 46 of the scanning line 2 faces the pixel electrode 4 via the interlayer insulating film 53 to form an auxiliary capacitance Cs.
Part of the pixel electrode 4 overlaps with the signal line 1 and the scanning line 2, and the light transmitted from the part other than the pixel electrode is blocked by the signal line 1 and the scanning line 2. Below the pixel electrode 4,
Red, green, and blue color filters 47R, 47G, 47B
Is provided to enable color display. The gate insulating film 52 is made of SiO2.

FIG. 3 is a block diagram showing a detailed structure of the video signal line drive circuit 34 of this embodiment. The video signal line drive circuit 34 is composed of circuit groups G1 to Gn having the same configuration. Each circuit group has a shift register (S-Reg
Sister) SR, sampling latch (S-Latch) SL, load latch (L-latch A) LLA, load latch (L-latch B)
LLB, D / A converters (DAC) 24 and 25, analog amplifiers (Amp) 26 and 27, and a signal line selection circuit (S) that distributes image signals corresponding to three signal lines, respectively.
el) 28, 29.

That is, according to this embodiment, six signal lines correspond to one shift register SR block. FIG. 4 shows the sampling latch SL and the load latch LL.
It is a block diagram which shows the detail of A and LLB. Hereinafter, the case where the video data DATA is 6 bits will be described. 1
The sampling latch SL of the circuit has six 1-bit sampling latches (S) for latching each bit data.
-L1 to S-L6), and each circuit includes a data bus 30
Connected to each data line above. Load latch LLA, L
The LB also has 6 circuits (L-LA1 to L-LA6, L-LA) each having 1-bit load latch to latch each bit data.
LB1 to L-B6) are provided.

FIG. 5 is a time chart showing the operation of the video signal line drive circuit 34. S shown in this time chart
A signal having a reference numeral such as R1 indicates that it is a signal output from a block having the same reference numeral in FIG.

6-bit video data Data1a, Data2a, ..., Data (n) on the data bus 30 in synchronization with the clock signal CLK (corresponding to CLK1 in FIG. 1).
-1) a, Data na, Data1b, Data2
b, ..., Data nb, Data1c, Data2
c, ..., Data nc, Data1d, Data2
d, ..., Data and Data1e, Data2
e, ..., Data ne, Data1f, Data2
, f, ..., Data nf are sequentially input during one horizontal scanning period (H). This n is the number n of the circuit group G
Corresponding to. From each shift register SR1 to SRn,
The latch pulse is output in a cycle of (n × CLK cycle) + (Blanking) period. In the case of this example, since one shift register SR is associated with six signal lines, a period which is 6 times (the number of output signals of the signal line selection circuits 28 and 29) times the period of the latch pulse is one horizontal scanning period (H ) Corresponds to. That is, the cycle of the latch pulse is H / 6.

In response to the latch pulse output from each shift register SR, each sampling latch SL1 to S
Ln latches the data on the data bus 30.

In response to the load pulse A (Load A), the load latches LLA1 to LLAn simultaneously latch the outputs of the sampling latches SL1 to SLn. In response to the load pulse B (Load B), the load latches LLB1 to LLBn are connected to the load latches LLA1 to LLA.
Latch the outputs of n at the same time.

After each of the load latches LLB1 to LLBn latches the data, the load latches LLA1 to LLAn latch the next data Data1b to Datanb in response to the load pulse A (Load A). At this point, the data of the load latches LLA1 to LLAn and the load latches LLB1 to LLBn are confirmed (updated), and D /
D / A conversion is performed by the A converters 24 and 23.

The video signal converted into an analog signal is amplified by amplifiers 26 and 27 and selected by signal line selection circuits 28 and 29. For example, signal lines 28a and 29a.
Is output to.

As described above, 1 / (1) of one horizontal scanning period (H)
The video data DATA is latched every 6 cycles (H / 6), and 2/6 cycles (2H / 6) of one horizontal scanning cycle (H)
The video signal D / A converted for each is selected by the signal line selection circuits 28 and 29, and the signal lines 28a to 28c and 29a are selected.
To 29c.

FIG. 6A is a diagram showing the configuration of the 1-bit load latch L-LA shown in FIG. The 1-bit load latch is a clocked inverter 35, 36, an inverter 37,
38. In the case of load latch L-LA,
The signal LoadA is input to the clocked inverters 35 and 36 as the CLK input. 1-bit load latch L
The configuration of -LB is the same as that of the 1-bit load latch L-LA, and the signal LoadB is input as the CLK input.

FIG. 6B shows the detailed structure of the clocked inverter 35. The clocked inverter 35 includes Pch transistors T1 and T2 and Nch transistors T3 and T4.
Composed of. The clocked inverter 35 latches the input data at the trailing edge of the clock signals (CLK and / CLK). The 1-bit data provided from the 1-bit sample latch SL is input to the gates of the Pch transistor T2 and the Nch transistor T3. The LoadA signal is input as the CLK input to the gate of the Pch transistor T1, and / Load is input to the Nch transistor T4.
An A signal (a reverse phase signal of LoadA) is input. The clocked inverter 36 has the same configuration as the clocked inverter 35, but the CLK inputs are input in opposite phases.

FIG. 7 is a diagram showing a conventional wiring pattern of the load latch circuit section 20 of FIG. A wiring pattern with a low concentration shown by hatching shows a wiring pattern of a lower layer (on the side of the insulating substrate 31), which is, for example, a molybdenum-tungsten alloy (Mo / W) wiring, and is formed in the same layer as the gate electrode of the transistor and the scanning line 2. Has been done. The wiring pattern having a high density indicates an upper wiring pattern which is arranged with respect to the lower wiring pattern via an interlayer insulating film or the like, and is, for example, an aluminum (Al) wiring and is formed in the same layer as the signal line 1. .

In each 1-bit load latch L-LA, a drain wiring 7a, a source wiring 9a, and an output signal wiring 10a are provided in the upper layer as power supply wiring. In addition, the signal line (gate line) is connected to the load latch circuit L-LA.
8a and CLK (Load A) input wiring 6a are provided in a lower layer with respect to the wirings 7a, 9a, and 10a via an interlayer insulating film.

Each 1-bit load latch circuit L-LB has a drain wire 7b and a source wire 9b as power supply wires,
The output signal wiring 10b and the CLK (LoadB) input wiring 6b are provided in the upper layer. The wiring 10b is connected to the wiring 12b in the lower layer through the contact hole 11b,
The wiring 12b is connected to the signal input of the DAC at the next stage. Further, the load latch circuit L-LB includes a signal input wiring 8b and a CLK (LoadB) input wiring 6c, a wiring 7b,
9b and 10b are provided in a lower layer via an interlayer insulating film.

The wiring 12a is connected to the wiring 8b in the lower layer. The wiring 12a is connected to the upper wiring 14 through the contact hole 13, and the wiring 14 is lower wiring 16 through the gate wiring / source wiring contact hole 15.
And the wiring 16 is connected to the signal input of the DAC in the next stage.

FIG. 8 is a diagram showing a wiring pattern of the load latch circuit section 20 of FIG. 4 according to an embodiment of the present invention.

Load latch LLA (L-LA1 to L-L
The wiring pattern for A6) has the same configuration as that of the conventional example of FIG. 7, except that the load latches LLB (L-LB1 to L-L) are used.
An ITO (transparent conductive film) wiring 17 formed in the same layer as the pixel electrode 4 is used as a wiring pattern for B6),
As a result, the circuit width W has been significantly reduced compared to the conventional one. I
The TO wiring 17 is made of the same material as the pixel electrode as described above,
It is formed at the same time when the pixel electrode 4 of ITO is formed on the display unit 32 shown in FIG. Here, since the light transmission type liquid crystal display device is taken as an example, the wiring pattern is made of ITO, but in the reflection type liquid crystal display device or the organic EL display device, a low resistance metal such as aluminum (Al) is used. The waveform distortion due to the wiring resistance is further reduced. In each 1-bit load latch circuit L-LA, a drain wiring 7a and a source wiring 9a and an output signal wiring 10a are provided in the upper layer as power supply wirings as in FIG. 8, and an input signal wiring 8a and CLK (LoadA)
The input wiring 6a is provided in the lower layer.

Each 1-bit load latch circuit L-LB has a drain wire 7b and a source wire 9b as power supply wires,
And the output signal wiring 10b is provided in the upper layer. In addition, the load latch circuit L-LB has input signal wirings 8b and C.
The LK (LoadB) input wiring 6d is connected to the wirings 7b and 9
b and 10b are provided as a lower layer via an interlayer insulating film.

The wiring 12a is connected to the wiring 8b in the lower layer. The wiring 12a is connected to the uppermost ITO wiring 17 through the source wiring / ITO wiring contact hole 18, and the ITO wiring 17 is connected to the signal input of the DAC in the next stage. The ITO wiring 17 is provided further above the power wiring 7b, 9b and the like via an interlayer insulating film. Since the ITO wiring has a larger electric resistance than the Al or Mo / W wiring, the signal quality may deteriorate when transmitting the signal. Therefore, the ITO wiring is preferably used when transmitting a binary signal.

In the above embodiment, the ITO wiring 17 was used as a wiring pattern between the load latch circuit block and the DAC circuit block. However, it is obvious that the ITO wiring can be used not only for the wiring between the circuit blocks but also for the wiring inside the circuit block. Further, although the ITO wiring is used for the wiring of the signal line driving circuit in the above-mentioned embodiment, it is obvious that the ITO wiring can also be used for the scanning line driving circuit or other circuits. Further, in the present invention, various wiring materials can be used instead of ITO as described above, depending on the configuration of the display device. As described above, according to the present invention, the wiring pattern between circuit blocks or the wiring pattern within the circuit block is formed in the same layer as the pixel electrode, so that unnecessary wiring patterns are alleviated and the circuit width is reduced as compared with the conventional one. . As a result, the degree of freedom in designing the wiring pattern is increased, and the degree of integration of the display peripheral circuit can be increased.

[0037]

According to the present invention, the degree of integration of the display peripheral circuit can be increased.

[Brief description of drawings]

FIG. 1 is a TFT-LC with a built-in drive circuit to which the present invention is applied.
The figure which shows schematic structure of D.

2A and 2B are a plan view and a cross-sectional view of the display unit of FIG.

FIG. 3 is a block diagram showing a detailed configuration of a video signal line drive circuit.

FIG. 4 is a block diagram showing a detailed configuration of a sampling latch and a load latch.

FIG. 5 is a time chart showing the operation of the video signal line drive circuit.

FIG. 6 is a circuit diagram showing a configuration of the 1-bit load latch of FIG.

FIG. 7 is a view showing a conventional wiring pattern of the load latch circuit section of FIG.

8 is a diagram showing a wiring pattern of the load latch circuit portion of FIG. 4 according to an embodiment of the present invention.

[Explanation of symbols]

1 ... Signal line, 2 ... Scan line, 3 ... Thin film transistor, 4 ...
Pixel electrodes, 5 ... Display pixels, 8 to 10, 12, 14, 1
6, 17 ... Wiring pattern, 11, 13, 15 ... Contact hole, 24, 25 ... D / A converter, 26, 27
... Analog amplifier, 28, 29 ... Signal line selection circuit, SR
1-SRn ... Shift register, SL1-SLn ... Sampling latch, LLA1-LLAn, LLB1-LLB
n ... load latch, S-L1 to S-L6 ... 1-bit sampling latch, L-LA1 to L-LA6, L-LB1
~ L-LBn ... 1-bit load latch.

─────────────────────────────────────────────────── ─── Continued Front Page (51) Int.Cl. ⁷ Identification Code FI Theme Coat (Reference) G09G 3/20 621 G09G 3/20 621M 5F033 680 680G 5F110 3/36 3/36 H01L 21/3205 H01L 29 / 78 612C 29/786 21/88 BF Term (reference) 2H092 GA59 JA25 JA29 JA38 JA42 JB13 JB38 JB51 JB58 JB63 MA05 NA27 NA29 PA06 2H093 NC22 NC23 NC24 NC26 NC34 ND42 ND43 ND52 NE03 NE07 5C006 AA22 BF52 BB16BF20 BF16 BB16BF20 AA10 BB05 DD25 FF11 JJ02 JJ04 JJ06 5C094 AA15 AA43 BA03 BA43 CA19 EA04 EA07 5F033 GG04 HH08 HH22 HH38 KK22 RR04 VV06 5F110 AA04 BB02 CC02 DD02 EE04 EE06 FF02 GG02 NN72HL0303

Claims (4)

[Claims] 1. A plurality of video signal lines and a plurality of scanning lines orthogonal thereto, a pixel switching thin film transistor provided near an intersection of the video signal lines and the scanning lines, and a source electrode of the thin film transistor electrically. A display unit in which a pixel electrode to be connected is provided on an insulating substrate, a scanning line drive circuit provided on the insulating substrate and driving the plurality of scanning lines, and provided on the insulating substrate, the image A video signal line driving circuit for driving a signal line, wherein at least a part of a wiring pattern of the video signal line driving circuit or the scanning line driving circuit is formed in the same layer as the pixel electrode. Display device. 2. The wiring pattern of the video signal line driving circuit or the scanning line driving circuit comprises a first metal pattern provided at a first level with respect to the insulating substrate, and an interlayer insulating film formed from the first metal pattern. A second metal pattern provided at a second level above the film via a film, and a third metal pattern formed in the same layer as the pixel electrode provided above the second metal pattern via an interlayer insulating film. The display device according to claim 1, further comprising: 3. The video signal line drive circuit is composed of a plurality of circuit blocks, and the first wiring is provided in the circuit block.
The display device according to claim 2, wherein a second metal pattern is used, and the transparent conductive film pattern is used for wiring between circuit blocks. 4. The display device according to claim 1, wherein the signal transmitted by the transparent conductive film pattern is a binary signal.