JPH021135A - Vertical mos field-effect transistor - Google Patents

Abstract

PURPOSE:To prevent a short circuit between a gate electrode and a drain region by forming the gate electrode only on a gate oxide film. CONSTITUTION:A gate electrode 7 is structured in such a way that it is formed only on a flat gate oxide film 6; the gate electrode 7 is not formed in a boundary part, between a thick field oxide film 11 and the thin gate oxide film 6, where a pinhole and a defect of the oxide film are apt to cause; accordingly, an inconvenient situation such as a short circuit between the gate electrode 7 and silicon is not caused. Thereby, it is possible to prevent a short circuit between the gate electrode 6 and a drain region 3.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a vertical MO8 field effect transistor (hereinafter referred to as vertical MOSFET) used in switching equipment and the like.

Conventional technology Vertical MO8FETs are fast, have a wide safe operating range, and can easily handle high withstand voltages and large currents, and are used in a wide range of fields, including switching power supplies, especially as power switching elements. .

A conventional vertical MO8FET has a cross-sectional structure as shown in FIG. A detailed explanation will be given below assuming that the illustrated vertical MO8FET is an n-channel type.

In this vertical MO8FET, the region 1 is an active region and operates as an actual FET. Further, a portion 2 is a field oxide film region located at the end of the active region 1, specifically a gate or drain wire bonding region, or a field oxide film region at the chip periphery.

In this vertical MO8FET, a channel region 4 made of a P-type diffusion region is formed in a low impurity concentration n-type silicon semiconductor substrate that becomes a drain region 3, and an n-type source region 5 is formed in this channel region. At the same time, a gate oxide film 6 is formed on the surfaces of the channel region 4 and the drain region 3, a gate electrode 7 is further formed on the gate oxide film 6, and a source electrode 7 is formed over the source region 5 and the channel forming region 4. An electrode 8 is formed, an interlayer insulating film 9 is formed between the source electrode 8 and the gate electrode 7,
This structure has a drain electrode 10 formed on the back surface of a silicon semiconductor substrate.

Note that the field oxide film region 2 at the end of the vertical MO8FET
A field oxide film 11 that is several times to ten times thicker than the gate oxide film 6 is formed in order to absorb bonding damage during wire bonding or to stabilize breakdown voltage between the drain and source. Furthermore, the gate electrode 7 is partially extended on this thick field oxide film 11,
It has a structure in which a bonding pad electrode for a gate electrode is formed.

In a vertical MOSFET with this structure, a channel is formed at the interface between the channel region 4 and the gate oxide film 6, and electrons flow from the source region 5 through the channel to the drain region 3, and then move vertically through the drain region 3 to the drain electrode 10. flows towards.

Problems to be Solved by the Invention In this structure, pinholes may occur at the boundary portion 12 between the gate oxide film 6 and the thick field oxide film 11.
Since the oxide film thickness becomes thinner, there are problems in that a short circuit occurs between the gate electrode 6 and the drain region 3 above this boundary portion 12, and the dielectric strength voltage between the gate and the drain decreases.

Means for Solving the Problems The vertical MOSFET of the present invention eliminates the above-mentioned problems, and only the part on the flat gate oxide film with no step difference between the gate oxide film and the field oxide film is provided. It has a structure in which a gate electrode is formed.

Effect: According to this structure, the gate electrode is not formed on the boundary between oxide films with different oxide film thicknesses, where defects are likely to occur. Problems such as short-circuiting of the semiconductor substrate and reduction in dielectric strength voltage do not occur.

Embodiment An embodiment of the vertical MO8FET of the present invention will be described with reference to the cross-sectional structure of the n-channel vertical MO8FET shown in FIG.

The names of the parts of this vertical MO8FET and the principle of operation of the FET are the same as those of the conventional example shown in FIG.

Here, the gate electrode 7 of the vertical MOSFET of the present invention has a structure in which it is formed only on the flat gate oxide film 6, and the gate electrode 7 is formed only on the flat gate oxide film 6. Since no gate electrode is formed at the boundary of the thin gate oxide film 6, problems such as short circuit between the gate electrode and silicon do not occur. Note that a bonding pad electrode and a wiring layer connected to the gate electrode are formed on the field oxide film 11 through a contact hole formed in the interlayer insulating film 9.

According to the vertical MO8FET of the present invention, since the gate electrode is formed only on the gate oxide film which is uniform and has few defects, the short-circuit failure between the gate and the silicon substrate and the rate of decrease in the dielectric strength are greatly reduced. .

Figure 3 shows the conventional and inventive vertical MO8FETs.
This is a comparison of the short-circuit failure rate between the gate electrode and the silicon substrate with respect to the gate oxide film thickness. From this, when the gate oxide film thickness is 1100 nm or less, the difference in short-circuit failure rate becomes more noticeable as the film thickness becomes thinner. In particular, for a film thickness of about 50 nm, which has recently attracted attention, the difference is more than 50%.

FIG. 4 compares the gate oxide film thickness and the dielectric breakdown voltage of the conventional vertical MO8FET and the present invention. From this, in the case of the conventional structure, the gate oxide film thickness is 1100nm.
As the thickness becomes thinner, the withstand voltage decreases in many cases, and the variation thereof also increases. However, in the case of the present invention, the variation in breakdown voltage is very small (the breakdown voltage determined by the original oxide film thickness is stably obtained).

Effects of the Invention According to the vertical MOSFET of the present invention, since the gate electrode is formed only on the gate oxide film, short circuits between the gate electrode and the drain region can be eliminated and the gate dielectric breakdown voltage can be increased.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional structural diagram showing an embodiment of the vertical MO8FET of the present invention, Fig. 2 is a cross-sectional structural diagram showing a conventional vertical MO8FET, and Fig. 3 is a diagram showing the gap between the gate electrode and the silicon substrate with respect to the gate oxide film thickness. Graph showing the relationship between short defect rate,
FIG. 4 is a graph comparing the relationship between gate oxide film thickness and its dielectric strength voltage. 1... Active region of vertical MOSFET, 2...
...Field oxide film region, 3...Drain region, 4...Channel region, 5...
Source region, 6... Gate oxide film, 7...
...Gate electrode, 8...Source electrode, 9...
...Interlayer insulating film, 10...Drain electrode, 1
1...Field oxide film, 12...Boundary portion between gate oxide film and field oxide film. Name of agent: Patent attorney Toshio Nakao and 1 other person 0

Claims (1)

[Claims] A channel region of a conductivity type opposite to that of the semiconductor substrate is formed on a semiconductor substrate of one conductivity type that becomes a drain region, a source region of one conductivity type is formed in the channel region, and the channel region and the drain region are formed. A uniform gate insulating film is formed thereon, a gate electrode is formed only on the gate insulating film, an interlayer insulating film is formed on the gate electrode, and the gate electrode and the contact hole are formed on the interlayer insulating film. A vertical MOS field effect transistor characterized in that a gate wiring layer is formed connected through the semiconductor substrate, a drain electrode is formed on the back surface of the semiconductor substrate, and a source electrode is formed spanning the source region and the channel region.