JPS59189675A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS59189675A JPS59189675A JP58064118A JP6411883A JPS59189675A JP S59189675 A JPS59189675 A JP S59189675A JP 58064118 A JP58064118 A JP 58064118A JP 6411883 A JP6411883 A JP 6411883A JP S59189675 A JPS59189675 A JP S59189675A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- diffusion layer
- diffused layer
- voltage
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 238000009792 diffusion process Methods 0.000 claims abstract description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 230000006378 damage Effects 0.000 abstract description 13
- 230000002159 abnormal effect Effects 0.000 abstract description 11
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 230000005611 electricity Effects 0.000 description 4
- 230000003068 static effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 230000002265 prevention Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Protection Of Static Devices (AREA)
- Amplifiers (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は静電気等の異常電圧による端子の破壊防止回路
を有するＭより半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device having a terminal destruction prevention circuit due to abnormal voltage such as static electricity.
一般にＭ工Ｓ半導体装置において、異常電圧による入力
端子の破壊は、ゲート酸化膜の絶縁破壊でちる裏が知ら
れており−、こｎに対しては、従来より入力端子からゲ
ート電極に至るまでの間に抵抗手段を挿入して破壊を防
止する対策が打たｎてきている。しかし、出力端子やア
ナログスイッチの入出力端子の破壊は、ドレイン拡散層
と基板の ・間での接合破壊である場合が多い、
こしは、第１図に示す様に通常のＭ工Ｓ半導体装置にお
いて、出力端子１と基板８の電位を与える電源端子９と
の間に異常電圧が加わると、前記出力端子１に接続さｎ
ているドレイ／拡散層３と前記電源端子９に接続さｎて
いる前記基板５の間の接合が過電流゛により熱破壊をお
こす為である。また第２図に示す様なアナログスイッチ
に対しても、同様に入出力端子２に接続さｎているドレ
イン拡散層３と電源端子９に接続さｎている基板８との
間の接合が破壊さ！しる場合が多い。こｎらに対しては
六方端子の破壊防止回路の様に、単に端子とＭ工Ｓ半導
体素子との間に抵抗手段を挿入するのは、半導体装置の
出力電流やオン抵抗等の電気的特性に対し不利に働くの
で好ましくない。従って、従来は、特に破壊防止の為の
対策を打たない場合が多く、異常電圧等に対して比較的
弱いという欠点があった。 □
この発明は、上記の欠点を除去する為になさｎたもので
入出力端子に対する電気的特性を不利にすることなしに
、静電気等の異常電圧による破壊に対し強い入出力端子
を持った半導体装置を提供することを目的とする。In general, in M/S semiconductor devices, it is known that damage to input terminals due to abnormal voltage is caused by dielectric breakdown of the gate oxide film. Countermeasures have been taken to prevent destruction by inserting resistance means between them. However, destruction of output terminals and input/output terminals of analog switches is often caused by junction breakdown between the drain diffusion layer and the substrate.
As shown in FIG. 1, in a normal M/S semiconductor device, when an abnormal voltage is applied between the output terminal 1 and the power supply terminal 9 that provides the potential of the substrate 8, the connection to the output terminal 1 occurs.
This is because the junction between the drain/diffusion layer 3 connected to the power supply terminal 9 and the substrate 5 connected to the power supply terminal 9 is thermally destroyed by an overcurrent. Similarly, for an analog switch as shown in FIG. 2, the bond between the drain diffusion layer 3 connected to the input/output terminal 2 and the substrate 8 connected to the power supply terminal 9 is destroyed. difference! Often. For these, simply inserting a resistance means between the terminal and the M/S semiconductor element, as in the case of a destruction prevention circuit for a hexagonal terminal, is not a good idea because of the electrical characteristics such as the output current and on-resistance of the semiconductor device. This is not desirable as it works against the user. Therefore, in the past, there were many cases in which no special measures were taken to prevent destruction, and they had the disadvantage of being relatively vulnerable to abnormal voltages and the like. □ This invention was made to eliminate the above-mentioned drawbacks, and is a semiconductor having input/output terminals that are resistant to destruction by abnormal voltages such as static electricity, without making the electrical characteristics of the input/output terminals disadvantageous. The purpose is to provide equipment.
以下、本発明の実施例を図面にもとづいて詳細に説明す
る。Hereinafter, embodiments of the present invention will be described in detail based on the drawings.
第３図は本発明の第１の実施例で、基板８に拡散により
形成さｎた前記基板８とは逆の導電型のドレイン拡散層
３とソース拡散層７を有し、前記ドレイン拡散層３に接
続さした出力端子１及び前記基板８から抵抗手段１０ヲ
介して接続さｎるとともに、前記ソース拡散層７に接続
さｎた電源端子９を有し゛ている。また、前記ドレイン
拡散層３と前記ソース拡散層７の間には、ゲート酸化膜
５を介してゲート電極３が配しである。FIG. 3 shows a first embodiment of the present invention, which has a drain diffusion layer 3 and a source diffusion layer 7 of a conductivity type opposite to that of the substrate 8, which are formed by diffusion on a substrate 8. 3 and a power supply terminal 9 connected to the substrate 8 via a resistor means 10 and to the source diffusion layer 7. Further, a gate electrode 3 is arranged between the drain diffusion layer 3 and the source diffusion layer 7 with a gate oxide film 5 interposed therebetween.
前記出力端子１と前記電源端子９とにそ几ぞｎ接゛続さ
ｎている前記ドレイン拡散層３と前記基板８との接合に
対して、逆方向となる様な異常電圧が、静電気等の原因
で加えらｎた場合、前記ドレイン拡散層３と前記基板８
の接合耐圧に達すると電流が流ｎ始めるが、大きな電流
が流ｔようとす扛ば、前記電源端子９と前記基板８との
間に挿入さ′ｎた前記抵抗手段１０によって電圧降下を
米たし接合に加わる電圧は下がり、電流は制限さｎる。An abnormal voltage that is in the opposite direction to the junction between the drain diffusion layer 3 and the substrate 8, which are connected to the output terminal 1 and the power supply terminal 9, may be caused by static electricity, etc. If the drain diffusion layer 3 and the substrate 8
When the junction breakdown voltage is reached, a current begins to flow, but if a large current tries to flow, the voltage drop is reduced by the resistor 10 inserted between the power supply terminal 9 and the substrate 8. However, the voltage applied to the junction is reduced and the current is limited.
従って、接合を破壊する様な電流は流しない事になる。Therefore, no current will flow that would destroy the junction.
この様に前記抵抗手段１０を挿入する事により前記ドレ
イン拡散層３と前記基板８の接合の破壊は防止さｎる。By inserting the resistor means 10 in this manner, destruction of the bond between the drain diffusion layer 3 and the substrate 8 can be prevented.
また、前記出力端子１と前記電源端子９とに、そ几ぞｎ
接続さしている前記ドレイ／拡散層３と前記基板８の接
合に対して順方間となる様な異常電圧が刀ａえらｎた場
合は、一般に逆方向の場合と比較して破壊を起こしにく
い事が知らしているが、この場合にも、前記抵抗手段１
０は電圧降下により電流を制限するのでさらに破壊しに
くくする事ができる。Further, there is a connection between the output terminal 1 and the power supply terminal 9.
If an abnormal voltage is applied in the forward direction to the bond between the connected drain/diffusion layer 3 and the substrate 8, it is generally less likely to cause damage compared to a case in the reverse direction. However, in this case as well, the resistance means 1
0 limits the current by voltage drop, making it even more difficult to break down.
一方この半導体装置の動作時には、電流は前記出力端子
１より前記ドレイン拡散層３ｆｔ通９チャネル層６を通
って前記ソース拡散層７から前記電源端子９へという経
路をたどって流肚る。従って、前記抵抗手段１０がこの
動作時の電流を防げる事はない。On the other hand, during operation of this semiconductor device, a current flows from the output terminal 1 through the drain diffusion layer 3 ft, through the 9 channel layer 6, and from the source diffusion layer 7 to the power supply terminal 9. Therefore, the resistor means 10 cannot prevent current flow during this operation.
また、第４図は本発明の第２の実施例であり、アナログ
スイッチに用いた場合を示したもので第１の実施例の場
合と比べ電源端子９がソース拡散層には接続さｎず基板
８に接続さ几ているが効果は、第１の実施例と同様に説
明することができるものである。FIG. 4 shows a second embodiment of the present invention, which is used in an analog switch, in which the power supply terminal 9 is not connected to the source diffusion layer compared to the first embodiment. Although it is connected to the substrate 8, the effect can be explained in the same way as the first embodiment.
以上のごとく本発明によｎば、ＭＩＳ半導体素子を構成
する基板と前記基板の電位を与える為の電源端子の間に
抵抗手段を挿入することによジ、ＭＩｓ半導体装置の電
気的特性を不利にする事なしに、出力端子や入出力端子
の静電気等による異常電圧に対し破壊を防止する著しい
効果がある。As described above, according to the present invention, the electrical characteristics of the MIS semiconductor device can be adversely affected by inserting the resistance means between the substrate constituting the MIS semiconductor element and the power supply terminal for applying the potential of the substrate. It has a remarkable effect of preventing damage due to abnormal voltage caused by static electricity at output terminals and input/output terminals without causing damage.
なお本発明の抵抗手段には、Ｍ工Ｓ半導体装置で一般に
使用さｎる基板とは逆の導電皿の拡散抵抗を何の支障も
なく用いる事ができ、この他に多結晶シリコン抵抗や薄
膜抵抗等も用いる事ができることは容易に理解さｎよう
。また、本発明の第１の実施例及び第２の実施例におい
て、基板は相補ｍＭＯＥ構造の場合のウェル拡散層に會
き換えてもまったく同様の効果が得られるのは明らかで
ある。As the resistance means of the present invention, a diffused resistor of a conductive plate, which is opposite to the substrate generally used in M/S semiconductor devices, can be used without any problem, and in addition, polycrystalline silicon resistors and thin film resistors can be used. It is easy to understand that resistors etc. can also be used. Furthermore, in the first and second embodiments of the present invention, it is clear that even if the substrate is replaced with the well diffusion layer of the complementary mMOE structure, exactly the same effect can be obtained.
第１図及び第２図はそｔぞ肚従来のＭ工Ｓ半導体装置を
示す断面図。
第３図は本発明の第１の実施例の断面図、第４図は不発
間第２の実施例の断面図である。
１１．出力端子 ２１．入出力端子 ３０．ドレイン拡
散層 ４１．ゲート電極 ５．。ゲート酸化、膜 ６１
．チャネル層 ７゜、ソース拡散層８゜。基板 ９．。
電源端子 １ｏ。。抵抗手段以上
出願人 株式会社第二精工合
第１は１
第３図
第２図
第４図1 and 2 are cross-sectional views showing a conventional M/S semiconductor device. FIG. 3 is a sectional view of the first embodiment of the present invention, and FIG. 4 is a sectional view of the second embodiment of the invention. 11. Output terminal 21. Input/output terminal 30. Drain diffusion layer 41. Gate electrode 5. . Gate oxidation, film 61
．． Channel layer 7°, source diffusion layer 8°. Substrate 9. . Power terminal 1o. . Resistance means and more Applicant Daini Seiko Co., Ltd. No. 1 is 1 Figure 3 Figure 2 Figure 4
Claims (1)
ン拡散層及びソース拡散層と、前記ドレイン拡散層と前
記ソース拡散層との間の前記基板表面上にゲート酸化膜
を介して設けたゲート電極と前記ドレイン拡散層につな
がｎる出力端子と、前記基板と電源端子の間に接続さｎ
る抵抗手段とからなる半導体装置。 （２）、前記抵抗手段として拡散抵抗を用いた事を特徴
とする特許請求の範囲第１項記載の半導体装置（３）、
前記抵抗手段として、多結晶シリコン抵抗を用いた事を
特徴とする特許請求の範囲第１項記載の半導体装置。 （４）、前記基板がウェル拡散にて形成さｎることを特
徴とする特許請求の範囲第１項記載の半導体装置。[Claims] (1). a drain diffusion layer and a source diffusion layer arranged at intervals on a substrate surface portion; and a gate electrode provided on the substrate surface between the drain diffusion layer and the source diffusion layer via a gate oxide film. an output terminal connected to the drain diffusion layer, and an output terminal connected between the substrate and the power supply terminal.
A semiconductor device comprising a resistance means. (2), a semiconductor device (3) according to claim 1, characterized in that a diffused resistor is used as the resistance means;
2. The semiconductor device according to claim 1, wherein a polycrystalline silicon resistor is used as the resistance means. (4) The semiconductor device according to claim 1, wherein the substrate is formed by well diffusion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58064118A JPS59189675A (en) | 1983-04-12 | 1983-04-12 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58064118A JPS59189675A (en) | 1983-04-12 | 1983-04-12 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59189675A true JPS59189675A (en) | 1984-10-27 |
Family
ID=13248826
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58064118A Pending JPS59189675A (en) | 1983-04-12 | 1983-04-12 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59189675A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03116864A (en) * | 1989-09-29 | 1991-05-17 | Nec Corp | Cmos semiconductor integrated circuit device |
| EP0442347A2 (en) * | 1990-02-15 | 1991-08-21 | National Semiconductor Corporation | Selecting one of a plurality of voltages without overlap |
| US5504361A (en) * | 1993-10-09 | 1996-04-02 | Deutsche Itt Industries Gmbh | Polarity-reversal protection for integrated electronic circuits in CMOS technology |
| WO2004059841A1 (en) * | 2002-12-25 | 2004-07-15 | Nec Corporation | Ground switching circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4929978A (en) * | 1972-07-19 | 1974-03-16 |
-
1983
- 1983-04-12 JP JP58064118A patent/JPS59189675A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4929978A (en) * | 1972-07-19 | 1974-03-16 |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03116864A (en) * | 1989-09-29 | 1991-05-17 | Nec Corp | Cmos semiconductor integrated circuit device |
| EP0442347A2 (en) * | 1990-02-15 | 1991-08-21 | National Semiconductor Corporation | Selecting one of a plurality of voltages without overlap |
| US5504361A (en) * | 1993-10-09 | 1996-04-02 | Deutsche Itt Industries Gmbh | Polarity-reversal protection for integrated electronic circuits in CMOS technology |
| WO2004059841A1 (en) * | 2002-12-25 | 2004-07-15 | Nec Corporation | Ground switching circuit |
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