JP3038722B2 - Junction type field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a junction field effect transistor (hereinafter referred to as J-FE).
T), J-F especially aimed at increasing the electrostatic withstand capability
About ET.

[Conventional technology]

A conventional J-FET of this type is shown in FIG. FIG.
1 is a plan view, and FIG. 1B is a cross-sectional view taken along the line CC. This J-FET has an n-type semiconductor layer 2 on a p-type semiconductor substrate 1.
Is formed, and the n-type semiconductor layer 2 is divided by ap ⁺ -type semiconductor region 3 connected to the p-type semiconductor substrate 1 to define an element region. Then, an oxide film 4 is formed on the n-type semiconductor layer 2, and a p ⁺ -type semiconductor region 5 as a gate region and an n ⁺ -type semiconductor as a source region and a drain region are formed through a window formed in the oxide film 4. Regions 6 and 7 are formed respectively.

The gate region 5 is connected to the p-type semiconductor substrate 1 as a gate electrode via the p-type semiconductor region 3, and the source region 6 and the drain region 7
Required wiring.

[Problems to be solved by the invention]

In the above-described conventional J-FET, the source region 6 and the drain region 7 are connected to the aluminum wiring 8 to perform necessary electric wiring, but the gate region 5 is connected to the p-type semiconductor via the p ⁺ semiconductor region 3. Electrical connection is made to the substrate 1. For this reason, the current flowing into the gate region 5 reaches the p-type semiconductor substrate 1 as the gate electrode through the p ⁺ -type semiconductor region 3, so that it takes time for the current to reach the gate electrode. For this reason, when a surge voltage is applied, it takes time for this to escape outside through the gate electrode,
There is a problem that local destruction is likely to occur in the gate region 5 and the electrostatic resistance becomes lower than that of the bipolar transistor.

In particular, in recent years, J-FETs have been increasingly miniaturized due to demands on characteristics, and since gate lengths are often 1 to 2 μm and gate widths are 200 to 300 μm, the diffusion resistance of the gate region is large. The problem is prominent.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a J-FET in which the electric resistance of a gate electrode is reduced and the electrostatic resistance is improved.

[Means for solving the problem]

According to the J-FET of the present invention, a gate electrode is formed on a back surface side of a substrate by connecting a metal wiring to a gate region formed on a front surface side of a one conductivity type semiconductor substrate as a source / drain, and through the metal wiring. Is electrically connected to

That is, a semiconductor layer of the opposite conductivity type is formed on a semiconductor substrate of one conductivity type, and a high-concentration one conductivity type impurity region is formed as an element isolation region so as to penetrate the semiconductor layer over the front and back surfaces. In the isolation region, a gate region of one conductivity type is provided in a plurality of lines, and a source region and a drain region of opposite conductivity types are provided in a region sandwiching the gate region. A source electrode and a drain electrode to be connected are respectively arranged in a comb tooth shape, a metal wiring connected to the gate region extends linearly between the source region and the drain region, and a part thereof includes the element. It is configured to be connected to the separation region.

Alternatively, a semiconductor layer of the opposite conductivity type is formed on a semiconductor substrate of one conductivity type, and a high-concentration one conductivity type impurity region is formed as an element isolation region so as to penetrate the semiconductor layer over the front and back surfaces. A gate region of one conductivity type is arranged in a lattice shape in an isolation region, and a source region and a drain region of an opposite conductivity type are arranged in an island shape in each lattice of the gate region. Metal wiring connected to the gate region extends in parallel with the lattice of the gate region, metal wiring connected to the gate region extends in a lattice shape between the source region and the drain region, and a part thereof includes the element. It is configured to be connected to the separation region.

[Action]

In this configuration, the metal wiring is connected to the gate region in parallel, and the electrical resistance in the gate region and the gate electrode is reduced by the low resistance characteristic of the metal wiring.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention. FIG. 1 (a) is a plan view, and FIG. 1 (b) is a cross-sectional view along the line AA. In FIG, 1 is a p-type semiconductor substrate 1 as the gate electrode, p ⁺ -type semiconductor region this n-type semiconductor layer 2 is formed on, and connected to the n-type semiconductor layer 2 to the p-type semiconductor substrate 1 3 to define the element region. Further, an oxide film 4 is formed on the n-type semiconductor layer 2,
Through the window opened in this oxide film 4 as a gate region
A p ⁺ -type semiconductor region 5 and n ⁺ -type semiconductor regions 6 and 7 as a source region and a drain region, respectively, are formed.

Then, the gate region 5, source region 6, connecting the aluminum wiring 8 provided on each of the drain region 7 window of the oxide film 4, a gate region 5 on which accordingly the p ⁺
It is connected to a p-type semiconductor substrate 1 as a gate electrode via a type semiconductor region 3. The source region 6 and the drain region 7 are electrically connected to a source electrode 9 and a drain electrode 10, respectively.

According to this configuration, the current flowing into the gate region 5 flows through the low-resistance aluminum wiring 8 connected to the gate region 5 and flows through the p ⁺ -type semiconductor region 3 into the p-type semiconductor substrate 1 as a gate electrode. . Therefore, the gate region 5
, The time required to reach the gate electrode can be reduced even if the diffusion resistance is large. Thus, even when a surge voltage is applied to the gate region 5, the surge voltage instantaneously reaches the gate electrode through the aluminum wiring 8 and is discharged to the outside, thereby preventing local destruction in the gate region. As a result, the electrostatic resistance can be improved.

FIG. 2 shows a second embodiment of the present invention. FIG. 2 (a) is a plan view and FIG. 2 (b) is a cross-sectional view taken along the line BB. The same or corresponding parts as those in FIG. 1 are denoted by the same reference numerals.

In this embodiment, the gate regions 5 are arranged in a lattice pattern, and the regions surrounded by the gate regions 5 have source regions 6 and 5, respectively.
The drain region 7 is formed. At this time, the p ⁺ -type semiconductor region similar to the gate region 5 is also formed in a part of the p ⁺ -type semiconductor region 3.
5A is formed.

Then, a grid-like aluminum wiring 8 is formed on the gate region 5 and the semiconductor region 5A, and the source region 6 and the drain region 7 are formed on the aluminum wiring in each region by the second aluminum wiring 12 formed on the interlayer insulating film 11. 8 are electrically connected to each other.

The aluminum wiring 8 of the gate region 5 is connected to the p-type semiconductor substrate 1 via the p ⁺ -type semiconductor region 5A and the p ⁺ -type semiconductor region 3.
Is electrically connected to

Also in this configuration, since the low resistance aluminum wiring 8 is connected to the gate region 5, the electrostatic withstand voltage can be improved as in the first embodiment.

〔The invention's effect〕

As described above, according to the present invention, the metal wiring is connected to the gate region formed on the semiconductor substrate, and the gate region is electrically connected to the gate electrode through the metal wiring. Thus, the surge voltage can be instantaneously passed to the gate electrode, thereby preventing local destruction in the gate region and improving the electrostatic withstand capability of the J-FET.

Further, according to the present invention, the metal wiring connected to the gate electrode extends linearly between the comb-shaped source / drain electrodes and is connected to the element isolation region, or the metal wiring is formed in a lattice shape and , The above-described effect can be more effectively exerted. In the latter configuration, the width of the metal wiring can be prevented from being increased by extending the metal wiring connected to each of the source and drain regions in parallel with the lattice of the gate region. Even if the metal wiring is misaligned by increasing the interval, it is difficult for the short circuit between the source and the drain and the contact hole to be exposed from the wiring.

[Brief description of the drawings]

FIG. 1 shows a first embodiment of the present invention. FIG. 1 (a) is a plan view, FIG. 1 (b) is a sectional view taken along line AA, and FIG. 2 is a second embodiment of the present invention. 3A is a plan view, FIG. 3B is a cross-sectional view taken along the line BB, and FIG.
FIG. 3A is a plan view, and FIG. 3B is a cross-sectional view taken along the line CC. 1 ... p-type semiconductor substrate, 2 ... n-type semiconductor layer, 3 ... p ⁺
Semiconductor region, 4 ... oxide film, 5 ... p ⁺ type semiconductor region,
5A ... p ⁺ type semiconductor region, 6,7 ... n ⁺ type semiconductor region, 8 ...
... aluminum wiring, 9 ... source electrode, 10 ... drain electrode, 11 ... interlayer insulating film, 12 ... second aluminum wiring.

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/337 H01L 21/338 H01L 29/808 H01L 29/812

Claims (2)

(57) [Claims] A semiconductor layer of the opposite conductivity type is formed on a semiconductor substrate of one conductivity type, and a high-concentration impurity region of one conductivity type is formed as an element isolation region so as to penetrate the semiconductor layer over the front and back surfaces. In the element isolation region, a gate region of one conductivity type is arranged in a plurality of lines, and a source region and a drain region of opposite conductivity types are arranged in a region sandwiching the gate region. A source electrode and a drain electrode connected to the drain region are respectively arranged in a comb tooth shape, and a metal wiring connected to the gate region extends linearly between the source region and the drain region, and a part thereof. 3. The junction field effect transistor according to claim 1, wherein the junction field effect transistor is connected to the element isolation region. 2. A semiconductor layer of opposite conductivity type is formed on a semiconductor substrate of one conductivity type, and a high-concentration impurity region of one conductivity type is formed as an element isolation region so as to penetrate the semiconductor layer over the front and back surfaces. A gate region of one conductivity type is arranged in a lattice shape in the element isolation region, and a source region and a drain region of the opposite conductivity type are arranged in an island shape in each lattice of the gate region; And a metal line connected to the drain region extends in parallel with the lattice of the gate region, and the metal line connected to the gate region extends in a lattice shape between the source region and the drain region, and a part thereof. 3. The junction field effect transistor according to claim 1, wherein the junction field effect transistor is connected to the element isolation region.