JPS60124122A - 論理ゲ−ト回路 - Google Patents
論理ゲ−ト回路Info
- Publication number
- JPS60124122A JPS60124122A JP58232531A JP23253183A JPS60124122A JP S60124122 A JPS60124122 A JP S60124122A JP 58232531 A JP58232531 A JP 58232531A JP 23253183 A JP23253183 A JP 23253183A JP S60124122 A JPS60124122 A JP S60124122A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- delay time
- control voltage
- gate circuit
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00323—Delay compensation
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
- G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
- G01R31/3191—Calibration
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Logic Circuits (AREA)
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58232531A JPS60124122A (ja) | 1983-12-09 | 1983-12-09 | 論理ゲ−ト回路 |
| DE8484308520T DE3483576D1 (de) | 1983-12-09 | 1984-12-07 | Tor-schaltungsanordnung. |
| EP84308520A EP0151875B1 (en) | 1983-12-09 | 1984-12-07 | Gate circuit device |
| KR1019840007774A KR900002599B1 (ko) | 1983-12-09 | 1984-12-08 | 게이트 회로장치 |
| US06/679,998 US4645958A (en) | 1983-12-09 | 1984-12-10 | Variable delay gate circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58232531A JPS60124122A (ja) | 1983-12-09 | 1983-12-09 | 論理ゲ−ト回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60124122A true JPS60124122A (ja) | 1985-07-03 |
| JPH0464032B2 JPH0464032B2 (https=) | 1992-10-13 |
Family
ID=16940795
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58232531A Granted JPS60124122A (ja) | 1983-12-09 | 1983-12-09 | 論理ゲ−ト回路 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60124122A (https=) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5710530A (en) * | 1980-05-16 | 1982-01-20 | Ibm | Electronic device |
| JPS5756945A (en) * | 1980-09-19 | 1982-04-05 | Mitsubishi Electric Corp | Logic circuit |
| JPS58107725A (ja) * | 1981-12-22 | 1983-06-27 | Nec Corp | 電流切換型論理回路 |
-
1983
- 1983-12-09 JP JP58232531A patent/JPS60124122A/ja active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5710530A (en) * | 1980-05-16 | 1982-01-20 | Ibm | Electronic device |
| JPS5756945A (en) * | 1980-09-19 | 1982-04-05 | Mitsubishi Electric Corp | Logic circuit |
| JPS58107725A (ja) * | 1981-12-22 | 1983-06-27 | Nec Corp | 電流切換型論理回路 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0464032B2 (https=) | 1992-10-13 |
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