JPS60100465A - 無接触横注入型２電極ｄｒａｍセル - Google Patents

無接触横注入型２電極ｄｒａｍセル

Info

Publication number
JPS60100465A
JPS60100465A JP59123551A JP12355184A JPS60100465A JP S60100465 A JPS60100465 A JP S60100465A JP 59123551 A JP59123551 A JP 59123551A JP 12355184 A JP12355184 A JP 12355184A JP S60100465 A JPS60100465 A JP S60100465A
Authority
JP
Japan
Prior art keywords
channel region
transistor
memory
memory cell
polysilicon layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59123551A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0430748B2 (enExample
Inventor
パラブ　チヤツタージー
ヒサシ　シチジヨウ
ジヨン　イー・レイス
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of JPS60100465A publication Critical patent/JPS60100465A/ja
Publication of JPH0430748B2 publication Critical patent/JPH0430748B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
JP59123551A 1983-06-17 1984-06-15 無接触横注入型２電極ｄｒａｍセル Granted JPS60100465A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/505,157 US4545034A (en) 1983-06-17 1983-06-17 Contactless tite RAM
US505157 1983-06-17

Publications (2)

Publication Number Publication Date
JPS60100465A true JPS60100465A (ja) 1985-06-04
JPH0430748B2 JPH0430748B2 (enExample) 1992-05-22

Family

ID=24009252

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59123551A Granted JPS60100465A (ja) 1983-06-17 1984-06-15 無接触横注入型２電極ｄｒａｍセル

Country Status (2)

Country Link
US (1) US4545034A (enExample)
JP (1) JPS60100465A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03134894A (ja) * 1989-10-19 1991-06-07 Sharp Corp 半導体記憶装置

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5008722A (en) * 1986-03-27 1991-04-16 Texas Instruments Incorporated Non-volatile memory
US5262846A (en) * 1988-11-14 1993-11-16 Texas Instruments Incorporated Contact-free floating-gate memory array with silicided buried bitlines and with single-step-defined floating gates
KR950008385B1 (ko) * 1990-05-24 1995-07-28 삼성전자주식회사 반도체 소자의 워드라인 형성방법
US5273926A (en) * 1991-06-27 1993-12-28 Texas Instruments Incorporated Method of making flash EEPROM or merged FAMOS cell without alignment sensitivity
US5218568A (en) * 1991-12-17 1993-06-08 Texas Instruments Incorporated Electrically-erasable, electrically-programmable read-only memory cell, an array of such cells and methods for making and using the same
EP2560195A1 (en) * 2011-08-17 2013-02-20 Hitachi, Ltd. Memory device with an isolated gate comprising two portions separated by a barrier and method of operating the same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4003036A (en) * 1975-10-23 1977-01-11 American Micro-Systems, Inc. Single IGFET memory cell with buried storage element
US4380804A (en) * 1980-12-29 1983-04-19 Ncr Corporation Earom cell matrix and logic arrays with common memory gate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03134894A (ja) * 1989-10-19 1991-06-07 Sharp Corp 半導体記憶装置

Also Published As

Publication number Publication date
US4545034A (en) 1985-10-01
JPH0430748B2 (enExample) 1992-05-22

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