JPS5955061A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JPS5955061A
JPS5955061A JP57165667A JP16566782A JPS5955061A JP S5955061 A JPS5955061 A JP S5955061A JP 57165667 A JP57165667 A JP 57165667A JP 16566782 A JP16566782 A JP 16566782A JP S5955061 A JPS5955061 A JP S5955061A
Authority
JP
Japan
Prior art keywords
fuse
wiring
cutting
manufacturing
aluminum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57165667A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6145388B2 (enrdf_load_stackoverflow
Inventor
Noriaki Sato
佐藤 典章
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57165667A priority Critical patent/JPS5955061A/ja
Publication of JPS5955061A publication Critical patent/JPS5955061A/ja
Publication of JPS6145388B2 publication Critical patent/JPS6145388B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
JP57165667A 1982-09-22 1982-09-22 半導体装置の製造方法 Granted JPS5955061A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57165667A JPS5955061A (ja) 1982-09-22 1982-09-22 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57165667A JPS5955061A (ja) 1982-09-22 1982-09-22 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS5955061A true JPS5955061A (ja) 1984-03-29
JPS6145388B2 JPS6145388B2 (enrdf_load_stackoverflow) 1986-10-07

Family

ID=15816724

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57165667A Granted JPS5955061A (ja) 1982-09-22 1982-09-22 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS5955061A (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005031866A3 (de) * 2003-09-25 2005-05-12 Infineon Technologies Ag Anordnung zur verbindung in integrierten mos-strukturen
KR100979367B1 (ko) 2008-03-19 2010-08-31 주식회사 하이닉스반도체 반도체 소자의 퓨즈 형성 방법

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005031866A3 (de) * 2003-09-25 2005-05-12 Infineon Technologies Ag Anordnung zur verbindung in integrierten mos-strukturen
DE10344391A1 (de) * 2003-09-25 2005-05-12 Infineon Technologies Ag Anordnung zur Verbindung in integrierten MOS-Strukturen
KR100979367B1 (ko) 2008-03-19 2010-08-31 주식회사 하이닉스반도체 반도체 소자의 퓨즈 형성 방법
US8017454B2 (en) 2008-03-19 2011-09-13 Hynix Semiconductor Inc. Fuse of semiconductor device and method for forming the same
US8324664B2 (en) 2008-03-19 2012-12-04 Hynix Semiconductor Inc. Fuse of a semiconductor device

Also Published As

Publication number Publication date
JPS6145388B2 (enrdf_load_stackoverflow) 1986-10-07

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