JPS5944852A - 多層チツプ実装方法 - Google Patents

多層チツプ実装方法

Info

Publication number
JPS5944852A
JPS5944852A JP57156206A JP15620682A JPS5944852A JP S5944852 A JPS5944852 A JP S5944852A JP 57156206 A JP57156206 A JP 57156206A JP 15620682 A JP15620682 A JP 15620682A JP S5944852 A JPS5944852 A JP S5944852A
Authority
JP
Japan
Prior art keywords
cover
chip
bonded
fusible material
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57156206A
Other languages
English (en)
Inventor
Masahiro Yamada
正弘 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP57156206A priority Critical patent/JPS5944852A/ja
Publication of JPS5944852A publication Critical patent/JPS5944852A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074—Stacked arrangements of non-apertured devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/1627—Disposition stacked type assemblies, e.g. stacked multi-cavities

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 本発明は、半導体素子（以下、チップと略記）の高密度
実装に関する。最近、半導体製造技術の向上に伴い、東
精度が高い半嗜２体製品が開発されている。このことに
チップザイズを上げることなく、より機能が大きな製品
が、出来ることを示す。
ととろが、半う、１体製造技術の向」二に比べ、こノ１
．らのチップを実装するパッケージの、高■１度イしか
、↓、進んでいない。そこで、木発ＩＪ’ｌ　ｉ従来の
パッケージのレベルを越えることなく、実装Ｗｉｔ’　
ｍｌを上げる方法を提供するものである。本発明の実訳
二方法Ｖ（一ついて、第１図Ｃα１〜ＣＣ１で説明する
。
セラミックパッケージ１０１上に、形成されたキャビテ
ィ（実装のための四部）Ｋ１チッグ１０３を、Ａｇ−８
ｎもしくは、エポキシ系鋼ペーストによシ固定する。次
に、パッケージに用魁されているリードの引出し耶１０
２と、該チップ１（）３の釦；極数シ出しパッドとの間
を、Ａｕによるワイヤーボンディング１０４を行なう。
第１図１ａ１次に、樹脂系ブヲスチソクス溶月１０５を
、ボッティング形成する。さらに、該プヲスヂツクス′
ｆｆｉイ′ＡｌＯ３が溶解している間に、セラミックス
もしくは、金属によるふた１０６′ｆＣ，のせ、ふた１
０６とプラスチックス浴材と接着させる。第一しＩＩ／
＋１該ふた上に、第二チップ１０７を、該ブヲスヂツク
ス溶材１０５が、丙溶解しない湿度にて、固定する。こ
の接着にｄｏ、エポキシ系接着制を使う。
さらに、パッケージに用意しである第二リード引出り、
　ｆ’ｔ’！　１０８と、該２１１．ニチツプとを、ワ
イヤーボンディング］、０９ｊ、、最後にパッケージ上
部にエポキシ系接着利シてより、ふた】１０を気密接着
する。第１図１ｃ１以上のように実装したパッケージは
、特に次の用途のデツプ実装に於いて効果が大きい。
Ｉｌｌ　　二つのチップ間で、電極リードを共有・する
ところが多い。（例、メモリー、マイコン）１２＋　　
チップが大きくなるため、ワンチップ化出来ない回路４
．ｔ（ｒ成の場合。などが考えら）する。
図面の１ハ１単なｈ兄明 第１図１（１，１１＃ｌ　ｌＣ１が、本発明の実装方法
であシ、１０３及び］０７が、チップ、１０５がボッテ
ィングされた封じＨ料、１０６，１１０がふたである。
以　　　上 出願人　株式会社識訪精玉舎 代理人　弁理士最　上　　務 二’、、　　１　　口

Claims (1)

    【特許請求の範囲】
  1. セラミックベース上に、第一半導体素子を固定し、該半
    導体素子と、該セラミックベース上の第一配線引出し＠
    ｊｌとワイヤーボンディングし、樹脂イＡ料によりボッ
    ティングし、該樹脂材料が溶解中、１１ｉＩ熱性材料の
    ふたを、形成固定し、該ふた上に第二半導体素子を固定
    し、第二前約引出し部とワイヤボンディングし、該セラ
    ミックベース上部に、耐熱性イ（イ′’＋にょる、８１
    八二ふたを、気密接層することを’ｌＩｆ徴とする多層
    チップ実装方法。
JP57156206A 1982-09-07 1982-09-07 多層チツプ実装方法 Pending JPS5944852A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57156206A JPS5944852A (ja) 1982-09-07 1982-09-07 多層チツプ実装方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57156206A JPS5944852A (ja) 1982-09-07 1982-09-07 多層チツプ実装方法

Publications (1)

Publication Number Publication Date
JPS5944852A true JPS5944852A (ja) 1984-03-13

Family

ID=15622683

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57156206A Pending JPS5944852A (ja) 1982-09-07 1982-09-07 多層チツプ実装方法

Country Status (1)

Country Link
JP (1) JPS5944852A (ja)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4807019A (en) * 1987-04-24 1989-02-21 Unisys Corporation Cavity-up-cavity-down multichip integrated circuit package
JPH0730059A (ja) * 1993-06-24 1995-01-31 Nec Corp マルチチップモジュール
US5856915A (en) * 1997-02-26 1999-01-05 Pacesetter, Inc. Vertically stacked circuit module using a platform having a slot for establishing multi-level connectivity
US5963429A (en) * 1997-08-20 1999-10-05 Sulzer Intermedics Inc. Printed circuit substrate with cavities for encapsulating integrated circuits
US6026325A (en) * 1998-06-18 2000-02-15 Pacesetter, Inc. Implantable medical device having an improved packaging system and method for making electrical connections
US7211884B1 (en) 2002-01-28 2007-05-01 Pacesetter, Inc. Implantable medical device construction using a flexible substrate

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4807019A (en) * 1987-04-24 1989-02-21 Unisys Corporation Cavity-up-cavity-down multichip integrated circuit package
JPH0730059A (ja) * 1993-06-24 1995-01-31 Nec Corp マルチチップモジュール
US5856915A (en) * 1997-02-26 1999-01-05 Pacesetter, Inc. Vertically stacked circuit module using a platform having a slot for establishing multi-level connectivity
US5963429A (en) * 1997-08-20 1999-10-05 Sulzer Intermedics Inc. Printed circuit substrate with cavities for encapsulating integrated circuits
US6026325A (en) * 1998-06-18 2000-02-15 Pacesetter, Inc. Implantable medical device having an improved packaging system and method for making electrical connections
US7211884B1 (en) 2002-01-28 2007-05-01 Pacesetter, Inc. Implantable medical device construction using a flexible substrate

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