JPS5940554A - 多層チツプキヤリア - Google Patents

多層チツプキヤリア

Info

Publication number
JPS5940554A
JPS5940554A JP57151068A JP15106882A JPS5940554A JP S5940554 A JPS5940554 A JP S5940554A JP 57151068 A JP57151068 A JP 57151068A JP 15106882 A JP15106882 A JP 15106882A JP S5940554 A JPS5940554 A JP S5940554A
Authority
JP
Japan
Prior art keywords
package
chip
mounting
chip carrier
bonded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57151068A
Other languages
English (en)
Inventor
Masahiro Yamada
正弘 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP57151068A priority Critical patent/JPS5940554A/ja
Publication of JPS5940554A publication Critical patent/JPS5940554A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/1627—Disposition stacked type assemblies, e.g. stacked multi-cavities

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 本発明は、半導体素子（以下、チップと略記）の高密度
実装に関する。最近、半導体製造技術の向上に伴い、集
積度が高い半導体製品が開発されている。このことは、
チップサイズを上げることなく、より機能が大きな製品
が、出来ることを示す。ところが、半導体製造技術の向
上に比べ、これらのチップを実装するパッケージの、高
密度化は進んでいない。そこで、本発明は従来のパッケ
ージのレベルを越えることなく、実装密度を上げる方法
を提供するものである。
第一図が、従来のリードレスチップキャリアパッケージ
（以下、チップキャリアと略記）の実装例である。通常
セラミックで出来たベース１ｏ１上に、実装のための四
部（キャビティと略記）が形成されであるパッケージに
、Ａｕ−３ｉなどによりチップ１０２を接着固定し、該
チップ１０２ニハターン形成されている電極パットト、
パッケージ上に用意されている電極引出し部１０４との
間をワイヤーボンディング１０３したのち、Ａｕ−３ｎ
１０５などによりふた１０６を、パッケージ上部に気密
接着する。このように実装されたチップキャリアに対し
、上下両面にチップ接着し、高密度実装を可能にしたの
が、本発明であり、以下のような用途に特に効果が大き
い。
（１）二つのチップ間で、電極リードを共有するところ
が多い。（メモリー、マイフンなト）（２）　　回路が
複雑で、一つのチップで作ると、チツブサイズが大きく
なる（マルチチップ構成）。
次に、第二図で本発明の説明をする。
まず、上下両面に、キャビティが形成しであるパンケー
ジ２０１の片面に、チップ２０２を接着し、パッケージ
の電極引出し部２０４と、チップ２０２に、用意されて
いるボンディングパッド間を金ワイヤ−２０６で、ボン
ディングする。
次に、パッケージ上面にふた２０５を形成する。
さらに、パッケージの残りの面に、チップ２０７を接着
し、ワイヤーボンディングし、ふた２０７を接着シール
する。本発明のように、上下両面にチップ実装するに当
っては、チップ接着及びふたのシールは、極力低温で行
なう必要がある。実施例では、主に、接着、シール剤に
、エボキン系樹脂接着剤を用いている。このように実装
されたパッケージは、リードレスであり、パッケージ外
型は小さく、さらに、複数チップ実装という多くの利点
をもつパッケージとなり、半導体製造技術向上による多
機能化に充分対応可能なパッケージである。
【図面の簡単な説明】
第１図が従来のチップキャリアパッケージの断面図。 第２図が本発明の断面図。 １０２．２０２，２０６がチップ １０６．２０５，２０７がふたである。 以　　上 出願人　　株式会社諏訪精工舎 代理人　　弁理士　最上　　務

Claims (1)

    【特許請求の範囲】
  1. リードレスデツプキャリアパッケージに於いて、上下両
    面に実装のための四部が形成され樹脂系接着剤により、
    半導体素子が実装されワイヤーボンディングされ、ふた
    が形成されていることを特徴とする多層チップキャリア
    。
JP57151068A 1982-08-31 1982-08-31 多層チツプキヤリア Pending JPS5940554A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57151068A JPS5940554A (ja) 1982-08-31 1982-08-31 多層チツプキヤリア

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57151068A JPS5940554A (ja) 1982-08-31 1982-08-31 多層チツプキヤリア

Publications (1)

Publication Number Publication Date
JPS5940554A true JPS5940554A (ja) 1984-03-06

Family

ID=15510599

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57151068A Pending JPS5940554A (ja) 1982-08-31 1982-08-31 多層チツプキヤリア

Country Status (1)

Country Link
JP (1) JPS5940554A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1949770B1 (en) * 2005-11-09 2018-12-12 Koninklijke Philips N.V. Method of manufacturing a package carrier for enclosing at least one microelectronic element and method of manufacturing a diagnostic device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1949770B1 (en) * 2005-11-09 2018-12-12 Koninklijke Philips N.V. Method of manufacturing a package carrier for enclosing at least one microelectronic element and method of manufacturing a diagnostic device

Similar Documents

Publication Publication Date Title
KR0179803B1 (ko) 리드노출형 반도체 패키지
JP4808408B2 (ja) マルチチップパッケージ、これに使われる半導体装置及びその製造方法
JP2000133767A (ja) 積層化半導体パッケ―ジ及びその製造方法
JP2004200683A (ja) マルチチップパッケージ
KR100664796B1 (ko) 사이드 브레이즈 패키지
US5255157A (en) Plastic pin grid array package with locking pillars
JPH04174551A (ja) 半導体装置及びその製造方法
JPS62142341A (ja) 半導体装置およびその製造方法
JPH0221139B2 (ja)
JPS5940554A (ja) 多層チツプキヤリア
JPS58219757A (ja) 半導体装置
JPS5944851A (ja) 多層チツプ実装パツケ−ジ
JPS6352461A (ja) 半導体装置
JPH01137660A (ja) 半導体装置
JPS6370532A (ja) 半導体装置
JPS5984557A (ja) 多層チツプキヤリアパツケ−ジ
JPS60150660A (ja) 半導体装置
JPS63151053A (ja) 半導体装置
JPH0461152A (ja) 半導体装置
KR100600176B1 (ko) 반도체패키지
JP2522182B2 (ja) 半導体装置
JPH02105450A (ja) 半導体装置
JPS6074659A (ja) 半導体装置
JPS5998540A (ja) 半導体装置
JPS62131555A (ja) 半導体集積回路装置