JPS59191765U

JPS59191765U - Wet multilayer ceramic substrate

Info

Publication number: JPS59191765U
Application number: JP8505983U
Authority: JP
Inventors: 茂斉藤; 品川　充久; 松本　智三; 元山　郁夫; 浅羽　洋史
Original assignee: 株式会社日立製作所
Priority date: 1983-06-06
Filing date: 1983-06-06
Publication date: 1984-12-19

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は印刷積層により形成された湿式多層セラミック
基板へ部品リード挿入後、はんだ付した断面図、第２図
は印刷積層部をセラミック基体で挾まれた湿式多層セラ
ミック基板へ部品リード挿入後、はんだ付した断面図、
第３図は本考案による湿式多層セラミック基板へ部品リ
ード挿入後、はんだ付した断面図である。１ａ、　　１ｂ・・・セラミック基体、２ａ、　　２ｄ
・・・絶縁体層、３ａ〜３ｄ−内部導電層、３ｅｌ　〜
３ｅ３゜３ｆ、　　３ｇ・・・導電層、４・・・ピアホ
ール、５・・・スルーホール、６・・・部品挿入穴、７
・・・オーバーコート、８・・・印刷抵抗、９・・・挿
入部品のリード、１０・・・チップ等装着部品、１１・
・・はんだ。Figure 1 is a cross-sectional view of soldering after inserting component leads into a wet multilayer ceramic board formed by printed lamination, and Figure 2 is a cross-sectional view of soldering after inserting component leads into a wet multilayer ceramic board sandwiched between printed laminated ceramic substrates. Cross section with soldering,
FIG. 3 is a cross-sectional view of a wet multilayer ceramic board according to the present invention in which component leads are inserted and soldered. 1a, 1b...ceramic base, 2a, 2d
...Insulator layer, 3a to 3d-inner conductive layer, 3el to
3e3゜3f, 3g... Conductive layer, 4... Pier hole, 5... Through hole, 6... Component insertion hole, 7
... Overcoat, 8... Printed resistor, 9... Lead for inserted parts, 10... Mounting parts such as chips, 11.
...Solder.

Claims

[Scope of utility model registration request]

In a wet multilayer ceramic substrate formed by alternately printing conductor layers and insulating layers on a ceramic substrate, solder electrodes for inserting components are formed in the intermediate layer, and soldering electrodes for inserting components are formed on the final layer of the component insertion portion. A wet multilayer ceramic substrate characterized by forming a conductive layer on the end face of an insulating layer.