JPS583067U

JPS583067U - printed wiring board

Info

Publication number: JPS583067U
Application number: JP9602081U
Authority: JP
Inventors: 福吉　弘和
Original assignee: 日本電気ホームエレクトロニクス株式会社
Priority date: 1981-06-30
Filing date: 1981-06-30
Publication date: 1983-01-10

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は従来の／リント配線板の使用状態を示４す要部
裏面図、第２図さ第３図は同プリント配線板の使用状態
を示す要部断面図、第４図は、本−案に係るプリント配
線板の７実施例を示す要部裏面図、第５図は同プリント
配線板の要部断面図、第６図は第５図の部分拡大図であ
る。１・・・絶縁基板、２・・・ランド部、３・・・取付孔
、４・・・第１層の半田付抵抗層、５・・・電子部品、
６・・・リード端子、７・・・半田、８・・・導電体パ
ターン、１４・・・第２層の半田付抵抗層。　　゛Figure 1 is a rear view of the main parts of a conventional/lint wiring board showing how it is used, Figures 2 and 3 are sectional views of the main parts showing how the same printed wiring board is used, and Figure 4 is a diagram showing how the printed wiring board is used. FIG. 5 is a sectional view of the main parts of the printed wiring board, and FIG. 6 is a partially enlarged view of FIG. 5. DESCRIPTION OF SYMBOLS 1... Insulating board, 2... Land portion, 3... Mounting hole, 4... First layer soldering resistance layer, 5... Electronic component,
6... Lead terminal, 7... Solder, 8... Conductor pattern, 14... Second layer soldered resistance layer.゛

Claims

[Scope of utility model registration request]

forming a plurality of conductor patterns adjacent to each other on an insulating substrate, leaving a land portion for soldering on one surface of the conductor pattern to form a first layer of soldering resistance layer;
A first layer of soldering resistor layer is formed on the other surface of the conductor pattern that contacts the tip of a lead terminal of an electronic component to be soldered to the backing part, and a second layer of soldering resistor layer is formed on the other surface of the conductive pattern. A printed wiring board characterized in that the printed wiring board is formed by laminating i layers on the first soldering resistance layer.