JPS59155152A - 樹脂封止半導体装置 - Google Patents

樹脂封止半導体装置

Info

Publication number
JPS59155152A
JPS59155152A JP58029815A JP2981583A JPS59155152A JP S59155152 A JPS59155152 A JP S59155152A JP 58029815 A JP58029815 A JP 58029815A JP 2981583 A JP2981583 A JP 2981583A JP S59155152 A JPS59155152 A JP S59155152A
Authority
JP
Japan
Prior art keywords
resin
lead frame
semiconductor device
glass
sealed semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58029815A
Other languages
English (en)
Inventor
Seiichi Iwamatsu
誠一 岩松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP58029815A priority Critical patent/JPS59155152A/ja
Publication of JPS59155152A publication Critical patent/JPS59155152A/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142Sealing arrangements between parts, e.g. adhesion promotors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 本発明は樹脂封止半導体装置の構造に関する。
従来、樹脂封止半導体装置の構造は、第1図に示す断面
の如き構造とな−ていた。すなわち、リード・フレーム
1の一部に金メッキ層2が形成され、該金メ〜キ部の一
部に半導体(fM )装置チップ3を貼付け、Siチヅ
プ3のAtパッド部4とリード・フレーム1の他の金メ
ツキ部2との間を金′線5で接続し、エポキシ樹#6で
封止する構造が用いられていた。
しかし、上記従来技術では、樹脂とリード・フレームと
の境界面からプレッシャー−クック・テス)(PCT、
’ 加圧φ加水・加温テスト)#cおいて、水が侵入し
、sjチップのaパッド部を腐蝕するという欠点があっ
た。
本発明は、かかる従来技術の欠点をなくシ、POTでも
aバッド腐蝕のない樹脂封止半導体装置を提供すること
を目的とする。
上記目的を達成するための本発明の基本的な構成は、樹
脂封止半導体装置に〉いて、リード・フレームの半導体
チップ貼付は部、ワイヤー−ポンディング部及び外部リ
ード接続部以外で、少なくとも樹脂封止の樹脂と接する
リード・フレーム部にガラス層が形成されて成ることを
特徴とする。
以下、実施例により本発明を詳述する。
第2図は本発明による樹脂封止半導体装置の一実施例を
示す断面図・である。リード・フレーム11には、一部
に塗布ガラスを印刷して形成したガラス層12と、金メ
ッキ層13が形成さ゛れ、Siチッグ14が貼付杜られ
ると共に、psiチップ14のAtハツト部15と、リ
ートeフレームの金メッキ層13の一部とけ金線16で
接続され、エポキシ樹脂17で封止する。
上記の如く、封止樹脂とリード・フレームとの境界面に
ガラス層を形成することにより、樹脂とガラスとの接着
力が向上し、該境界面からの水分の侵入が防止され、P
CTでのaバッド腐蝕が防止できるという効果がある。
本発明によるガラス層は塗布ガラスの入ならずセラミッ
ク層、ホウロウ層、あるいは酸化鉄屑等であっても良い
【図面の簡単な説明】
第1図は従来技術による樹脂封止半導体装置の断面図。 第2図は本発明による樹脂封止半導体装置の一例を示す
断面図である。 1.11・・・・・・リート・フレーム2.13・・・
・・・金メッキ層 3.14・・・・・・半導体チップ 4.15・・・・・・aバッド部 5.16・・・・・・金線 6.17・・・・・・樹脂 12・・・・・・ガラス層 以  上 出願人 株式会社 諏訪精工舎

Claims (1)

    【特許請求の範囲】
  1. リード拳フレームの半導体チップ貼付は部、ワイヤーボ
    ンディング部及び外部リード接続部以外で、少なくとも
    樹脂封止の樹脂と接するリード・フレーム部にガラス層
    が形成されて成ることを特徴とする樹脂封止半導体装置
JP58029815A 1983-02-24 1983-02-24 樹脂封止半導体装置 Pending JPS59155152A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58029815A JPS59155152A (ja) 1983-02-24 1983-02-24 樹脂封止半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58029815A JPS59155152A (ja) 1983-02-24 1983-02-24 樹脂封止半導体装置

Publications (1)

Publication Number Publication Date
JPS59155152A true JPS59155152A (ja) 1984-09-04

Family

ID=12286510

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58029815A Pending JPS59155152A (ja) 1983-02-24 1983-02-24 樹脂封止半導体装置

Country Status (1)

Country Link
JP (1) JPS59155152A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02126696A (ja) * 1988-11-07 1990-05-15 Fujikura Ltd ホウロウ配線基板とその製造法
US7629677B2 (en) * 2006-09-21 2009-12-08 Samsung Electronics Co., Ltd. Semiconductor package with inner leads exposed from an encapsulant

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5439709A (en) * 1977-09-06 1979-03-27 Toshiba Corp Steam condenser
JPS5578554A (en) * 1978-12-11 1980-06-13 Hitachi Ltd Semiconductor
JPS6023497A (ja) * 1983-06-20 1985-02-06 ユニリ−バ−・ナ−ムロ−ゼ・ベンノ−トシヤ−プ 漂白洗剤組成物

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5439709A (en) * 1977-09-06 1979-03-27 Toshiba Corp Steam condenser
JPS5578554A (en) * 1978-12-11 1980-06-13 Hitachi Ltd Semiconductor
JPS6023497A (ja) * 1983-06-20 1985-02-06 ユニリ−バ−・ナ−ムロ−ゼ・ベンノ−トシヤ−プ 漂白洗剤組成物

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02126696A (ja) * 1988-11-07 1990-05-15 Fujikura Ltd ホウロウ配線基板とその製造法
US7629677B2 (en) * 2006-09-21 2009-12-08 Samsung Electronics Co., Ltd. Semiconductor package with inner leads exposed from an encapsulant

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