JPS59144932A - 処理装置切替方式 - Google Patents

処理装置切替方式

Info

Publication number
JPS59144932A
JPS59144932A JP58018362A JP1836283A JPS59144932A JP S59144932 A JPS59144932 A JP S59144932A JP 58018362 A JP58018362 A JP 58018362A JP 1836283 A JP1836283 A JP 1836283A JP S59144932 A JPS59144932 A JP S59144932A
Authority
JP
Japan
Prior art keywords
typewriter
abbreviated
processing device
line status
ttysw281
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58018362A
Other languages
English (en)
Japanese (ja)
Other versions
JPS63828B2 (enrdf_load_html_response
Inventor
Toru Jinbo
神保　亨
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58018362A priority Critical patent/JPS59144932A/ja
Publication of JPS59144932A publication Critical patent/JPS59144932A/ja
Publication of JPS63828B2 publication Critical patent/JPS63828B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Accessory Devices And Overall Control Thereof (AREA)
  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)
JP58018362A 1983-02-07 1983-02-07 処理装置切替方式 Granted JPS59144932A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58018362A JPS59144932A (ja) 1983-02-07 1983-02-07 処理装置切替方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58018362A JPS59144932A (ja) 1983-02-07 1983-02-07 処理装置切替方式

Publications (2)

Publication Number Publication Date
JPS59144932A true JPS59144932A (ja) 1984-08-20
JPS63828B2 JPS63828B2 (enrdf_load_html_response) 1988-01-08

Family

ID=11969580

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58018362A Granted JPS59144932A (ja) 1983-02-07 1983-02-07 処理装置切替方式

Country Status (1)

Country Link
JP (1) JPS59144932A (enrdf_load_html_response)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03155928A (ja) * 1989-11-14 1991-07-03 Taku Nakasaki 合成樹脂製袋の製造方法及びその装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5720830A (en) * 1980-07-11 1982-02-03 Mitsubishi Electric Corp Automatic switching device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5720830A (en) * 1980-07-11 1982-02-03 Mitsubishi Electric Corp Automatic switching device

Also Published As

Publication number Publication date
JPS63828B2 (enrdf_load_html_response) 1988-01-08

Similar Documents

Publication Publication Date Title
JP2886856B2 (ja) 二重化バス接続方式
JPS59106056A (ja) フエイルセイフ式デ−タ処理システム
JPS59144932A (ja) 処理装置切替方式
CN112838945B (zh) 一种基于混合型同城双活的网络拓扑结构
JPS62179044A (ja) 複合計算機システム
JPS60134352A (ja) 二重化バス制御装置
JPS60123952A (ja) 入出力制御方式
JPS593916B2 (ja) 再開処理方式
JPS638500B2 (enrdf_load_html_response)
JPS6061859A (ja) マイクロコンピュ−タのデ−タ通信方式
JPS604498B2 (ja) 電子計算機とダイレクト・メモリ・アクセス装置の結合方法
JPS59223876A (ja) コンピユ−タ・ネツトワ−ク
JPH04263333A (ja) メモリ二重化方式
JPH0346855B2 (enrdf_load_html_response)
JPS6233622B2 (enrdf_load_html_response)
JPH0329021A (ja) プリンタサーバ
JPS55127790A (en) Duplex system of exchange processing unit
JPS6149260A (ja) チヤネル処理装置
JPS5990150A (ja) 入出力装置の二重化方法
JPS63279359A (ja) マルチｃｐｕのデ−タ受け渡し装置
JPS61242194A (ja) 外部フアイルメモリのコピ−方式
JPS61166670A (ja) サ−ビスプロセツサバス切り替え方式
JPS59201153A (ja) スタンドアロン型画像処理システムのホスト接続方式
JPS62260263A (ja) マルチプロセツサによるプログラム制御方式
JPH05204878A (ja) インタフェース制御システム