JPS59123931A - キヤリ−信号発生器 - Google Patents

キヤリ−信号発生器

Info

Publication number
JPS59123931A
JPS59123931A JP23361382A JP23361382A JPS59123931A JP S59123931 A JPS59123931 A JP S59123931A JP 23361382 A JP23361382 A JP 23361382A JP 23361382 A JP23361382 A JP 23361382A JP S59123931 A JPS59123931 A JP S59123931A
Authority
JP
Japan
Prior art keywords
gate
input
output
trs
carry signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP23361382A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0218499B2 (enrdf_load_stackoverflow
Inventor
Masaru Uya
宇屋　優
Katsuyuki Kaneko
克幸 金子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP23361382A priority Critical patent/JPS59123931A/ja
Publication of JPS59123931A publication Critical patent/JPS59123931A/ja
Publication of JPH0218499B2 publication Critical patent/JPH0218499B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
JP23361382A 1982-12-29 1982-12-29 キヤリ−信号発生器 Granted JPS59123931A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23361382A JPS59123931A (ja) 1982-12-29 1982-12-29 キヤリ−信号発生器

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23361382A JPS59123931A (ja) 1982-12-29 1982-12-29 キヤリ−信号発生器

Publications (2)

Publication Number Publication Date
JPS59123931A true JPS59123931A (ja) 1984-07-17
JPH0218499B2 JPH0218499B2 (enrdf_load_stackoverflow) 1990-04-25

Family

ID=16957785

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23361382A Granted JPS59123931A (ja) 1982-12-29 1982-12-29 キヤリ−信号発生器

Country Status (1)

Country Link
JP (1) JPS59123931A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62241029A (ja) * 1985-12-20 1987-10-21 テキサス　インスツルメンツ　インコ−ポレイテツド 多段並列バイナリイ加算器回路

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51147933A (en) * 1975-06-13 1976-12-18 Nippon Telegr & Teleph Corp <Ntt> Binary full adder circuit
JPS5447450A (en) * 1977-09-21 1979-04-14 Nec Corp Arthmetic circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51147933A (en) * 1975-06-13 1976-12-18 Nippon Telegr & Teleph Corp <Ntt> Binary full adder circuit
JPS5447450A (en) * 1977-09-21 1979-04-14 Nec Corp Arthmetic circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62241029A (ja) * 1985-12-20 1987-10-21 テキサス　インスツルメンツ　インコ−ポレイテツド 多段並列バイナリイ加算器回路

Also Published As

Publication number Publication date
JPH0218499B2 (enrdf_load_stackoverflow) 1990-04-25

Similar Documents

Publication Publication Date Title
JP2636749B2 (ja) Ｘｏｒ回路と反転セレクタ回路及びこれらを用いた加算回路
US4297591A (en) Electronic counter for electrical digital pulses
JPS59123931A (ja) キヤリ−信号発生器
EP0224841B1 (en) Logic arithmetic circuit
JPS58209225A (ja) ３ステ−ト出力回路
JPH0355045B2 (enrdf_load_stackoverflow)
JP3137629B2 (ja) 桁上げ‐セーブ算術演算機構に対する加算器セル
KR100278992B1 (ko) 전가산기
KR940000267B1 (ko) 직렬 비교기 집적회로
JPH11163718A (ja) 論理ゲート
JPH0462499B2 (enrdf_load_stackoverflow)
JPS6442720A (en) Clock generating circuit
JPS62231521A (ja) 半導体集積回路
JPH0552688B2 (enrdf_load_stackoverflow)
JP2595272B2 (ja) ダイナミック型セット・リセットフリップフロップ
KR930010941B1 (ko) 전가산기 집적회로
JPS60170092A (ja) デコ−ド回路
JP2752778B2 (ja) 半導体集積回路
JPH03283815A (ja) 出力バッファ回路
JPH04290010A (ja) 論理回路
JPH02135815A (ja) 高低いずれかのレベルにおいて互いに重なりのない２相の論理信号を生じる回路
JPH0254617A (ja) 入出力バッファ回路
JPS595348A (ja) 全加算器
JPH02254814A (ja) ３ステート出力バッファ回路
JPS62186613A (ja) Ｃｍｏｓ選択回路