JPS5910229A - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法

Info

Publication number
JPS5910229A
JPS5910229A JP57118568A JP11856882A JPS5910229A JP S5910229 A JPS5910229 A JP S5910229A JP 57118568 A JP57118568 A JP 57118568A JP 11856882 A JP11856882 A JP 11856882A JP S5910229 A JPS5910229 A JP S5910229A
Authority
JP
Japan
Prior art keywords
pellet
gold
stem
gold foil
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57118568A
Other languages
English (en)
Inventor
Koji Kanzawa
神沢　孝治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57118568A priority Critical patent/JPS5910229A/ja
Publication of JPS5910229A publication Critical patent/JPS5910229A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/325—Material
    • H01L2224/32505—Material outside the bonding interface, e.g. in the bulk of the layer connector
    • H01L2224/32506—Material outside the bonding interface, e.g. in the bulk of the layer connector comprising an eutectic alloy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4823—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a pin of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/83805—Soldering or alloying involving forming a eutectic alloy at the bonding interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 本発明は半導体装置およびその製造方法に関する。
半導体装置の製造において、基板の主面にベレット（半
導体素子）を固定する工程がある。この場合、その接続
方法として基板とベレットとの間に金箔を介在させ、熱
圧着による金（Ａｕ）−シリコン（Ｓｉ）の共晶層によ
って接続化を図る方法がある。
基板がリードフレームの場合はリードフレームが薄い金
属板からなっていることから金箔をスポットウェルドに
よってリードフレームに固定することができる。このた
め、金箔の移動等は生じない。
しかし、第１図で示すようなステム１の中央窪部にガラ
ス２を充填した構造の基板３を用いて組み立てるキャン
封止型のトランジスタ４にあっては、スポットウェルド
による金箔のステム１への固定はできない。このため１
組立にあっては、ステム１の平坦面上に単に金箔を載置
するだけであり、金箔の位置が振動等の外力によってず
れてもわかりにくく修正はむずかしい。この結果、ベレ
ン、トの取付時に金箔がベレット５の下から部分的に外
れ、ベレット全域での接続ができなくなり、ペレット５
にクラックが発生したり、外観不良品と認定されたりし
て好ましくない。そこで、従来は金箔の大きさを必要以
上大きくして、金箔の位置がずれてもペレット下面全域
に金が濡れるようにしている。しかし、この場合であっ
ても、ステムの主面が平坦であることから、金箔が溶け
た際流れ出すため、金箔を大きくしてもペレット全域の
濡れを常に図ることは難しい。なお、図中６はペレット
５をステム１に固定するＡｕ−８ｉ共晶層、７はリード
、８はリード７とペレット５の電極を接続するワイヤ、
９はキャップである。
したがって、本発明の目的はペレット付けの歩留向上を
図るとともに、金箔の使用量の軽減が図れる半導体装置
およびその製造方法を提供することにある。
このような目的を達成するために本発明は、基板の主面
に金箔を載置した後、この金箔上にペレットを載せてペ
レットをこすり付けるとともに加熱してペレットを基板
に固定してなる半導体装置において、前記基板のペレッ
ト取付領域を金の流出防止およびペレットの位置決めを
図るようにあらかじめ一段と低い窪みとしておくととも
に、その後、窪み内に金箔を入れてペレットの固定を行
なうものである。
以下、実施例により本発明を説明する。
第２図は本発明の一実施例によるキャン封止型のトラン
ジスタ４を示す断面図である。このトランジスタ４の組
立にあっては、あらかじめ第３図で示すような構造の基
板３を用意する。すなわち、基板３は第１図で示すよう
な表面に金めつきを施した金属製のステムｌと、このス
テム１の下面中央部を窪むように成形した窪み部分に埋
め込んだガラス２とからなっている。また、ステム１に
は非接触で３本のり−ド７が貫通配設されるとともに、
このリード７はガラス２によって支持されている。また
、この実施例のステム１にあっては、ペレット５を固定
する領域が一段低い窪み１ｏとなっている。この窪み１
０はペレット５の太きさよりもわずかに大きい寸法とな
っている。そして、ペレット固定時には、この窪み１ｏ
内に窪み１゜と略同−寸法の金箔１１を入れた後、ステ
ム１を加熱すると同時に真空吸着工具１２の下端に保持
したペレット５を金箔１１上に載せ、かつこすり付ける
。この結果、熱によって溶は始めた金箔の金と、ペレッ
ト５を形作るシリコンとの間にＡｕ−８ｉ　の共晶化が
起き、ペレ・ソト５は第２図で示すようにＡｕ−８ｉ共
晶層６によってステムＩＫ固定される。そこで、ペレッ
ト５の電極とこれに対応するり−ド７の上端とをワイヤ
８で接続した後、キャップ９をリングシールによって基
板３に固定して気密封止を行ない、キャン封止型トラン
ジスタ４を製造する。
このような実施例によれば、ペレット取付時に金箔１１
は基板３の窪み１０内に供給される。したがって、摂動
等によってもこの窪み１０から金箔１１が跳び出すこと
は少なく金箔１１の位置決めが正確となる。また、金箔
１１を溶かした際、溶けた金は窪み１０内に位置し、こ
の窪み１０から外に流れ出すようなことはない。このた
め、ペレット付は時にペレット５の全域に亘って金が濡
れ、確実なペレットボンディングができるようになり、
部分的な接続に基因するペレットクラックの発生あるい
は外観検査時での不良数の軽減が図れ、歩留が向上する
。
また、金箔１１が部分的に窪み１０から外れるようなこ
とがあっても、金箔１１が溶けて溶融した金となった状
態で窪み１０に流れ込み易い。このようなことから、金
箔１１はペレット５の接続に際して最小限必要とする量
だけでよいことになるため、金箔１１の大きさは従来よ
りも小さくすることができるようになり、金箔使用量の
低減化を図ることができる。
なお、本発明は前記実施例に限定されない。また、本発
明は他の半導体装置の製造にも適用できる。
以上のように、本発明によれば、ペレットを正確確実に
基板に固定することができることから、信頼性の高いペ
レットボンディングが行なえるとともに１歩留の向上を
図ることができる。また。
金箔の使用量も軽減できることと和項って、ペレットボ
ンディング、換言すれば半導体装置のコストの低減も図
ることができる。
【図面の簡単な説明】
第１図は従来のキャン封止型トランジスタの断面図、 第２図は本発明の−・実施例によるキャン封止型トラン
ジスタの断面図、 第３図は同じ（ペレットボンディング工程における組立
状態を示す説明的断面図である。 １・・ステム、２・・・ガラス、３・・・基板、４・・
・トランジスタ、５・・・ベレット、６・・・Ａｕ　−
Ｓｉ　共晶層。 ７・・リード、８・・・ワイヤ、９・・・キャップ、１
０・・・窪み、１１・・金箔、１２・・・真空吸着工具
。

Claims (1)

  1. 【特許請求の範囲】 １、基板の主面に金−シリコン共晶により半導体ベレッ
    トを固定してなる半導体装置において、前記ペレット取
    付部の基板主面部分は窪んでいることを特徴とする半導
    体装置。 ２、基板の主面に金箔を載置した後、この金箔上にベレ
    ットを載せてベレットをこすり付けるとともに加熱して
    ベレットを基板に固定する半導体装置の製造方法におい
    て、前記基板のベレット取付領域を金の流出防止および
    ベレットの位置決めを図るようにあらかじめ一段と低い
    窪みとしておくとともに、その後１ｇみ内に金箔を入れ
    ベレットの固定を行なうことを特徴とする半導体装置の
    製造方法。
JP57118568A 1982-07-09 1982-07-09 半導体装置およびその製造方法 Pending JPS5910229A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57118568A JPS5910229A (ja) 1982-07-09 1982-07-09 半導体装置およびその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57118568A JPS5910229A (ja) 1982-07-09 1982-07-09 半導体装置およびその製造方法

Publications (1)

Publication Number Publication Date
JPS5910229A true JPS5910229A (ja) 1984-01-19

Family

ID=14739812

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57118568A Pending JPS5910229A (ja) 1982-07-09 1982-07-09 半導体装置およびその製造方法

Country Status (1)

Country Link
JP (1) JPS5910229A (ja)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6299268U (ja) * 1985-12-13 1987-06-24
JPS62111058U (ja) * 1985-12-28 1987-07-15
JPH0324168U (ja) * 1989-07-14 1991-03-13
JPH0383573U (ja) * 1989-09-11 1991-08-26
JPH041433U (ja) * 1990-04-19 1992-01-08
JPH07213662A (ja) * 1994-01-19 1995-08-15 Easton Aluminum Inc 模造木製複合ボールバット
JP2008207813A (ja) * 2007-02-23 2008-09-11 Iwaki Packs Kk 仕切体

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6299268U (ja) * 1985-12-13 1987-06-24
JPS62111058U (ja) * 1985-12-28 1987-07-15
JPH0324168U (ja) * 1989-07-14 1991-03-13
JPH0383573U (ja) * 1989-09-11 1991-08-26
JPH041433U (ja) * 1990-04-19 1992-01-08
JPH07213662A (ja) * 1994-01-19 1995-08-15 Easton Aluminum Inc 模造木製複合ボールバット
JP2008207813A (ja) * 2007-02-23 2008-09-11 Iwaki Packs Kk 仕切体

Similar Documents

Publication Publication Date Title
JPH09237806A (ja) 半導体装置とその製造方法及びこの半導体装置を用いた実装構造体とその製造方法
JPS5910229A (ja) 半導体装置およびその製造方法
KR100258050B1 (ko) 반도체 장치와 그 제조 방법 및 그에 사용되는 리드 프레임
IE54534B1 (en) Semiconductor device package
JPH01239958A (ja) 気密封止型半導体素子
KR19980079223A (ko) 반도체 장치 및 그의 제조 방법
JPH03108361A (ja) 半導体集積回路装置
JPH0126538B2 (ja)
JPH02137236A (ja) 樹脂封止型半導体装置の組立方法
JPS62128155A (ja) 半導体装置の製造方法
JPH0794674A (ja) 半導体装置およびその製造方法
JPS6330131Y2 (ja)
KR830002575B1 (ko) 기밀단자(氣密端子)의 제조방법
JPH041500B2 (ja)
JPH0744024Y2 (ja) 半導体セラミック・パッケージ用窓枠状ろう材付き封着板
JPS61156842A (ja) 半導体装置の製造方法
JPS63122250A (ja) 半導体装置
JP2543661Y2 (ja) マイクロ波トランジスタ
JPS6221254A (ja) 電子装置
JPH0513608A (ja) 半導体装置
JPH01238129A (ja) 樹脂封止型半導体装置
JPS63127540A (ja) 半導体装置
JPS5996742A (ja) 半田付け方法
JPH0974116A (ja) 半導体装置及び該半導体装置の製造方法
JPS606090B2 (ja) 半導体装置の製造方法