JPS5910068B2 - バイポ−ラ論理回路 - Google Patents
バイポ−ラ論理回路Info
- Publication number
- JPS5910068B2 JPS5910068B2 JP50118224A JP11822475A JPS5910068B2 JP S5910068 B2 JPS5910068 B2 JP S5910068B2 JP 50118224 A JP50118224 A JP 50118224A JP 11822475 A JP11822475 A JP 11822475A JP S5910068 B2 JPS5910068 B2 JP S5910068B2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- collector
- region
- emitter
- epitaxial layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
- H10D84/63—Combinations of vertical and lateral BJTs
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
- H03K19/091—Integrated injection logic or merged transistor logic
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
- H10D84/65—Integrated injection logic
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Bipolar Integrated Circuits (AREA)
- Logic Circuits (AREA)
- Bipolar Transistors (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19742446649 DE2446649A1 (de) | 1974-09-30 | 1974-09-30 | Bipolare logikschaltung |
| DE2446649 | 1974-09-30 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5161260A JPS5161260A (enrdf_load_stackoverflow) | 1976-05-27 |
| JPS5910068B2 true JPS5910068B2 (ja) | 1984-03-06 |
Family
ID=5927133
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP50118224A Expired JPS5910068B2 (ja) | 1974-09-30 | 1975-09-30 | バイポ−ラ論理回路 |
Country Status (8)
| Country | Link |
|---|---|
| JP (1) | JPS5910068B2 (enrdf_load_stackoverflow) |
| BE (1) | BE833958A (enrdf_load_stackoverflow) |
| CA (1) | CA1040319A (enrdf_load_stackoverflow) |
| DE (1) | DE2446649A1 (enrdf_load_stackoverflow) |
| FR (1) | FR2286557A1 (enrdf_load_stackoverflow) |
| GB (1) | GB1531735A (enrdf_load_stackoverflow) |
| IT (1) | IT1042857B (enrdf_load_stackoverflow) |
| NL (1) | NL7511516A (enrdf_load_stackoverflow) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2509530C2 (de) * | 1975-03-05 | 1985-05-23 | Ibm Deutschland Gmbh, 7000 Stuttgart | Halbleiteranordnung für die Grundbausteine eines hochintegrierbaren logischen Halbleiterschaltungskonzepts basierend auf Mehrfachkollektor-Umkehrtransistoren |
| DE2652103C2 (de) * | 1976-11-16 | 1982-10-28 | Ibm Deutschland Gmbh, 7000 Stuttgart | Integrierte Halbleiteranordnung für ein logisches Schaltungskonzept und Verfahren zu ihrer Herstellung |
| US4199776A (en) * | 1978-08-24 | 1980-04-22 | Rca Corporation | Integrated injection logic with floating reinjectors |
-
1974
- 1974-09-30 DE DE19742446649 patent/DE2446649A1/de not_active Ceased
-
1975
- 1975-09-11 GB GB37352/75A patent/GB1531735A/en not_active Expired
- 1975-09-25 IT IT27631/75A patent/IT1042857B/it active
- 1975-09-26 FR FR7529564A patent/FR2286557A1/fr active Granted
- 1975-09-29 CA CA236,643A patent/CA1040319A/en not_active Expired
- 1975-09-29 BE BE160491A patent/BE833958A/xx unknown
- 1975-09-30 JP JP50118224A patent/JPS5910068B2/ja not_active Expired
- 1975-09-30 NL NL7511516A patent/NL7511516A/xx not_active Application Discontinuation
Also Published As
| Publication number | Publication date |
|---|---|
| FR2286557B1 (enrdf_load_stackoverflow) | 1980-04-18 |
| DE2446649A1 (de) | 1976-04-15 |
| JPS5161260A (enrdf_load_stackoverflow) | 1976-05-27 |
| GB1531735A (en) | 1978-11-08 |
| CA1040319A (en) | 1978-10-10 |
| IT1042857B (it) | 1980-01-30 |
| FR2286557A1 (fr) | 1976-04-23 |
| BE833958A (fr) | 1976-01-16 |
| NL7511516A (nl) | 1976-04-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Hart et al. | Integrated injection logic: A new approach to LSI | |
| US3955210A (en) | Elimination of SCR structure | |
| US4220961A (en) | Monolithic combination of two complementary bipolar transistors | |
| JPS6132464A (ja) | Cmos型集積回路装置 | |
| US3947865A (en) | Collector-up semiconductor circuit structure for binary logic | |
| JPS5910068B2 (ja) | バイポ−ラ論理回路 | |
| Hewlett | Schottky I/sup 2/L | |
| GB1533156A (en) | Semiconductor integrated circuits | |
| CA1051982A (en) | Inverter stage in an integrated injection logic | |
| JPH044755B2 (enrdf_load_stackoverflow) | ||
| US5155572A (en) | Vertical isolated-collector PNP transistor structure | |
| JPS6352805B2 (enrdf_load_stackoverflow) | ||
| JPH0222405B2 (enrdf_load_stackoverflow) | ||
| JPH0493076A (ja) | 半導体集積回路装置 | |
| GB1446386A (en) | Single bipolar transistor memory cell and methods of operation and fabrication | |
| JPS5950224B2 (ja) | 半導体装置 | |
| JPH0456465B2 (enrdf_load_stackoverflow) | ||
| US5581096A (en) | Integrated semiconductor device having a thyristor | |
| JP3206149B2 (ja) | 絶縁ゲートバイポーラトランジスタ | |
| Klaassen | Physics of and models for I 2 L | |
| JP2525142B2 (ja) | 半導体集積回路 | |
| JPS6331110B2 (enrdf_load_stackoverflow) | ||
| JPS5845827B2 (ja) | 半導体集積回路 | |
| JPH0258870A (ja) | 半導体記憶装置 | |
| SU571155A1 (ru) | Интегральна схема |