CA1040319A - Bipolar logic circuit - Google Patents
Bipolar logic circuitInfo
- Publication number
- CA1040319A CA1040319A CA236,643A CA236643A CA1040319A CA 1040319 A CA1040319 A CA 1040319A CA 236643 A CA236643 A CA 236643A CA 1040319 A CA1040319 A CA 1040319A
- Authority
- CA
- Canada
- Prior art keywords
- doped
- transistor
- zone
- epitaxial layer
- logic circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
- H01L27/0821—Combination of lateral and vertical transistors only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
- H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
- H01L27/0233—Integrated injection logic structures [I2L]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
- H03K19/091—Integrated injection logic or merged transistor logic
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Bipolar Integrated Circuits (AREA)
- Logic Circuits (AREA)
- Bipolar Transistors (AREA)
Abstract
ABSTRACT
An integrated logic circuit has an epitaxial layer arranged on a substrate consisting of semiconductor material. An emitter zone, an output collector zone and at least one additional collector zone are provided in the epitaxial layer. A lateral pnp transistor and a vertical, inversely operated npn transistor are provided with the epitaxial and zone structure such that the emitter of the lateral transistor is connected to a supply line, the out-put collector of the lateral transistor is simultaneously the base of the ver-tical transistor, the collector terminals which represent the outputs of the vertical transistor are provided for taking off output signals and the supply potential is connected across the supply line and the epitaxial layer which contains the base terminal of the lateral transistor and the emitter terminal of the vertical transistor.
An integrated logic circuit has an epitaxial layer arranged on a substrate consisting of semiconductor material. An emitter zone, an output collector zone and at least one additional collector zone are provided in the epitaxial layer. A lateral pnp transistor and a vertical, inversely operated npn transistor are provided with the epitaxial and zone structure such that the emitter of the lateral transistor is connected to a supply line, the out-put collector of the lateral transistor is simultaneously the base of the ver-tical transistor, the collector terminals which represent the outputs of the vertical transistor are provided for taking off output signals and the supply potential is connected across the supply line and the epitaxial layer which contains the base terminal of the lateral transistor and the emitter terminal of the vertical transistor.
Description
This invention relates to a bipolar logic circuit of the integrated type in which an eyitaxial layer is arranged on a substrate consisting of semi-conductor material, wherein an emitter zone, and output collector zone and at least one additional collector zone are provided in the epitaxial layer.
Logic circuits of the type generally set forth above are known in the art. For examplel a bipolar CHL circuit is described in the publication "IEEE International Solid State Circuits Conference 1974 on Pages 18 and 19 under the title: "Current Hogging Logic-A New Logic for LSI With Noise Immunity" The CHL element represented therein in Figure 1 of basically a pnp transistor which includes an additional collector Cl between the emitter E
and the output collector C0. When current flows between the emitter and the output collector C0, the CHL element acts as a normal pnp transistor. If, however, the control collector Cl has a negative bias in respect of the emitter E, it withdraws the charge carriers which have previously accumulated on the output collector C0, and only a blocking current flows from the emitter E to the output collector CO.
Additional collectors C' are also provided, which collectors are connected to the substrate and which function to prevent charge carriers from diffusing off from the control collector Cl.
NOR and NAND gates can be constructed with the aid of such CHL
elements.
Also, the publication "Integrated Injection Logic: A New Approach To LSI", in the IEEE Journal of Solid State Circuits, Vol. SC-7, No, 5, October 1972, pp. 364-351 discloses functionally integrated I2L basic circuits having a lateral pnp transistor and a vertical, inversely operated npn transistor, I The object of the present invention is to further increase the in-
Logic circuits of the type generally set forth above are known in the art. For examplel a bipolar CHL circuit is described in the publication "IEEE International Solid State Circuits Conference 1974 on Pages 18 and 19 under the title: "Current Hogging Logic-A New Logic for LSI With Noise Immunity" The CHL element represented therein in Figure 1 of basically a pnp transistor which includes an additional collector Cl between the emitter E
and the output collector C0. When current flows between the emitter and the output collector C0, the CHL element acts as a normal pnp transistor. If, however, the control collector Cl has a negative bias in respect of the emitter E, it withdraws the charge carriers which have previously accumulated on the output collector C0, and only a blocking current flows from the emitter E to the output collector CO.
Additional collectors C' are also provided, which collectors are connected to the substrate and which function to prevent charge carriers from diffusing off from the control collector Cl.
NOR and NAND gates can be constructed with the aid of such CHL
elements.
Also, the publication "Integrated Injection Logic: A New Approach To LSI", in the IEEE Journal of Solid State Circuits, Vol. SC-7, No, 5, October 1972, pp. 364-351 discloses functionally integrated I2L basic circuits having a lateral pnp transistor and a vertical, inversely operated npn transistor, I The object of the present invention is to further increase the in-
2 tegration density in comparison to the known circuits of the prior art.
Thus, in accordance with the invention, there is provided a logic circuit comprising a substrate, an epitaxial layer carried on said substrate, - 1 ~
: i .. . .
)4(3319 . .
an emitter zone, an output collector zone and at least one additional collector zone in said epitaxial layer, a first transistor of one conductivity type and a second transistor of the opposite conductivity type defined by said epitaxial layer and said zones, each of said transistors including an emitter, a base, and at least one output collector, said first transistor also including at least one control collector for receiving control signals, a supply line car-ried on said epitaxial layer, said output collector of said first transistor connected to said base of said second transistor, said epitaxial layer forming said base of said first transistor and said emitter of said second transistor, and said emitter of said first transistor connected to said supply line, the output state of said output collector of said second transistor depending on the level of the control signals applied to said control with a supply pot-ential applied between said supply line and said epitaxial layer.
An essential advantage of the invention resides in the fact that only approximately 1/3 of the space requirement of conventional CHL arrange-ments is necessary, due to the substantial functional integration of the output stage.
Advantageously, in logic arrangements constructed in accordance with the invention, no separating diffusion processes or other insulation processes are required, such as is the case with respect to known CHL circuits.
The possibility of producing fundamental circuits also advantageous-ly results in a saving of space in comparison to the known I2L arrangements.
Other objects, features and advantages of the invention, its organization, construction and operation will be best understood from the following detailed description taken in conjunction with the accompanying drawings, on which:
Figure 1 is a schematic circuit diagram of a NOR gate having two outputs and constructed in accordance with the invention.
Figure 2 is a plan view of a design of the NOR gate illustrated in Figure l;
'S~æ ~ , , il~)4tl~319 Figure 3 is a schematic circuit diagram of a NOR gate constructed in accordance witll the invention in which two collectors are combined to form one diffusion zone; and Figure 4 is a plan view of the design of the circuit illustrated in Figure 3.
Referring to Figure 1, a NOR gate constructed in accordance with the invention is illustrated which comprises a lateral pnp transistor 1 and a vertical, inversely operated transistor 2. The emitter of the transistor 1 is con-~ , 1~)4t~319 V~
nected to a supply line 3. Preferably, a constant feed current is impressed ~, by way of the line 3. The base 12 of the transistor 1 is preferably connected ~, to ground potential. lhe transistor 1 is provided with control collectors 13 and 14 and an output collector 15. The output collector 15 is connected to the base of the transistor 2, as illustrated in Figure 1, and simultaneously forms the base of the npn transistor 2, as is illustrated in Figure 2 which will be , discussed below. The transistor 2 includes an emitter 23 which is also pre-;~ ferably connected to ground potential. The terminals 21 and 22 represent the outputs of the transistor 2, which in the following is referred to as the out-~; 10 put transistor.
Figure 2 represents the technological construction of the NOR gate illustrated in Figure 1. Preferably, an epitaxial layer 4 is arranged on a
Thus, in accordance with the invention, there is provided a logic circuit comprising a substrate, an epitaxial layer carried on said substrate, - 1 ~
: i .. . .
)4(3319 . .
an emitter zone, an output collector zone and at least one additional collector zone in said epitaxial layer, a first transistor of one conductivity type and a second transistor of the opposite conductivity type defined by said epitaxial layer and said zones, each of said transistors including an emitter, a base, and at least one output collector, said first transistor also including at least one control collector for receiving control signals, a supply line car-ried on said epitaxial layer, said output collector of said first transistor connected to said base of said second transistor, said epitaxial layer forming said base of said first transistor and said emitter of said second transistor, and said emitter of said first transistor connected to said supply line, the output state of said output collector of said second transistor depending on the level of the control signals applied to said control with a supply pot-ential applied between said supply line and said epitaxial layer.
An essential advantage of the invention resides in the fact that only approximately 1/3 of the space requirement of conventional CHL arrange-ments is necessary, due to the substantial functional integration of the output stage.
Advantageously, in logic arrangements constructed in accordance with the invention, no separating diffusion processes or other insulation processes are required, such as is the case with respect to known CHL circuits.
The possibility of producing fundamental circuits also advantageous-ly results in a saving of space in comparison to the known I2L arrangements.
Other objects, features and advantages of the invention, its organization, construction and operation will be best understood from the following detailed description taken in conjunction with the accompanying drawings, on which:
Figure 1 is a schematic circuit diagram of a NOR gate having two outputs and constructed in accordance with the invention.
Figure 2 is a plan view of a design of the NOR gate illustrated in Figure l;
'S~æ ~ , , il~)4tl~319 Figure 3 is a schematic circuit diagram of a NOR gate constructed in accordance witll the invention in which two collectors are combined to form one diffusion zone; and Figure 4 is a plan view of the design of the circuit illustrated in Figure 3.
Referring to Figure 1, a NOR gate constructed in accordance with the invention is illustrated which comprises a lateral pnp transistor 1 and a vertical, inversely operated transistor 2. The emitter of the transistor 1 is con-~ , 1~)4t~319 V~
nected to a supply line 3. Preferably, a constant feed current is impressed ~, by way of the line 3. The base 12 of the transistor 1 is preferably connected ~, to ground potential. lhe transistor 1 is provided with control collectors 13 and 14 and an output collector 15. The output collector 15 is connected to the base of the transistor 2, as illustrated in Figure 1, and simultaneously forms the base of the npn transistor 2, as is illustrated in Figure 2 which will be , discussed below. The transistor 2 includes an emitter 23 which is also pre-;~ ferably connected to ground potential. The terminals 21 and 22 represent the outputs of the transistor 2, which in the following is referred to as the out-~; 10 put transistor.
Figure 2 represents the technological construction of the NOR gate illustrated in Figure 1. Preferably, an epitaxial layer 4 is arranged on a
3 silicon substrate (not illustrated). It is preferable that a buried layer is arranged between the epitaxial layer 4 and the substrate in order to compensate potential differences in the epitaxial layer. Here, the epitaxial layer 4 simultaneously forms the base zone 12 of the lateral pnp transistor and the emitter zone 23 of the :vertical inverse npn output transistor. Preferably, the epitaxial layer 4 is~, n-doped. The p-doped zones contained in the epitaxial layer are provided with oblique shading. Zones illustrated with random dots are contact areas. Corresponding elements in Figures 1 and 2 carry correspon-ding reference characters.
Since, as is illustrated in Figure 1, both the base zone 12 of the lateral pnp transistor and the emitter zone 23 of the vertical output transis-tor carry the same potential, preferably ground potential, is advantageous that no mutual isolation of the components is required. This elimination of isolation, or the necessity for isolation, due to the structure of the inven-tion results in a space saving of approximately 70% in comparison to conven-tional CHl, circuits.
The collectors 6, which are preferably arranged in the epitaxial layer, serve to withdraw excess charge carriers. Preferably, these collectors t 1C~4~319 are connected to ground potential.
The mode of operation of the NOR gate constructed in accordance with the invention and as illustrated in Figures 1 and 2 will now be described. The emitter ll of the lateral pnp transistor 1 is connected, by way of the supply line 3, to a positive potential of a supply voltage. The base 12 of the tran- -sistor 1 and the emitter 23 of the output transistor 2 are connected to ground potential. When the supply voltage +UB is connected, the emitter 11 injects holes into the n-epitaxial layer which represents the base 12. These holes are at least partially withdrawn by the collector 13, as long as the potential thereof remains below the potential of the emitter 12. When the collector 13 is open, it is charged, due to the withdrawal of the holes, to positive poten-tial to such an extent that holes are re-injected into the epitaxial layer.
These holes are then withdrawn by the collector 14. When the collector 14 is open, charging and hole injection are again carried out so that for open col-lectors 13 and 14 there is a current flow to the collector 15.
Since the collector 15 simultaneously represents the base of the vertical npn output transistor 2, the current then flows to the ground terminal.
It can therefore be seen that for open collectors 13 and 14 the pnp transistor 1 is rendered conductive, and that the outputs 21 and 22 of the output transis-' 20 tor 2 are drawn to ground potential. However, as soon as either thecollector 13 or the collector 14 are connected to ground, and therefore assume current flow, the collector 15 is without current flow, and the output transistor 2 blocks, Therefore, only a blocking current ca~ flow by way of the outputs 21 and 22. The state of the outputs 21 and 22 (current and no current) corres-ponds to a NOR linking of the states of the collectors 13 and 14 which serve as inputs.
For the construction of a corresponding NOR gate with a lateral npn transistor with a vertical, inversely operated pnp transistor, all the doped layers and zones of the arrangement illustrated in Figures 1 and 2 obtain a doping of the opposite conductivity type.
-- . .
1~4(~319 In accordance with the publication mentioned above, the IEEE
International Solid State Circuits Conference, 1974, Pages 18 and 19, it is also possible to produce NAND gates by a suitable arrangement of the emitter zones. For example, in order to construct such a gate, in the instant Figure 1 the collector referenced 13 would be omitted and the collector referenced 14 would be divided into two collectors arranged next to one another This would correspond to the collectors Cl and C2 in Figure 2b of the aforementi.oned publication.
In the circuit illustrated in Figures 3 and 4, the collectors 14 and 15 of Figure 1 are combined to form a base zone 150 of the transistor 20 tFigure 3), in accordance with another development of the invention. This does not alter the function of the circuit, as the output transistor 20, as before, can be blocked due to a withdrawal of current from the collector 130 or from the collector 150 which is simultaneously the base zone of the transistor 20.
It is also preferable to provide collectors 60 which serve to with-draw excess charge carriers. Preferably, these collectors are connected to ground potential.
Although I have described my invention by reference to particular illustrative embodiments thereof, many changes and modifications of the inven-tion may become apparent to those skilled in the art without departing from the spirit and scope of the invention. I therefore intend to include within the patent warranted hereon all such changes and modifications as may reason-ably ant properly be included within the scope of my contribution to the art.
Since, as is illustrated in Figure 1, both the base zone 12 of the lateral pnp transistor and the emitter zone 23 of the vertical output transis-tor carry the same potential, preferably ground potential, is advantageous that no mutual isolation of the components is required. This elimination of isolation, or the necessity for isolation, due to the structure of the inven-tion results in a space saving of approximately 70% in comparison to conven-tional CHl, circuits.
The collectors 6, which are preferably arranged in the epitaxial layer, serve to withdraw excess charge carriers. Preferably, these collectors t 1C~4~319 are connected to ground potential.
The mode of operation of the NOR gate constructed in accordance with the invention and as illustrated in Figures 1 and 2 will now be described. The emitter ll of the lateral pnp transistor 1 is connected, by way of the supply line 3, to a positive potential of a supply voltage. The base 12 of the tran- -sistor 1 and the emitter 23 of the output transistor 2 are connected to ground potential. When the supply voltage +UB is connected, the emitter 11 injects holes into the n-epitaxial layer which represents the base 12. These holes are at least partially withdrawn by the collector 13, as long as the potential thereof remains below the potential of the emitter 12. When the collector 13 is open, it is charged, due to the withdrawal of the holes, to positive poten-tial to such an extent that holes are re-injected into the epitaxial layer.
These holes are then withdrawn by the collector 14. When the collector 14 is open, charging and hole injection are again carried out so that for open col-lectors 13 and 14 there is a current flow to the collector 15.
Since the collector 15 simultaneously represents the base of the vertical npn output transistor 2, the current then flows to the ground terminal.
It can therefore be seen that for open collectors 13 and 14 the pnp transistor 1 is rendered conductive, and that the outputs 21 and 22 of the output transis-' 20 tor 2 are drawn to ground potential. However, as soon as either thecollector 13 or the collector 14 are connected to ground, and therefore assume current flow, the collector 15 is without current flow, and the output transistor 2 blocks, Therefore, only a blocking current ca~ flow by way of the outputs 21 and 22. The state of the outputs 21 and 22 (current and no current) corres-ponds to a NOR linking of the states of the collectors 13 and 14 which serve as inputs.
For the construction of a corresponding NOR gate with a lateral npn transistor with a vertical, inversely operated pnp transistor, all the doped layers and zones of the arrangement illustrated in Figures 1 and 2 obtain a doping of the opposite conductivity type.
-- . .
1~4(~319 In accordance with the publication mentioned above, the IEEE
International Solid State Circuits Conference, 1974, Pages 18 and 19, it is also possible to produce NAND gates by a suitable arrangement of the emitter zones. For example, in order to construct such a gate, in the instant Figure 1 the collector referenced 13 would be omitted and the collector referenced 14 would be divided into two collectors arranged next to one another This would correspond to the collectors Cl and C2 in Figure 2b of the aforementi.oned publication.
In the circuit illustrated in Figures 3 and 4, the collectors 14 and 15 of Figure 1 are combined to form a base zone 150 of the transistor 20 tFigure 3), in accordance with another development of the invention. This does not alter the function of the circuit, as the output transistor 20, as before, can be blocked due to a withdrawal of current from the collector 130 or from the collector 150 which is simultaneously the base zone of the transistor 20.
It is also preferable to provide collectors 60 which serve to with-draw excess charge carriers. Preferably, these collectors are connected to ground potential.
Although I have described my invention by reference to particular illustrative embodiments thereof, many changes and modifications of the inven-tion may become apparent to those skilled in the art without departing from the spirit and scope of the invention. I therefore intend to include within the patent warranted hereon all such changes and modifications as may reason-ably ant properly be included within the scope of my contribution to the art.
Claims (15)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A logic circuit comprising a substrate, an epitaxial layer carried on said substrate, an emitter zone, an output collector zone and at least one additional collector zone in said epitaxial layer, a first transistor of one conductivity type and a second transistor of the opposite conductivity type defined by said epitaxial layer and said zones, each of said transistors in-cluding an emitter, a base, and at least one output collector, said first transistor also including at least one control collector for receiving control signals, a supply line carried on said epitaxial layer, said output collector of said first transistor connected to said base of said second transistor, said epitaxial layer forming said base of said first transistor and said emit-ter of said second transistor, and said emitter of said first transistor con-nected to said supply line, the output state of said output collector of said second transistor depending on the level of the control signals applied to said control with a supply potential applied between said supply line and said epitaxial layer.
2. The logic circuit of claim 1, wherein said substrate is a p-conduc-tive substrate, said epitaxial layer is an n-conductive layer, said first tran-sistor is a pnp transistor arranged in said epitaxial layer including a p-doped emitter zone, a p-doped first control collector zone, a p-doped second control collector zone and a p-doped output collector zone in said n-conductive epi-taxial layer, said second transistor is an npn transistor arranged in said epitaxial layer including an n-doped first output collector zone and an n-doped second output collector zone in said p-doped output collector zone of said first transistor, and contacts carried by said p-doped and n-doped zones, said n-conductive epitaxial layer constituting said base of said first transistor and said emitter of said second transistor.
3. The logic circuit of claim 2, comprising a pair of p-doped zones in said n-conductive epitaxial layer located on opposite sides of said logic cir-cuit to shield said n-doped zones and p-doped zones of said first and second transistors.
4. The logic circuit of claim 1 wherein said epitaxial layer is an n-conductive layer, a p-doped emitter zone, a p-doped collector zone and a p-doped additional zone are provided in said n-epitaxial layer, n-doped terminal zones are disposed in said p-doped additional zone, said p-doped additional zone simultaneously serving as an output collector zone and a control collector zone, said p-doped emitter zone connected to said supply line, and said n-epitaxial layer simultaneously forming the base terminal of the first transis-tor and the emitter terminal of the second transistor.
5. The logic circuit of claim 4, comprising a pair of p-doped collec-tor zones in said n-epitaxial layer located on opposite sides of said logic circuit to shield said p-doped and n-doped zones.
6. The logic circuit of claim 1, wherein said substrate and said epi-taxial layer consist of silicon.
7. The logic circuit of claim 1, wherein said supply line consists of aluminum.
8. The logic circuit of claim 1, wherein said output collector zone is divided into two collector zones arranged next to one another at right angles to the current direction.
9. The logic circuit of claim 1, wherein said substrate is an n-conduc-tive substrate, said epitaxial layer is a p-conductive layer, said first tran-sistor is an npn transistor arranged in said epitaxial layer including an n-doped emitter zone, an n-doped first control collector zone, an n-doped second control collector zone and an n-doped output collector zone in said p-conduc-tive epitaxial layer, said second transistor is a pnp transistor arranged in said epitaxial layer including a p-doped first output collector zone and a p-doped second output collector zone in said n-doped output collector zone of said first transistor, and contacts carried by said n-doped and p-doped zones, said p-conductive epitaxial layer constituting said base of said first tran-sistor and said emitter of said second transistor.
10. The logic circuit of claim 9, comprising a pair of n-doped zones in said p-conductive epitaxial layer located on opposite sides of said logic cir-cuit to shield said p-doped zones and n-doped zones of said first and second transistors.
11. The logic circuit of claim l wherein said epitaxial layer is a p-conductive layer, an n-doped emitter zone, an n-doped collector zone and an n-doped additional zone are provided in said p-epitaxial layer, p-doped ter-minal zones are disposed in said n-doped additional zone, said n-doped addi-tional zone simultaneously serving as an output collector zone and a control collector zone, said n-doped emitter zone connected to said supply line, and said p-epitaxial layer simultaneously forming the base terminal of the first transistor and the emitter terminal of the second transistor.
12. The logic circuit of claim 11, comprising a pair of n-doped collec-tor zones in said p-epitaxial layer located on opposite sides of said logic circuit to shield said p-doped and n-doped zones.
13. The logic circuit of claim 1, wherein said substrate and said epi-taxial layer consist of silicon.
14. The logic circuit of claim 1, wherein said supply line consists of aluminum.
15. The logic circuit of claim 1, wherein said output collector zone is divided into two collector zones arranged next to one another at right an-gles to the current direction.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19742446649 DE2446649A1 (en) | 1974-09-30 | 1974-09-30 | BIPOLAR LOGIC CIRCUIT |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1040319A true CA1040319A (en) | 1978-10-10 |
Family
ID=5927133
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA236,643A Expired CA1040319A (en) | 1974-09-30 | 1975-09-29 | Bipolar logic circuit |
Country Status (8)
| Country | Link |
|---|---|
| JP (1) | JPS5910068B2 (en) |
| BE (1) | BE833958A (en) |
| CA (1) | CA1040319A (en) |
| DE (1) | DE2446649A1 (en) |
| FR (1) | FR2286557A1 (en) |
| GB (1) | GB1531735A (en) |
| IT (1) | IT1042857B (en) |
| NL (1) | NL7511516A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2509530C2 (en) * | 1975-03-05 | 1985-05-23 | Ibm Deutschland Gmbh, 7000 Stuttgart | Semiconductor arrangement for the basic building blocks of a highly integrable logic semiconductor circuit concept based on multiple collector reversing transistors |
| DE2652103C2 (en) * | 1976-11-16 | 1982-10-28 | Ibm Deutschland Gmbh, 7000 Stuttgart | Integrated semiconductor arrangement for a logical circuit concept and method for their production |
| US4199776A (en) * | 1978-08-24 | 1980-04-22 | Rca Corporation | Integrated injection logic with floating reinjectors |
| JPS6255688A (en) * | 1985-09-04 | 1987-03-11 | 茨城トヨペット株式会社 | Car driving training apparatus |
-
1974
- 1974-09-30 DE DE19742446649 patent/DE2446649A1/en not_active Ceased
-
1975
- 1975-09-11 GB GB3735275A patent/GB1531735A/en not_active Expired
- 1975-09-25 IT IT2763175A patent/IT1042857B/en active
- 1975-09-26 FR FR7529564A patent/FR2286557A1/en active Granted
- 1975-09-29 CA CA236,643A patent/CA1040319A/en not_active Expired
- 1975-09-29 BE BE160491A patent/BE833958A/en unknown
- 1975-09-30 JP JP50118224A patent/JPS5910068B2/en not_active Expired
- 1975-09-30 NL NL7511516A patent/NL7511516A/en not_active Application Discontinuation
Also Published As
| Publication number | Publication date |
|---|---|
| NL7511516A (en) | 1976-04-01 |
| FR2286557A1 (en) | 1976-04-23 |
| JPS5910068B2 (en) | 1984-03-06 |
| IT1042857B (en) | 1980-01-30 |
| JPS5161260A (en) | 1976-05-27 |
| BE833958A (en) | 1976-01-16 |
| GB1531735A (en) | 1978-11-08 |
| DE2446649A1 (en) | 1976-04-15 |
| FR2286557B1 (en) | 1980-04-18 |
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