JPS589285A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS589285A
JPS589285A JP56106498A JP10649881A JPS589285A JP S589285 A JPS589285 A JP S589285A JP 56106498 A JP56106498 A JP 56106498A JP 10649881 A JP10649881 A JP 10649881A JP S589285 A JPS589285 A JP S589285A
Authority
JP
Japan
Prior art keywords
input
circuit
output
precharge
row
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56106498A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0373080B2 (de
Inventor
Kiyobumi Ochii
落井　清文
Hiroshi Iwahashi
岩橋　弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56106498A priority Critical patent/JPS589285A/ja
Priority to US06/395,342 priority patent/US4528646A/en
Priority to EP82303540A priority patent/EP0069588B1/de
Priority to DE8282303540T priority patent/DE3279429D1/de
Publication of JPS589285A publication Critical patent/JPS589285A/ja
Publication of JPH0373080B2 publication Critical patent/JPH0373080B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Read Only Memory (AREA)
JP56106498A 1981-07-08 1981-07-08 半導体装置 Granted JPS589285A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP56106498A JPS589285A (ja) 1981-07-08 1981-07-08 半導体装置
US06/395,342 US4528646A (en) 1981-07-08 1982-07-06 Semiconductor memory with selectively enabled precharge and sense amplifier circuits
EP82303540A EP0069588B1 (de) 1981-07-08 1982-07-06 Integrierte Halbleiterspeicherschaltung
DE8282303540T DE3279429D1 (en) 1981-07-08 1982-07-06 Semiconductor integrated memory circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56106498A JPS589285A (ja) 1981-07-08 1981-07-08 半導体装置

Publications (2)

Publication Number Publication Date
JPS589285A true JPS589285A (ja) 1983-01-19
JPH0373080B2 JPH0373080B2 (de) 1991-11-20

Family

ID=14435094

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56106498A Granted JPS589285A (ja) 1981-07-08 1981-07-08 半導体装置

Country Status (4)

Country Link
US (1) US4528646A (de)
EP (1) EP0069588B1 (de)
JP (1) JPS589285A (de)
DE (1) DE3279429D1 (de)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60501233A (ja) * 1983-05-05 1985-08-01 モトロ−ラ・インコ−ポレ−テツド ランダム・アクセス・メモリ
JPH02146183A (ja) * 1988-11-28 1990-06-05 Nec Corp 半導体装置
JPH0636556A (ja) * 1992-07-16 1994-02-10 Nec Corp ダイナミックｒａｍ

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS618796A (ja) * 1984-06-20 1986-01-16 Nec Corp ダイナミツクメモリ
US4698788A (en) * 1985-07-01 1987-10-06 Motorola, Inc. Memory architecture with sub-arrays
US4740921A (en) * 1985-10-04 1988-04-26 Motorola, Inc. Precharge of a dram data line to an intermediate voltage
JPH0778993B2 (ja) * 1985-11-05 1995-08-23 株式会社日立製作所 半導体メモリ
USRE34463E (en) * 1985-12-06 1993-11-30 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device with active pull up
JPH0640439B2 (ja) * 1986-02-17 1994-05-25 日本電気株式会社 半導体記憶装置
KR880008330A (ko) * 1986-12-30 1988-08-30 강진구 스테이틱 램의 프리차아지 시스템
JPH07107797B2 (ja) * 1987-02-10 1995-11-15 三菱電機株式会社 ダイナミツクランダムアクセスメモリ
JPH01294295A (ja) * 1988-05-20 1989-11-28 Fujitsu Ltd パーシャル・ランダム・アクセス・メモリ
US4969125A (en) * 1989-06-23 1990-11-06 International Business Machines Corporation Asynchronous segmented precharge architecture
US5022010A (en) * 1989-10-30 1991-06-04 International Business Machines Corporation Word decoder for a memory array
DE69023456T2 (de) * 1989-10-30 1996-06-20 Ibm Bitdekodierungsschema für Speichermatrizen.
EP0455834A4 (en) * 1989-11-21 1992-06-03 Fujitsu Limited Sense amplifier control circuit
US5281873A (en) * 1989-11-21 1994-01-25 Fujitsu Limited Sense amplifier control circuit
US6751696B2 (en) 1990-04-18 2004-06-15 Rambus Inc. Memory device having a programmable register
IL96808A (en) 1990-04-18 1996-03-31 Rambus Inc Introductory / Origin Circuit Agreed Using High-Performance Brokerage
WO1991018394A1 (en) * 1990-05-17 1991-11-28 International Business Machines Corporation Read/write/restore circuit for memory arrays
JP2630059B2 (ja) * 1990-11-09 1997-07-16 日本電気株式会社 半導体メモリ装置
US5280452A (en) * 1991-07-12 1994-01-18 International Business Machines Corporation Power saving semsing circuits for dynamic random access memory
KR950004853B1 (ko) * 1991-08-14 1995-05-15 삼성전자 주식회사 저전력용 블럭 선택 기능을 가지는 반도체 메모리 장치
JPH05234366A (ja) * 1992-02-25 1993-09-10 Mitsubishi Electric Corp 半導体記憶装置
US5270591A (en) * 1992-02-28 1993-12-14 Xerox Corporation Content addressable memory architecture and circuits
US5729501A (en) * 1995-09-08 1998-03-17 International Business Machines Corporation High Speed SRAM with or-gate sense
US5836007A (en) * 1995-09-14 1998-11-10 International Business Machines Corporation Methods and systems for improving memory component size and access speed including splitting bit lines and alternate pre-charge/access cycles
KR100270006B1 (ko) * 1996-12-23 2000-12-01 포만 제프리 엘 다수의액세스값을기억하고액세스하기위한장치및그복원방법
US7622986B2 (en) 2005-08-26 2009-11-24 Micron Technology, Inc. High performance input receiver circuit for reduced-swing inputs
US8279659B2 (en) * 2009-11-12 2012-10-02 Qualcomm Incorporated System and method of operating a memory device
US10923185B2 (en) * 2019-06-04 2021-02-16 Qualcomm Incorporated SRAM with burst mode operation

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55135392A (en) * 1979-04-04 1980-10-22 Nec Corp Memory circuit
JPS5619584A (en) * 1979-07-24 1981-02-24 Chiyou Lsi Gijutsu Kenkyu Kumiai Semiconductor memory
JPS5647996A (en) * 1979-09-20 1981-04-30 Chiyou Lsi Gijutsu Kenkyu Kumiai Semiconductor memory device

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3613055A (en) * 1969-12-23 1971-10-12 Andrew G Varadi Read-only memory utilizing service column switching techniques
US3969706A (en) * 1974-10-08 1976-07-13 Mostek Corporation Dynamic random access memory misfet integrated circuit
JPS592996B2 (ja) * 1976-05-24 1984-01-21 株式会社日立製作所 半導体記憶回路
JPS6013214B2 (ja) * 1976-12-08 1985-04-05 株式会社日立製作所 半導体記憶装置
JPS5399736A (en) * 1977-02-10 1978-08-31 Toshiba Corp Semiconductor memory unit
DE2712735B1 (de) * 1977-03-23 1978-09-14 Ibm Deutschland Lese-/Schreibzugriffschaltung zu Speicherzellen eines Speichers und Verfahren zu ihrem Betrieb
JPS599990B2 (ja) * 1978-07-25 1984-03-06 超エル・エス・アイ技術研究組合 半導体記憶装置
US4222112A (en) * 1979-02-09 1980-09-09 Bell Telephone Laboratories, Incorporated Dynamic RAM organization for reducing peak current
JPS55132589A (en) * 1979-03-30 1980-10-15 Fujitsu Ltd Semiconductor memory unit
US4318014A (en) * 1979-07-27 1982-03-02 Motorola, Inc. Selective precharge circuit for read-only-memory
US4263664A (en) * 1979-08-31 1981-04-21 Xicor, Inc. Nonvolatile static random access memory system
US4447895A (en) * 1979-10-04 1984-05-08 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor memory device
US4350992A (en) * 1979-10-05 1982-09-21 Texas Instruments Incorporated N-Channel silicon gate virtual ground ROM
JPS6027113B2 (ja) * 1980-02-13 1985-06-27 日本電気株式会社 プリチャ−ジ装置
JPS5836504B2 (ja) * 1980-02-22 1983-08-09 富士通株式会社 半導体記憶装置
JPS5857838B2 (ja) * 1980-12-29 1983-12-22 富士通株式会社 デコ−ド回路
US4405996A (en) * 1981-02-06 1983-09-20 Rca Corporation Precharge with power conservation

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55135392A (en) * 1979-04-04 1980-10-22 Nec Corp Memory circuit
JPS5619584A (en) * 1979-07-24 1981-02-24 Chiyou Lsi Gijutsu Kenkyu Kumiai Semiconductor memory
JPS5647996A (en) * 1979-09-20 1981-04-30 Chiyou Lsi Gijutsu Kenkyu Kumiai Semiconductor memory device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60501233A (ja) * 1983-05-05 1985-08-01 モトロ−ラ・インコ−ポレ−テツド ランダム・アクセス・メモリ
JPH02146183A (ja) * 1988-11-28 1990-06-05 Nec Corp 半導体装置
JPH0636556A (ja) * 1992-07-16 1994-02-10 Nec Corp ダイナミックｒａｍ

Also Published As

Publication number Publication date
EP0069588A2 (de) 1983-01-12
DE3279429D1 (en) 1989-03-09
JPH0373080B2 (de) 1991-11-20
EP0069588A3 (en) 1985-05-15
US4528646A (en) 1985-07-09
EP0069588B1 (de) 1989-02-01

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