JPS5868033U - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS5868033U
JPS5868033U JP1981162394U JP16239481U JPS5868033U JP S5868033 U JPS5868033 U JP S5868033U JP 1981162394 U JP1981162394 U JP 1981162394U JP 16239481 U JP16239481 U JP 16239481U JP S5868033 U JPS5868033 U JP S5868033U
Authority
JP
Japan
Prior art keywords
thickness
insulating layer
oxide insulating
semiconductor device
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1981162394U
Other languages
English (en)
Inventor
富永　保
Original Assignee
日産自動車株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日産自動車株式会社 filed Critical 日産自動車株式会社
Priority to JP1981162394U priority Critical patent/JPS5868033U/ja
Publication of JPS5868033U publication Critical patent/JPS5868033U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は従来の半導体装置を示す断面図。第２図イ９口
は本考案の第１の実施例を示し、イは平面図、口はイの
Ａ−Ａ断面図。第３図ａ”−ｇは本考案の半導体装置を
製造する工程を示す説明図。 第４図イは本考案と従来の半導体装置の耐圧特性を示す
説明図。第４図用よ第４図イの試験用高周波サージ電圧
を示し、第４図ハは本考案の試験用サンプルを示す説明
図。第５図は本考案の他の実施例を示す断面図。 符号の説明、１・・・入力パッド、２・・・多結晶シリ
コン抵抗層、３．４・・・コンタクトホール、５・・・
金属配線、９・・・シリコン酸化物層の入力パッド周囲
輪郭部分、１０・・・入力部のシリラン酸化物層、１１
・・・シリコン酸化物層、１２・・・シリコン基板。

Claims (1)

  1. 【実用新案登録請求の範囲】 入力パッドおよび入力保護抵抗を有する半導体素子入力
    部の基板酸化物絶縁層の厚さを該入力部以外の基板酸化
    物絶縁層の厚さより大にした半導体装置において、 前記半導体素子入力部の基板酸化物絶縁層が半導体基板
    との熱膨張伸縮差によって生じるクラックにより耐圧低
    下しない厚さを有し、前記入力パッド周囲輪郭部分にお
    いて厚さが増大されていることを特徴とする半導体装置
    。
JP1981162394U 1981-10-30 1981-10-30 半導体装置 Pending JPS5868033U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1981162394U JPS5868033U (ja) 1981-10-30 1981-10-30 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1981162394U JPS5868033U (ja) 1981-10-30 1981-10-30 半導体装置

Publications (1)

Publication Number Publication Date
JPS5868033U true JPS5868033U (ja) 1983-05-09

Family

ID=29954709

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981162394U Pending JPS5868033U (ja) 1981-10-30 1981-10-30 半導体装置

Country Status (1)

Country Link
JP (1) JPS5868033U (ja)

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