JPS60149136U - 集積回路素子 - Google Patents
集積回路素子Info
- Publication number
- JPS60149136U JPS60149136U JP3616384U JP3616384U JPS60149136U JP S60149136 U JPS60149136 U JP S60149136U JP 3616384 U JP3616384 U JP 3616384U JP 3616384 U JP3616384 U JP 3616384U JP S60149136 U JPS60149136 U JP S60149136U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- circuit elements
- chip
- main surface
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
め要約のデータは記録されません。
Description
は本考案の一実施例の要部断面図、第2図すは試験電極
部の部分拡大平面図である。 1、 2.3・・・・・・機能ブロック、4・・・・・
・外部端子に接続される電−15・・・・・・機能ブロ
ック電極、6.6′・・・・・・配線、7,8・・・・
・・試験電極、10・・・・・・半導体基板、11・・
・・・・拡散層、12・・・・・・外部端子に接続され
る電極、13・・・・・・第1配線層、14
゛・・・・・・層間絶縁膜、15・・・・・・第2配線
層、15′・・・・・・機能ブロック間の結合配線、1
6・・・・・・表面保護膜ミ 17・・・・・・試験電
極、18・・・・・・機能ブロック境目、19・・・・
・・探針。
部の部分拡大平面図である。 1、 2.3・・・・・・機能ブロック、4・・・・・
・外部端子に接続される電−15・・・・・・機能ブロ
ック電極、6.6′・・・・・・配線、7,8・・・・
・・試験電極、10・・・・・・半導体基板、11・・
・・・・拡散層、12・・・・・・外部端子に接続され
る電極、13・・・・・・第1配線層、14
゛・・・・・・層間絶縁膜、15・・・・・・第2配線
層、15′・・・・・・機能ブロック間の結合配線、1
6・・・・・・表面保護膜ミ 17・・・・・・試験電
極、18・・・・・・機能ブロック境目、19・・・・
・・探針。
Claims (1)
- 主表面上の外端部に電極を有する多層配線構造のICチ
ップにおいて、任意の層の配線と接続された電極をIC
チップの主表面の最上層の任意の位置に形成し試験電極
としたことを特徴とする集積回路素子。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3616384U JPS60149136U (ja) | 1984-03-14 | 1984-03-14 | 集積回路素子 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3616384U JPS60149136U (ja) | 1984-03-14 | 1984-03-14 | 集積回路素子 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60149136U true JPS60149136U (ja) | 1985-10-03 |
Family
ID=30541100
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3616384U Pending JPS60149136U (ja) | 1984-03-14 | 1984-03-14 | 集積回路素子 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60149136U (ja) |
-
1984
- 1984-03-14 JP JP3616384U patent/JPS60149136U/ja active Pending
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