JPS5864840A - デ−タ同期回路 - Google Patents

デ−タ同期回路

Info

Publication number
JPS5864840A
JPS5864840A JP56162837A JP16283781A JPS5864840A JP S5864840 A JPS5864840 A JP S5864840A JP 56162837 A JP56162837 A JP 56162837A JP 16283781 A JP16283781 A JP 16283781A JP S5864840 A JPS5864840 A JP S5864840A
Authority
JP
Japan
Prior art keywords
output
circuit
edge
signal
falling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56162837A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0415649B2 (enrdf_load_stackoverflow
Inventor
Takao Arai
孝雄 荒井
Eiji Okubo
大久保 栄治
Hiroshi Endo
浩 遠藤
Masaharu Kobayashi
正治 小林
Takashi Takeuchi
崇 竹内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56162837A priority Critical patent/JPS5864840A/ja
Priority to US06/422,190 priority patent/US4611335A/en
Priority to GB08227465A priority patent/GB2109203B/en
Priority to DE19823236311 priority patent/DE3236311A1/de
Publication of JPS5864840A publication Critical patent/JPS5864840A/ja
Publication of JPH0415649B2 publication Critical patent/JPH0415649B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/04Speed or phase control by synchronisation signals
    • H04L7/041Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/042Detectors therefor, e.g. correlators, state machines

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP56162837A 1981-09-30 1981-10-14 デ−タ同期回路 Granted JPS5864840A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP56162837A JPS5864840A (ja) 1981-10-14 1981-10-14 デ−タ同期回路
US06/422,190 US4611335A (en) 1981-09-30 1982-09-23 Digital data synchronizing circuit
GB08227465A GB2109203B (en) 1981-09-30 1982-09-27 Digital data synchronizing circuit
DE19823236311 DE3236311A1 (de) 1981-09-30 1982-09-30 Datensynchronisierer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56162837A JPS5864840A (ja) 1981-10-14 1981-10-14 デ−タ同期回路

Publications (2)

Publication Number Publication Date
JPS5864840A true JPS5864840A (ja) 1983-04-18
JPH0415649B2 JPH0415649B2 (enrdf_load_stackoverflow) 1992-03-18

Family

ID=15762182

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56162837A Granted JPS5864840A (ja) 1981-09-30 1981-10-14 デ−タ同期回路

Country Status (1)

Country Link
JP (1) JPS5864840A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0597372A3 (en) * 1992-11-11 1996-05-15 Hitachi Ltd Devices for reproducing a digital signal, integrated circuits therefor and methods for reproducing a digital signal.

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0597372A3 (en) * 1992-11-11 1996-05-15 Hitachi Ltd Devices for reproducing a digital signal, integrated circuits therefor and methods for reproducing a digital signal.

Also Published As

Publication number Publication date
JPH0415649B2 (enrdf_load_stackoverflow) 1992-03-18

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