JPS57116459A - Clock regenerating circuit - Google Patents
Clock regenerating circuitInfo
- Publication number
- JPS57116459A JPS57116459A JP56002688A JP268881A JPS57116459A JP S57116459 A JPS57116459 A JP S57116459A JP 56002688 A JP56002688 A JP 56002688A JP 268881 A JP268881 A JP 268881A JP S57116459 A JPS57116459 A JP S57116459A
- Authority
- JP
- Japan
- Prior art keywords
- clock
- output
- circuit
- phase
- inverted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
PURPOSE:To obtain data possibly precise until a phase locked loop is surely synchronized, by switching to a clock reversed in phase to a present regenerated clock when there is phase slip, and by using it as a lock for regeneration. CONSTITUTION:The output of a clock synchronizing circuit 4 is sent to a clock selecting circuit 5 to extract an output clock or its inverted clock (c) selectively, and the clock is sent to an output terminal 3. When there is a phase slip and the digit of digital input data right after it has a ''1'', the output of the FF63 of a phase slip detecting circuit 6 is inverted and at its Q' output terminal, an output (g) with the ''1'' showing the detection of the phase slip appears. A change in the signal inverts the output of the FF71 of a clock selection-signal generating circuit 7 and an output (h) from the output terminal Q goes up to the ''1'' while the output (i) from the terminal Q' is inverted to a ''0''. Consequently, the AND circuit 53 of the circuit 5 is closed and an AND circuit 52 is opened to obtain a clock (c), obtained by inverting the output clock (b) of the circuit 4, as a regenerated clock.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56002688A JPS57116459A (en) | 1981-01-13 | 1981-01-13 | Clock regenerating circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56002688A JPS57116459A (en) | 1981-01-13 | 1981-01-13 | Clock regenerating circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57116459A true JPS57116459A (en) | 1982-07-20 |
Family
ID=11536217
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56002688A Pending JPS57116459A (en) | 1981-01-13 | 1981-01-13 | Clock regenerating circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57116459A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0477916A2 (en) * | 1990-09-28 | 1992-04-01 | Hitachi, Ltd. | Clock generating apparatus, data transmitting/receiving apparatus and data transmitting/receiving method |
-
1981
- 1981-01-13 JP JP56002688A patent/JPS57116459A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0477916A2 (en) * | 1990-09-28 | 1992-04-01 | Hitachi, Ltd. | Clock generating apparatus, data transmitting/receiving apparatus and data transmitting/receiving method |
US5379325A (en) * | 1990-09-28 | 1995-01-03 | Hitachi, Ltd. | Clock generating apparatus, data transmitting/receiving apparatus and data transmitting/receiving method |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS5580867A (en) | Block synchronous signal extracting circuit | |
GB1264024A (en) | Frame synchronisation system | |
ES482447A1 (en) | Timing-phase recovery circuit | |
JPS54102811A (en) | Signal system | |
JPS54148412A (en) | Reproduction system for timing information | |
JPS5797751A (en) | Circuit for adding artificial synchronizing signal | |
JPS5360150A (en) | Instantaneous leading-in system for digital phase lock loop | |
JPS57116459A (en) | Clock regenerating circuit | |
JPS53136424A (en) | Correlative processing system for picture signal | |
JPS56114461A (en) | Timing extracting circuit | |
JPS5461406A (en) | Pulse delivery system | |
JPS576423A (en) | Demodulating circuit of mfm modulation signal | |
JPS5232655A (en) | Logic low-pass filter circuit | |
JPS5371519A (en) | Error compensating unit for time axis | |
JPS54148413A (en) | Reproduction system for timing information | |
JPS5430060A (en) | Dislocation detecting circuit | |
JPS57143963A (en) | Data detector | |
JPS5556226A (en) | Multi-function key input circuit | |
JPS5781752A (en) | Demodulating circuit for transmission system of same direction data | |
JPS5448473A (en) | Coder | |
JPS51144539A (en) | Synchronized method of plural digital circuits | |
JPS5419346A (en) | Digital phase synchronous system | |
SU553754A1 (en) | Device for synchronizing pseudo-random signals | |
JPS56112164A (en) | Phase synchronizing device | |
JPS54122943A (en) | Synchronizing unit |