JPS57116459A - Clock regenerating circuit - Google Patents

Abstract

PURPOSE:To obtain data possibly precise until a phase locked loop is surely synchronized, by switching to a clock reversed in phase to a present regenerated clock when there is phase slip, and by using it as a lock for regeneration. CONSTITUTION:The output of a clock synchronizing circuit 4 is sent to a clock selecting circuit 5 to extract an output clock or its inverted clock (c) selectively, and the clock is sent to an output terminal 3. When there is a phase slip and the digit of digital input data right after it has a ''1'', the output of the FF63 of a phase slip detecting circuit 6 is inverted and at its Q' output terminal, an output (g) with the ''1'' showing the detection of the phase slip appears. A change in the signal inverts the output of the FF71 of a clock selection-signal generating circuit 7 and an output (h) from the output terminal Q goes up to the ''1'' while the output (i) from the terminal Q' is inverted to a ''0''. Consequently, the AND circuit 53 of the circuit 5 is closed and an AND circuit 52 is opened to obtain a clock (c), obtained by inverting the output clock (b) of the circuit 4, as a regenerated clock.