JPH0415649B2 - - Google Patents

Info

Publication number
JPH0415649B2
JPH0415649B2 JP56162837A JP16283781A JPH0415649B2 JP H0415649 B2 JPH0415649 B2 JP H0415649B2 JP 56162837 A JP56162837 A JP 56162837A JP 16283781 A JP16283781 A JP 16283781A JP H0415649 B2 JPH0415649 B2 JP H0415649B2
Authority
JP
Japan
Prior art keywords
circuit
output
edge
signal
falling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56162837A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5864840A (ja
Inventor
Takao Arai
Eiji Ookubo
Hiroshi Endo
Masaharu Kobayashi
Takashi Takeuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56162837A priority Critical patent/JPS5864840A/ja
Priority to US06/422,190 priority patent/US4611335A/en
Priority to GB08227465A priority patent/GB2109203B/en
Priority to DE19823236311 priority patent/DE3236311A1/de
Publication of JPS5864840A publication Critical patent/JPS5864840A/ja
Publication of JPH0415649B2 publication Critical patent/JPH0415649B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/042—Detectors therefor, e.g. correlators, state machines

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP56162837A 1981-09-30 1981-10-14 デ−タ同期回路 Granted JPS5864840A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP56162837A JPS5864840A (ja) 1981-10-14 1981-10-14 デ−タ同期回路
US06/422,190 US4611335A (en) 1981-09-30 1982-09-23 Digital data synchronizing circuit
GB08227465A GB2109203B (en) 1981-09-30 1982-09-27 Digital data synchronizing circuit
DE19823236311 DE3236311A1 (de) 1981-09-30 1982-09-30 Datensynchronisierer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56162837A JPS5864840A (ja) 1981-10-14 1981-10-14 デ−タ同期回路

Publications (2)

Publication Number Publication Date
JPS5864840A JPS5864840A (ja) 1983-04-18
JPH0415649B2 true JPH0415649B2 (enrdf_load_stackoverflow) 1992-03-18

Family

ID=15762182

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56162837A Granted JPS5864840A (ja) 1981-09-30 1981-10-14 デ−タ同期回路

Country Status (1)

Country Link
JP (1) JPS5864840A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3083221B2 (ja) * 1992-11-11 2000-09-04 株式会社日立製作所 ディジタル信号再生装置及びディジタル信号再生方法

Also Published As

Publication number Publication date
JPS5864840A (ja) 1983-04-18

Similar Documents

Publication Publication Date Title
DE69632376T2 (de) Verfahren und Einrichtung zur Dekodierung von Manchester-kodierten Daten
US4851710A (en) Metastable prevent circuit
JPH0220022B2 (enrdf_load_stackoverflow)
US3939438A (en) Phase locked oscillator
US4054747A (en) Data buffer
GB2109203A (en) Digital data synchronizing circuit
US4606053A (en) Bi-phase decoder
JPH0415649B2 (enrdf_load_stackoverflow)
US5159615A (en) Digital frequency detection circuit
US3696401A (en) Digital data decoder with data rate recovery
JP2001503204A (ja) ディジタルコンポーネントビデオ信号の安定性検出の方法および装置
KR910001405B1 (ko) 디지틀신호처리회로 및 그에 대한 신호전송방법
JP2621897B2 (ja) 非同期データ伝送用送信バッファ回路
JPH0418485B2 (enrdf_load_stackoverflow)
JP2591850B2 (ja) フレーム同期回路
JPH0738535A (ja) ノイズ除去回路
JPS5943860B2 (ja) フレ−ム同期信号検出回路
JPS61156977A (ja) 同期信号抽出回路
JP2613916B2 (ja) データ非周期読出し回路
JPH0789653B2 (ja) 水平同期信号処理回路
KR100207644B1 (ko) 섹터동기신호 발생방법 및 장치
JPH0528537B2 (enrdf_load_stackoverflow)
JPH05292075A (ja) デジタル信号記録再生装置の同期信号再生回路
JP3614313B2 (ja) 同期信号検知装置
JPH0585982B2 (enrdf_load_stackoverflow)